LXR linux/arch/arm/mach-s3c24xx/include/mach/regs-clock.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
   4 *      http://armlinux.simtec.co.uk/
   5 *
   6 * S3C2410 clock register definitions
   7 */
   8
   9#ifndef __ASM_ARM_REGS_CLOCK
  10#define __ASM_ARM_REGS_CLOCK
  11
  12#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
  13
  14#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
  15
  16#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
  17#define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
  18#define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
  19#define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
  20#define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
  21#define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
  22
  23#define S3C2410_CLKCON_IDLE          (1<<2)
  24#define S3C2410_CLKCON_POWER         (1<<3)
  25#define S3C2410_CLKCON_NAND          (1<<4)
  26#define S3C2410_CLKCON_LCDC          (1<<5)
  27#define S3C2410_CLKCON_USBH          (1<<6)
  28#define S3C2410_CLKCON_USBD          (1<<7)
  29#define S3C2410_CLKCON_PWMT          (1<<8)
  30#define S3C2410_CLKCON_SDI           (1<<9)
  31#define S3C2410_CLKCON_UART0         (1<<10)
  32#define S3C2410_CLKCON_UART1         (1<<11)
  33#define S3C2410_CLKCON_UART2         (1<<12)
  34#define S3C2410_CLKCON_GPIO          (1<<13)
  35#define S3C2410_CLKCON_RTC           (1<<14)
  36#define S3C2410_CLKCON_ADC           (1<<15)
  37#define S3C2410_CLKCON_IIC           (1<<16)
  38#define S3C2410_CLKCON_IIS           (1<<17)
  39#define S3C2410_CLKCON_SPI           (1<<18)
  40
  41#define S3C2410_CLKDIVN_PDIVN        (1<<0)
  42#define S3C2410_CLKDIVN_HDIVN        (1<<1)
  43
  44#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
  45#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
  46#define S3C2410_CLKSLOW_SLOW            (1<<4)
  47#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
  48#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
  49
  50#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
  51
  52/* extra registers */
  53#define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
  54
  55#define S3C2440_CLKCON_CAMERA        (1<<19)
  56#define S3C2440_CLKCON_AC97          (1<<20)
  57
  58#define S3C2440_CLKDIVN_PDIVN        (1<<0)
  59#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
  60#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
  61#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
  62#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
  63#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
  64#define S3C2440_CLKDIVN_UCLK         (1<<3)
  65
  66#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
  67#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
  68#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
  69#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
  70#define S3C2440_CAMDIVN_DVSEN        (1<<12)
  71
  72#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
  73
  74#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
  75
  76#if defined(CONFIG_CPU_S3C2412)
  77
  78#define S3C2412_OSCSET          S3C2410_CLKREG(0x18)
  79#define S3C2412_CLKSRC          S3C2410_CLKREG(0x1C)
  80
  81#define S3C2412_PLLCON_OFF              (1<<20)
  82
  83#define S3C2412_CLKDIVN_PDIVN           (1<<2)
  84#define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
  85#define S3C2412_CLKDIVN_ARMDIVN         (1<<3)
  86#define S3C2412_CLKDIVN_DVSEN           (1<<4)
  87#define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
  88#define S3C2412_CLKDIVN_USB48DIV        (1<<6)
  89#define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
  90#define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
  91#define S3C2412_CLKDIVN_I2SDIV_MASK     (15<<12)
  92#define S3C2412_CLKDIVN_I2SDIV_SHIFT    (12)
  93#define S3C2412_CLKDIVN_CAMDIV_MASK     (15<<16)
  94#define S3C2412_CLKDIVN_CAMDIV_SHIFT    (16)
  95
  96#define S3C2412_CLKCON_WDT              (1<<28)
  97#define S3C2412_CLKCON_SPI              (1<<27)
  98#define S3C2412_CLKCON_IIS              (1<<26)
  99#define S3C2412_CLKCON_IIC              (1<<25)
 100#define S3C2412_CLKCON_ADC              (1<<24)
 101#define S3C2412_CLKCON_RTC              (1<<23)
 102#define S3C2412_CLKCON_GPIO             (1<<22)
 103#define S3C2412_CLKCON_UART2            (1<<21)
 104#define S3C2412_CLKCON_UART1            (1<<20)
 105#define S3C2412_CLKCON_UART0            (1<<19)
 106#define S3C2412_CLKCON_SDI              (1<<18)
 107#define S3C2412_CLKCON_PWMT             (1<<17)
 108#define S3C2412_CLKCON_USBD             (1<<16)
 109#define S3C2412_CLKCON_CAMCLK           (1<<15)
 110#define S3C2412_CLKCON_UARTCLK          (1<<14)
 111/* missing 13 */
 112#define S3C2412_CLKCON_USB_HOST48       (1<<12)
 113#define S3C2412_CLKCON_USB_DEV48        (1<<11)
 114#define S3C2412_CLKCON_HCLKdiv2         (1<<10)
 115#define S3C2412_CLKCON_HCLKx2           (1<<9)
 116#define S3C2412_CLKCON_SDRAM            (1<<8)
 117/* missing 7 */
 118#define S3C2412_CLKCON_USBH             S3C2410_CLKCON_USBH
 119#define S3C2412_CLKCON_LCDC             S3C2410_CLKCON_LCDC
 120#define S3C2412_CLKCON_NAND             S3C2410_CLKCON_NAND
 121#define S3C2412_CLKCON_DMA3             (1<<3)
 122#define S3C2412_CLKCON_DMA2             (1<<2)
 123#define S3C2412_CLKCON_DMA1             (1<<1)
 124#define S3C2412_CLKCON_DMA0             (1<<0)
 125
 126/* clock sourec controls */
 127
 128#define S3C2412_CLKSRC_EXTCLKDIV_MASK           (7 << 0)
 129#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT          (0)
 130#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV        (1<<3)
 131#define S3C2412_CLKSRC_MSYSCLK_MPLL             (1<<4)
 132#define S3C2412_CLKSRC_USYSCLK_UPLL             (1<<5)
 133#define S3C2412_CLKSRC_UARTCLK_MPLL             (1<<8)
 134#define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
 135#define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
 136#define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
 137#define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
 138#define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
 139
 140#endif /* CONFIG_CPU_S3C2412 */
 141
 142#define S3C2416_CLKDIV2         S3C2410_CLKREG(0x28)
 143
 144#endif /* __ASM_ARM_REGS_CLOCK */
 145