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7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/list.h>
12#include <linux/timer.h>
13#include <linux/init.h>
14#include <linux/gpio.h>
15#include <linux/syscore_ops.h>
16#include <linux/serial_core.h>
17#include <linux/serial_s3c.h>
18#include <linux/platform_device.h>
19#include <linux/dm9000.h>
20#include <linux/ata_platform.h>
21#include <linux/i2c.h>
22#include <linux/io.h>
23#include <linux/serial_8250.h>
24
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/rawnand.h>
27#include <linux/mtd/nand_ecc.h>
28#include <linux/mtd/partitions.h>
29
30#include <linux/platform_data/asoc-s3c24xx_simtec.h>
31#include <linux/platform_data/hwmon-s3c.h>
32#include <linux/platform_data/i2c-s3c2410.h>
33#include <linux/platform_data/mtd-nand-s3c2410.h>
34
35#include <net/ax88796.h>
36
37#include <asm/irq.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41#include <asm/mach-types.h>
42
43#include <mach/fb.h>
44#include <mach/hardware.h>
45#include <mach/regs-gpio.h>
46#include <mach/regs-lcd.h>
47#include <mach/gpio-samsung.h>
48
49#include <plat/cpu.h>
50#include <plat/cpu-freq.h>
51#include <plat/devs.h>
52#include <plat/gpio-cfg.h>
53#include <plat/samsung-time.h>
54
55#include "bast.h"
56#include "common.h"
57#include "simtec.h"
58
59#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
60
61
62#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
63#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
64#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
65#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
66
67
68
69#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
70#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
71#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
72#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
73
74static struct map_desc bast_iodesc[] __initdata = {
75
76 {
77 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
78 .pfn = PA_CS2(BAST_PA_ISAIO),
79 .length = SZ_16M,
80 .type = MT_DEVICE,
81 }, {
82 .virtual = (u32)S3C24XX_VA_ISA_WORD,
83 .pfn = PA_CS3(BAST_PA_ISAIO),
84 .length = SZ_16M,
85 .type = MT_DEVICE,
86 },
87
88 {
89 .virtual = (u32)BAST_VA_CTRL1,
90 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
91 .length = SZ_1M,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (u32)BAST_VA_CTRL2,
95 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
96 .length = SZ_1M,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (u32)BAST_VA_CTRL3,
100 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
101 .length = SZ_1M,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (u32)BAST_VA_CTRL4,
105 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
106 .length = SZ_1M,
107 .type = MT_DEVICE,
108 },
109
110 {
111 .virtual = (u32)BAST_VA_PC104_IRQREQ,
112 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
113 .length = SZ_1M,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (u32)BAST_VA_PC104_IRQRAW,
117 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
118 .length = SZ_1M,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (u32)BAST_VA_PC104_IRQMASK,
122 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
123 .length = SZ_1M,
124 .type = MT_DEVICE,
125 },
126
127
128
129
130
131
132 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
133 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
134 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
135
136
137 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
138 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
139 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
140
141
142 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
145
146
147 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
150};
151
152#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
153#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
154#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
155
156static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
157 [0] = {
158 .hwport = 0,
159 .flags = 0,
160 .ucon = UCON,
161 .ulcon = ULCON,
162 .ufcon = UFCON,
163 },
164 [1] = {
165 .hwport = 1,
166 .flags = 0,
167 .ucon = UCON,
168 .ulcon = ULCON,
169 .ufcon = UFCON,
170 },
171
172 [2] = {
173 .hwport = 2,
174 .flags = 0,
175 .ucon = UCON,
176 .ulcon = ULCON,
177 .ufcon = UFCON,
178 }
179};
180
181
182
183#ifdef CONFIG_PM
184static int bast_pm_suspend(void)
185{
186
187 gpio_direction_output(S3C2410_GPA(21), 1);
188 return 0;
189}
190
191static void bast_pm_resume(void)
192{
193 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
194}
195
196#else
197#define bast_pm_suspend NULL
198#define bast_pm_resume NULL
199#endif
200
201static struct syscore_ops bast_pm_syscore_ops = {
202 .suspend = bast_pm_suspend,
203 .resume = bast_pm_resume,
204};
205
206static int smartmedia_map[] = { 0 };
207static int chip0_map[] = { 1 };
208static int chip1_map[] = { 2 };
209static int chip2_map[] = { 3 };
210
211static struct mtd_partition __initdata bast_default_nand_part[] = {
212 [0] = {
213 .name = "Boot Agent",
214 .size = SZ_16K,
215 .offset = 0,
216 },
217 [1] = {
218 .name = "/boot",
219 .size = SZ_4M - SZ_16K,
220 .offset = SZ_16K,
221 },
222 [2] = {
223 .name = "user",
224 .offset = SZ_4M,
225 .size = MTDPART_SIZ_FULL,
226 }
227};
228
229
230
231
232
233
234
235
236
237static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
238 [0] = {
239 .name = "SmartMedia",
240 .nr_chips = 1,
241 .nr_map = smartmedia_map,
242 .options = NAND_SCAN_SILENT_NODEV,
243 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
244 .partitions = bast_default_nand_part,
245 },
246 [1] = {
247 .name = "chip0",
248 .nr_chips = 1,
249 .nr_map = chip0_map,
250 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
251 .partitions = bast_default_nand_part,
252 },
253 [2] = {
254 .name = "chip1",
255 .nr_chips = 1,
256 .nr_map = chip1_map,
257 .options = NAND_SCAN_SILENT_NODEV,
258 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
259 .partitions = bast_default_nand_part,
260 },
261 [3] = {
262 .name = "chip2",
263 .nr_chips = 1,
264 .nr_map = chip2_map,
265 .options = NAND_SCAN_SILENT_NODEV,
266 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
267 .partitions = bast_default_nand_part,
268 }
269};
270
271static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
272{
273 unsigned int tmp;
274
275 slot = set->nr_map[slot] & 3;
276
277 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
278 slot, set, set->nr_map);
279
280 tmp = __raw_readb(BAST_VA_CTRL2);
281 tmp &= BAST_CPLD_CTLR2_IDERST;
282 tmp |= slot;
283 tmp |= BAST_CPLD_CTRL2_WNAND;
284
285 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
286
287 __raw_writeb(tmp, BAST_VA_CTRL2);
288}
289
290static struct s3c2410_platform_nand __initdata bast_nand_info = {
291 .tacls = 30,
292 .twrph0 = 60,
293 .twrph1 = 60,
294 .nr_sets = ARRAY_SIZE(bast_nand_sets),
295 .sets = bast_nand_sets,
296 .select_chip = bast_nand_select,
297 .ecc_mode = NAND_ECC_SOFT,
298};
299
300
301
302static struct resource bast_dm9k_resource[] = {
303 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
304 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
305 [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
306 | IORESOURCE_IRQ_HIGHLEVEL),
307};
308
309
310
311
312
313static struct dm9000_plat_data bast_dm9k_platdata = {
314 .flags = DM9000_PLATF_16BITONLY,
315};
316
317static struct platform_device bast_device_dm9k = {
318 .name = "dm9000",
319 .id = 0,
320 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
321 .resource = bast_dm9k_resource,
322 .dev = {
323 .platform_data = &bast_dm9k_platdata,
324 }
325};
326
327
328
329#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
330#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
331#define SERIAL_CLK (1843200)
332
333static struct plat_serial8250_port bast_sio_data[] = {
334 [0] = {
335 .mapbase = SERIAL_BASE + 0x2f8,
336 .irq = BAST_IRQ_PCSERIAL1,
337 .flags = SERIAL_FLAGS,
338 .iotype = UPIO_MEM,
339 .regshift = 0,
340 .uartclk = SERIAL_CLK,
341 },
342 [1] = {
343 .mapbase = SERIAL_BASE + 0x3f8,
344 .irq = BAST_IRQ_PCSERIAL2,
345 .flags = SERIAL_FLAGS,
346 .iotype = UPIO_MEM,
347 .regshift = 0,
348 .uartclk = SERIAL_CLK,
349 },
350 { }
351};
352
353static struct platform_device bast_sio = {
354 .name = "serial8250",
355 .id = PLAT8250_DEV_PLATFORM,
356 .dev = {
357 .platform_data = &bast_sio_data,
358 },
359};
360
361
362
363
364
365static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
366 .flags = 0,
367 .slave_addr = 0x10,
368 .frequency = 100*1000,
369};
370
371
372
373static struct ax_plat_data bast_asix_platdata = {
374 .flags = AXFLG_MAC_FROMDEV,
375 .wordlength = 2,
376 .dcr_val = 0x48,
377 .rcr_val = 0x40,
378};
379
380static struct resource bast_asix_resource[] = {
381 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
382 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
383 [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
384};
385
386static struct platform_device bast_device_asix = {
387 .name = "ax88796",
388 .id = 0,
389 .num_resources = ARRAY_SIZE(bast_asix_resource),
390 .resource = bast_asix_resource,
391 .dev = {
392 .platform_data = &bast_asix_platdata
393 }
394};
395
396
397
398static struct resource bast_asixpp_resource[] = {
399 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
400 0x30 * 0x20),
401};
402
403static struct platform_device bast_device_axpp = {
404 .name = "ax88796-pp",
405 .id = 0,
406 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
407 .resource = bast_asixpp_resource,
408};
409
410
411
412static struct s3c2410fb_display __initdata bast_lcd_info[] = {
413 {
414 .type = S3C2410_LCDCON1_TFT,
415 .width = 640,
416 .height = 480,
417
418 .pixclock = 33333,
419 .xres = 640,
420 .yres = 480,
421 .bpp = 4,
422 .left_margin = 40,
423 .right_margin = 20,
424 .hsync_len = 88,
425 .upper_margin = 30,
426 .lower_margin = 32,
427 .vsync_len = 3,
428
429 .lcdcon5 = 0x00014b02,
430 },
431 {
432 .type = S3C2410_LCDCON1_TFT,
433 .width = 640,
434 .height = 480,
435
436 .pixclock = 33333,
437 .xres = 640,
438 .yres = 480,
439 .bpp = 8,
440 .left_margin = 40,
441 .right_margin = 20,
442 .hsync_len = 88,
443 .upper_margin = 30,
444 .lower_margin = 32,
445 .vsync_len = 3,
446
447 .lcdcon5 = 0x00014b02,
448 },
449 {
450 .type = S3C2410_LCDCON1_TFT,
451 .width = 640,
452 .height = 480,
453
454 .pixclock = 33333,
455 .xres = 640,
456 .yres = 480,
457 .bpp = 16,
458 .left_margin = 40,
459 .right_margin = 20,
460 .hsync_len = 88,
461 .upper_margin = 30,
462 .lower_margin = 32,
463 .vsync_len = 3,
464
465 .lcdcon5 = 0x00014b02,
466 },
467};
468
469
470
471static struct s3c2410fb_mach_info __initdata bast_fb_info = {
472
473 .displays = bast_lcd_info,
474 .num_displays = ARRAY_SIZE(bast_lcd_info),
475 .default_display = 1,
476};
477
478
479
480static struct i2c_board_info bast_i2c_devs[] __initdata = {
481 {
482 I2C_BOARD_INFO("tlv320aic23", 0x1a),
483 }, {
484 I2C_BOARD_INFO("simtec-pmu", 0x6b),
485 }, {
486 I2C_BOARD_INFO("ch7013", 0x75),
487 },
488};
489
490static struct s3c_hwmon_pdata bast_hwmon_info = {
491
492 .in[0] = &(struct s3c_hwmon_chcfg) {
493 .name = "lcd-contrast",
494 .mult = 3300,
495 .div = 512,
496 },
497
498 .in[1] = &(struct s3c_hwmon_chcfg) {
499 .name = "led-feedback",
500 .mult = 3300,
501 .div = 1024,
502 },
503
504 .in[2] = &(struct s3c_hwmon_chcfg) {
505 .name = "lcd-feedback",
506 .mult = 3300,
507 .div = 512,
508 },
509
510 .in[3] = &(struct s3c_hwmon_chcfg) {
511 .name = "vcore",
512 .mult = 3300,
513 .div = 1024,
514 },
515};
516
517
518
519
520static struct platform_device *bast_devices[] __initdata = {
521 &s3c2410_device_dclk,
522 &s3c_device_ohci,
523 &s3c_device_lcd,
524 &s3c_device_wdt,
525 &s3c_device_i2c0,
526 &s3c_device_rtc,
527 &s3c_device_nand,
528 &s3c_device_adc,
529 &s3c_device_hwmon,
530 &bast_device_dm9k,
531 &bast_device_asix,
532 &bast_device_axpp,
533 &bast_sio,
534};
535
536static struct s3c_cpufreq_board __initdata bast_cpufreq = {
537 .refresh = 7800,
538 .auto_io = 1,
539 .need_io = 1,
540};
541
542static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
543 .have_mic = 1,
544 .have_lout = 1,
545};
546
547static void __init bast_map_io(void)
548{
549 s3c_hwmon_set_platdata(&bast_hwmon_info);
550
551 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
552 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
553 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
554}
555
556static void __init bast_init_time(void)
557{
558 s3c2410_init_clocks(12000000);
559 samsung_timer_init();
560}
561
562static void __init bast_init(void)
563{
564 register_syscore_ops(&bast_pm_syscore_ops);
565
566 s3c_i2c0_set_platdata(&bast_i2c_info);
567 s3c_nand_set_platdata(&bast_nand_info);
568 s3c24xx_fb_set_platdata(&bast_fb_info);
569 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
570
571 i2c_register_board_info(0, bast_i2c_devs,
572 ARRAY_SIZE(bast_i2c_devs));
573
574 usb_simtec_init();
575 nor_simtec_init();
576 simtec_audio_add(NULL, true, &bast_audio);
577
578 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
579
580 s3c_cpufreq_setboard(&bast_cpufreq);
581}
582
583MACHINE_START(BAST, "Simtec-BAST")
584
585 .atag_offset = 0x100,
586 .map_io = bast_map_io,
587 .init_irq = s3c2410_init_irq,
588 .init_machine = bast_init,
589 .init_time = bast_init_time,
590MACHINE_END
591
