LXR linux/arch/arm/mach-s3c24xx/pm-s3c2410.c

   1// SPDX-License-Identifier: GPL-2.0+
   2//
   3// Copyright (c) 2006 Simtec Electronics
   4//      Ben Dooks <ben@simtec.co.uk>
   5//
   6// S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
   7
   8#include <linux/init.h>
   9#include <linux/suspend.h>
  10#include <linux/errno.h>
  11#include <linux/time.h>
  12#include <linux/device.h>
  13#include <linux/syscore_ops.h>
  14#include <linux/gpio.h>
  15#include <linux/io.h>
  16
  17#include <asm/mach-types.h>
  18
  19#include <mach/hardware.h>
  20#include <mach/regs-gpio.h>
  21#include <mach/gpio-samsung.h>
  22
  23#include <plat/gpio-cfg.h>
  24#include <plat/cpu.h>
  25#include <plat/pm.h>
  26
  27#include "h1940.h"
  28
  29static void s3c2410_pm_prepare(void)
  30{
  31        /* ensure at least GSTATUS3 has the resume address */
  32
  33        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
  34
  35        S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
  36        S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
  37
  38        if (machine_is_h1940()) {
  39                void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  40                unsigned long ptr;
  41                unsigned long calc = 0;
  42
  43                /* generate check for the bootloader to check on resume */
  44
  45                for (ptr = 0; ptr < 0x40000; ptr += 0x400)
  46                        calc += __raw_readl(base+ptr);
  47
  48                __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  49        }
  50
  51        /* RX3715 and RX1950 use similar to H1940 code and the
  52         * same offsets for resume and checksum pointers */
  53
  54        if (machine_is_rx3715() || machine_is_rx1950()) {
  55                void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  56                unsigned long ptr;
  57                unsigned long calc = 0;
  58
  59                /* generate check for the bootloader to check on resume */
  60
  61                for (ptr = 0; ptr < 0x40000; ptr += 0x4)
  62                        calc += __raw_readl(base+ptr);
  63
  64                __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  65        }
  66
  67        if (machine_is_aml_m5900()) {
  68                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
  69                gpio_free(S3C2410_GPF(2));
  70        }
  71
  72        if (machine_is_rx1950()) {
  73                /* According to S3C2442 user's manual, page 7-17,
  74                 * when the system is operating in NAND boot mode,
  75                 * the hardware pin configuration - EINT[23:21] –
  76                 * must be set as input for starting up after
  77                 * wakeup from sleep mode
  78                 */
  79                s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
  80                s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
  81                s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
  82        }
  83}
  84
  85static void s3c2410_pm_resume(void)
  86{
  87        unsigned long tmp;
  88
  89        /* unset the return-from-sleep flag, to ensure reset */
  90
  91        tmp = __raw_readl(S3C2410_GSTATUS2);
  92        tmp &= S3C2410_GSTATUS2_OFFRESET;
  93        __raw_writel(tmp, S3C2410_GSTATUS2);
  94
  95        if (machine_is_aml_m5900()) {
  96                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
  97                gpio_free(S3C2410_GPF(2));
  98        }
  99}
 100
 101struct syscore_ops s3c2410_pm_syscore_ops = {
 102        .resume         = s3c2410_pm_resume,
 103};
 104
 105static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
 106{
 107        pm_cpu_prep = s3c2410_pm_prepare;
 108        pm_cpu_sleep = s3c2410_cpu_suspend;
 109
 110        return 0;
 111}
 112
 113#if defined(CONFIG_CPU_S3C2410)
 114static struct subsys_interface s3c2410_pm_interface = {
 115        .name           = "s3c2410_pm",
 116        .subsys         = &s3c2410_subsys,
 117        .add_dev        = s3c2410_pm_add,
 118};
 119
 120/* register ourselves */
 121
 122static int __init s3c2410_pm_drvinit(void)
 123{
 124        return subsys_interface_register(&s3c2410_pm_interface);
 125}
 126
 127arch_initcall(s3c2410_pm_drvinit);
 128
 129static struct subsys_interface s3c2410a_pm_interface = {
 130        .name           = "s3c2410a_pm",
 131        .subsys         = &s3c2410a_subsys,
 132        .add_dev        = s3c2410_pm_add,
 133};
 134
 135static int __init s3c2410a_pm_drvinit(void)
 136{
 137        return subsys_interface_register(&s3c2410a_pm_interface);
 138}
 139
 140arch_initcall(s3c2410a_pm_drvinit);
 141#endif
 142
 143#if defined(CONFIG_CPU_S3C2440)
 144static struct subsys_interface s3c2440_pm_interface = {
 145        .name           = "s3c2440_pm",
 146        .subsys         = &s3c2440_subsys,
 147        .add_dev        = s3c2410_pm_add,
 148};
 149
 150static int __init s3c2440_pm_drvinit(void)
 151{
 152        return subsys_interface_register(&s3c2440_pm_interface);
 153}
 154
 155arch_initcall(s3c2440_pm_drvinit);
 156#endif
 157
 158#if defined(CONFIG_CPU_S3C2442)
 159static struct subsys_interface s3c2442_pm_interface = {
 160        .name           = "s3c2442_pm",
 161        .subsys         = &s3c2442_subsys,
 162        .add_dev        = s3c2410_pm_add,
 163};
 164
 165static int __init s3c2442_pm_drvinit(void)
 166{
 167        return subsys_interface_register(&s3c2442_pm_interface);
 168}
 169
 170arch_initcall(s3c2442_pm_drvinit);
 171#endif
 172