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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irqchip.h>
12#include <linux/irqchip/arm-gic.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/time.h>
17
18#include "common.h"
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24
25
26#define MEBUFCNTR 0xFE950098
27static void __init r8a7740_meram_workaround(void)
28{
29 void __iomem *reg;
30
31 reg = ioremap_nocache(MEBUFCNTR, 4);
32 if (reg) {
33 iowrite32(0x01600164, reg);
34 iounmap(reg);
35 }
36}
37
38static void __init r8a7740_init_irq_of(void)
39{
40 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
41 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
42 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
43
44 irqchip_init();
45
46
47 iowrite32(0x0, pfc_inta_ctrl);
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53
54 iowrite32(0x0, intc_prio_base + 0x0);
55 iowrite32(0x0, intc_prio_base + 0x4);
56 iowrite32(0x0, intc_prio_base + 0x8);
57 iowrite32(0x0, intc_prio_base + 0xc);
58 iowrite8(0xff, intc_msk_base + 0x0);
59 iowrite8(0xff, intc_msk_base + 0x4);
60 iowrite8(0xff, intc_msk_base + 0x8);
61 iowrite8(0xff, intc_msk_base + 0xc);
62
63 iounmap(intc_prio_base);
64 iounmap(intc_msk_base);
65 iounmap(pfc_inta_ctrl);
66}
67
68static void __init r8a7740_generic_init(void)
69{
70 r8a7740_meram_workaround();
71}
72
73static const char *const r8a7740_boards_compat_dt[] __initconst = {
74 "renesas,r8a7740",
75 NULL,
76};
77
78DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
79 .l2c_aux_val = 0,
80 .l2c_aux_mask = ~0,
81 .init_early = shmobile_init_delay,
82 .init_irq = r8a7740_init_irq_of,
83 .init_machine = r8a7740_generic_init,
84 .init_late = shmobile_init_late,
85 .dt_compat = r8a7740_boards_compat_dt,
86MACHINE_END
87