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14#include <linux/arm-cci.h>
15#include <linux/cpu_pm.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/irqchip/arm-gic.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/smp.h>
24
25#include <asm/cacheflush.h>
26#include <asm/cp15.h>
27#include <asm/cputype.h>
28#include <asm/idmap.h>
29#include <asm/smp_plat.h>
30#include <asm/suspend.h>
31
32#define SUNXI_CPUS_PER_CLUSTER 4
33#define SUNXI_NR_CLUSTERS 2
34
35#define POLL_USEC 100
36#define TIMEOUT_USEC 100000
37
38#define CPUCFG_CX_CTRL_REG0(c) (0x10 * (c))
39#define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n)
40#define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL 0xf
41#define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4)
42#define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0)
43#define CPUCFG_CX_CTRL_REG1(c) (0x10 * (c) + 0x4)
44#define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0)
45#define CPUCFG_CX_STATUS(c) (0x30 + 0x4 * (c))
46#define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n))
47#define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0)
48#define CPUCFG_CX_RST_CTRL(c) (0x80 + 0x4 * (c))
49#define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24)
50#define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n))
51#define CPUCFG_CX_RST_CTRL_ETM_RST_ALL (0xf << 20)
52#define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n))
53#define CPUCFG_CX_RST_CTRL_DBG_RST_ALL (0xf << 16)
54#define CPUCFG_CX_RST_CTRL_H_RST BIT(12)
55#define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
56#define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
57#define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
58#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
59
60#define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c))
61#define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
62#define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
63#define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
64
65#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0)
66#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4)
67#define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
68#define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu))
69#define PRCM_CPU_SOFT_ENTRY_REG 0x164
70
71
72#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
73#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n)
74#define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4
75
76#define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F
77#define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A
78
79static void __iomem *cpucfg_base;
80static void __iomem *prcm_base;
81static void __iomem *sram_b_smp_base;
82static void __iomem *r_cpucfg_base;
83
84extern void sunxi_mc_smp_secondary_startup(void);
85extern void sunxi_mc_smp_resume(void);
86static bool is_a83t;
87
88static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
89{
90 struct device_node *node;
91 int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
92 bool is_compatible;
93
94 node = of_cpu_device_node_get(cpu);
95
96
97 if (!node)
98 node = of_get_cpu_node(cpu, NULL);
99
100 if (!node) {
101
102
103
104
105 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
106 __func__, cluster, core);
107
108 return false;
109 }
110
111 is_compatible = of_device_is_compatible(node, "arm,cortex-a15");
112 of_node_put(node);
113 return is_compatible;
114}
115
116static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
117 bool enable)
118{
119 u32 reg;
120
121
122 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
123 if (enable) {
124 if (reg == 0x00) {
125 pr_debug("power clamp for cluster %u cpu %u already open\n",
126 cluster, cpu);
127 return 0;
128 }
129
130 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
131 udelay(10);
132 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
133 udelay(10);
134 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
135 udelay(10);
136 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
137 udelay(10);
138 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
139 udelay(10);
140 } else {
141 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
142 udelay(10);
143 }
144
145 return 0;
146}
147
148static void sunxi_cpu0_hotplug_support_set(bool enable)
149{
150 if (enable) {
151 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
152 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
153 } else {
154 writel(0x0, sram_b_smp_base);
155 writel(0x0, sram_b_smp_base + 0x4);
156 }
157}
158
159static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
160{
161 u32 reg;
162
163 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
164 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
165 return -EINVAL;
166
167
168 if (cluster == 0 && cpu == 0)
169 sunxi_cpu0_hotplug_support_set(true);
170
171
172 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
173 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
174 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
175
176 if (is_a83t) {
177
178 reg = readl(r_cpucfg_base +
179 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
180 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
181 writel(reg, r_cpucfg_base +
182 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
183 udelay(10);
184 }
185
186
187 if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
188 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
189 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu);
190 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
191 }
192
193
194 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
195 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
196
197
198
199
200
201 if (!sunxi_core_is_cortex_a15(cpu, cluster))
202 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
203
204 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
205
206
207 sunxi_cpu_power_switch_set(cpu, cluster, true);
208
209
210 if (is_a83t) {
211 if (cpu == 0)
212 cpu = 4;
213 }
214
215
216 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
217 reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
218 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
219 udelay(20);
220
221
222 if (is_a83t) {
223 if (cpu == 4)
224 cpu = 0;
225 }
226
227
228 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
229 reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
230 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
231
232 if (is_a83t) {
233 reg = readl(r_cpucfg_base +
234 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
235 reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
236 writel(reg, r_cpucfg_base +
237 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
238 udelay(10);
239 }
240
241
242 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
243 reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
244 reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu);
245 if (!sunxi_core_is_cortex_a15(cpu, cluster))
246 reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
247 else
248 reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu);
249 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
250
251 return 0;
252}
253
254static int sunxi_cluster_powerup(unsigned int cluster)
255{
256 u32 reg;
257
258 pr_debug("%s: cluster %u\n", __func__, cluster);
259 if (cluster >= SUNXI_NR_CLUSTERS)
260 return -EINVAL;
261
262
263 if (is_a83t) {
264 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
265 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
266 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
267 udelay(10);
268 }
269
270
271 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
272 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
273 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
274
275
276 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
277 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
278 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
279
280
281 if (is_a83t) {
282 reg = readl(r_cpucfg_base +
283 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
284 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
285 writel(reg, r_cpucfg_base +
286 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
287 udelay(10);
288 }
289
290
291 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
292 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
293 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL;
294 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
295 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
296
297
298
299
300
301 if (!sunxi_core_is_cortex_a15(0, cluster))
302 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL;
303
304 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
305
306
307 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
308 if (sunxi_core_is_cortex_a15(0, cluster)) {
309
310 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15;
311 } else {
312
313 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL;
314 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7;
315 }
316 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
317
318
319 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
320 if (is_a83t)
321 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
322 else
323 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
324 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
325 udelay(20);
326
327
328 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
329 reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
330 reg |= CPUCFG_CX_RST_CTRL_H_RST;
331 reg |= CPUCFG_CX_RST_CTRL_L2_RST;
332 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
333
334
335 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
336 reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM;
337 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
338
339 return 0;
340}
341
342
343
344
345
346static void sunxi_cluster_cache_disable_without_axi(void)
347{
348 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
349
350
351
352
353 asm volatile(
354 "mcr p15, 1, %0, c15, c0, 3\n"
355 "isb\n"
356 "dsb"
357 : : "r" (0x400));
358 }
359
360
361 v7_exit_coherency_flush(all);
362
363
364
365
366
367 cci_disable_port_by_cpu(read_cpuid_mpidr());
368}
369
370static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
371int sunxi_mc_smp_first_comer;
372
373static DEFINE_SPINLOCK(boot_lock);
374
375static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
376{
377 int i;
378
379 for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++)
380 if (sunxi_mc_smp_cpu_table[cluster][i])
381 return false;
382 return true;
383}
384
385static void sunxi_mc_smp_secondary_init(unsigned int cpu)
386{
387
388 if (cpu == 0)
389 sunxi_cpu0_hotplug_support_set(false);
390}
391
392static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
393{
394 unsigned int mpidr, cpu, cluster;
395
396 mpidr = cpu_logical_map(l_cpu);
397 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
398 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
399
400 if (!cpucfg_base)
401 return -ENODEV;
402 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
403 return -EINVAL;
404
405 spin_lock_irq(&boot_lock);
406
407 if (sunxi_mc_smp_cpu_table[cluster][cpu])
408 goto out;
409
410 if (sunxi_mc_smp_cluster_is_down(cluster)) {
411 sunxi_mc_smp_first_comer = true;
412 sunxi_cluster_powerup(cluster);
413 } else {
414 sunxi_mc_smp_first_comer = false;
415 }
416
417
418 sync_cache_w(&sunxi_mc_smp_first_comer);
419 sunxi_cpu_powerup(cpu, cluster);
420
421out:
422 sunxi_mc_smp_cpu_table[cluster][cpu]++;
423 spin_unlock_irq(&boot_lock);
424
425 return 0;
426}
427
428#ifdef CONFIG_HOTPLUG_CPU
429static void sunxi_cluster_cache_disable(void)
430{
431 unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
432 u32 reg;
433
434 pr_debug("%s: cluster %u\n", __func__, cluster);
435
436 sunxi_cluster_cache_disable_without_axi();
437
438
439 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
440 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
441 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
442}
443
444static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
445{
446 unsigned int mpidr, cpu, cluster;
447 bool last_man;
448
449 mpidr = cpu_logical_map(l_cpu);
450 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
451 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
452 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
453
454 spin_lock(&boot_lock);
455 sunxi_mc_smp_cpu_table[cluster][cpu]--;
456 if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
457
458 pr_debug("%s: aborting due to a power up request\n",
459 __func__);
460 spin_unlock(&boot_lock);
461 return;
462 } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
463 pr_err("Cluster %d CPU%d boots multiple times\n",
464 cluster, cpu);
465 BUG();
466 }
467
468 last_man = sunxi_mc_smp_cluster_is_down(cluster);
469 spin_unlock(&boot_lock);
470
471 gic_cpu_if_down(0);
472 if (last_man)
473 sunxi_cluster_cache_disable();
474 else
475 v7_exit_coherency_flush(louis);
476
477 for (;;)
478 wfi();
479}
480
481static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
482{
483 u32 reg;
484
485 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
486 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
487 return -EINVAL;
488
489
490 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
491 reg |= PRCM_PWROFF_GATING_REG_CORE(cpu);
492 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
493 udelay(20);
494
495
496 sunxi_cpu_power_switch_set(cpu, cluster, false);
497
498 return 0;
499}
500
501static int sunxi_cluster_powerdown(unsigned int cluster)
502{
503 u32 reg;
504
505 pr_debug("%s: cluster %u\n", __func__, cluster);
506 if (cluster >= SUNXI_NR_CLUSTERS)
507 return -EINVAL;
508
509
510 pr_debug("%s: assert cluster reset\n", __func__);
511 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
512 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
513 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
514 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
515 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
516
517
518 pr_debug("%s: gate cluster power\n", __func__);
519 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
520 if (is_a83t)
521 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
522 else
523 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
524 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
525 udelay(20);
526
527 return 0;
528}
529
530static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
531{
532 unsigned int mpidr, cpu, cluster;
533 unsigned int tries, count;
534 int ret = 0;
535 u32 reg;
536
537 mpidr = cpu_logical_map(l_cpu);
538 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
539 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
540
541
542 if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
543 cpu >= SUNXI_CPUS_PER_CLUSTER))
544 return 0;
545
546
547 count = TIMEOUT_USEC / POLL_USEC;
548 spin_lock_irq(&boot_lock);
549 for (tries = 0; tries < count; tries++) {
550 spin_unlock_irq(&boot_lock);
551 usleep_range(POLL_USEC / 2, POLL_USEC);
552 spin_lock_irq(&boot_lock);
553
554
555
556
557
558
559
560
561 if (sunxi_mc_smp_cpu_table[cluster][cpu])
562 continue;
563
564 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
565 if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu))
566 break;
567 }
568
569 if (tries >= count) {
570 ret = ETIMEDOUT;
571 goto out;
572 }
573
574
575 sunxi_cpu_powerdown(cpu, cluster);
576
577 if (!sunxi_mc_smp_cluster_is_down(cluster))
578 goto out;
579
580
581 ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
582 reg & CPUCFG_CX_STATUS_STANDBYWFIL2,
583 POLL_USEC, TIMEOUT_USEC);
584 if (ret) {
585
586
587
588
589
590
591 ret = 0;
592 goto out;
593 }
594
595
596 sunxi_cluster_powerdown(cluster);
597
598out:
599 spin_unlock_irq(&boot_lock);
600 pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
601 __func__, cluster, cpu, ret);
602 return !ret;
603}
604
605static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
606{
607
608 if (is_a83t)
609 if (cpu == 0)
610 return false;
611 return true;
612}
613#endif
614
615static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = {
616 .smp_secondary_init = sunxi_mc_smp_secondary_init,
617 .smp_boot_secondary = sunxi_mc_smp_boot_secondary,
618#ifdef CONFIG_HOTPLUG_CPU
619 .cpu_die = sunxi_mc_smp_cpu_die,
620 .cpu_kill = sunxi_mc_smp_cpu_kill,
621 .cpu_can_disable = sunxi_mc_smp_cpu_can_disable,
622#endif
623};
624
625static bool __init sunxi_mc_smp_cpu_table_init(void)
626{
627 unsigned int mpidr, cpu, cluster;
628
629 mpidr = read_cpuid_mpidr();
630 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
631 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
632
633 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
634 pr_err("%s: boot CPU is out of bounds!\n", __func__);
635 return false;
636 }
637 sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
638 return true;
639}
640
641
642
643
644
645
646typedef typeof(cpu_reset) phys_reset_t;
647
648static int __init nocache_trampoline(unsigned long __unused)
649{
650 phys_reset_t phys_reset;
651
652 setup_mm_for_reboot();
653 sunxi_cluster_cache_disable_without_axi();
654
655 phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
656 phys_reset(__pa_symbol(sunxi_mc_smp_resume), false);
657 BUG();
658}
659
660static int __init sunxi_mc_smp_loopback(void)
661{
662 int ret;
663
664
665
666
667
668
669
670 sunxi_mc_smp_first_comer = true;
671 local_irq_disable();
672 local_fiq_disable();
673 ret = cpu_pm_enter();
674 if (!ret) {
675 ret = cpu_suspend(0, nocache_trampoline);
676 cpu_pm_exit();
677 }
678 local_fiq_enable();
679 local_irq_enable();
680 sunxi_mc_smp_first_comer = false;
681
682 return ret;
683}
684
685
686
687
688
689struct sunxi_mc_smp_nodes {
690 struct device_node *prcm_node;
691 struct device_node *cpucfg_node;
692 struct device_node *sram_node;
693 struct device_node *r_cpucfg_node;
694};
695
696
697struct sunxi_mc_smp_data {
698 const char *enable_method;
699 int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
700 bool is_a83t;
701};
702
703static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
704{
705 of_node_put(nodes->prcm_node);
706 of_node_put(nodes->cpucfg_node);
707 of_node_put(nodes->sram_node);
708 of_node_put(nodes->r_cpucfg_node);
709 memset(nodes, 0, sizeof(*nodes));
710}
711
712static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
713{
714 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
715 "allwinner,sun9i-a80-prcm");
716 if (!nodes->prcm_node) {
717 pr_err("%s: PRCM not available\n", __func__);
718 return -ENODEV;
719 }
720
721 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
722 "allwinner,sun9i-a80-cpucfg");
723 if (!nodes->cpucfg_node) {
724 pr_err("%s: CPUCFG not available\n", __func__);
725 return -ENODEV;
726 }
727
728 nodes->sram_node = of_find_compatible_node(NULL, NULL,
729 "allwinner,sun9i-a80-smp-sram");
730 if (!nodes->sram_node) {
731 pr_err("%s: Secure SRAM not available\n", __func__);
732 return -ENODEV;
733 }
734
735 return 0;
736}
737
738static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
739{
740 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
741 "allwinner,sun8i-a83t-r-ccu");
742 if (!nodes->prcm_node) {
743 pr_err("%s: PRCM not available\n", __func__);
744 return -ENODEV;
745 }
746
747 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
748 "allwinner,sun8i-a83t-cpucfg");
749 if (!nodes->cpucfg_node) {
750 pr_err("%s: CPUCFG not available\n", __func__);
751 return -ENODEV;
752 }
753
754 nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
755 "allwinner,sun8i-a83t-r-cpucfg");
756 if (!nodes->r_cpucfg_node) {
757 pr_err("%s: RCPUCFG not available\n", __func__);
758 return -ENODEV;
759 }
760
761 return 0;
762}
763
764static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
765 {
766 .enable_method = "allwinner,sun9i-a80-smp",
767 .get_smp_nodes = sun9i_a80_get_smp_nodes,
768 },
769 {
770 .enable_method = "allwinner,sun8i-a83t-smp",
771 .get_smp_nodes = sun8i_a83t_get_smp_nodes,
772 .is_a83t = true,
773 },
774};
775
776static int __init sunxi_mc_smp_init(void)
777{
778 struct sunxi_mc_smp_nodes nodes = { 0 };
779 struct device_node *node;
780 struct resource res;
781 void __iomem *addr;
782 int i, ret;
783
784
785
786
787
788 node = of_cpu_device_node_get(0);
789 if (!node)
790 return -ENODEV;
791
792
793
794
795
796
797
798
799
800 for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
801 ret = of_property_match_string(node, "enable-method",
802 sunxi_mc_smp_data[i].enable_method);
803 if (!ret)
804 break;
805 }
806
807 is_a83t = sunxi_mc_smp_data[i].is_a83t;
808
809 of_node_put(node);
810 if (ret)
811 return -ENODEV;
812
813 if (!sunxi_mc_smp_cpu_table_init())
814 return -EINVAL;
815
816 if (!cci_probed()) {
817 pr_err("%s: CCI-400 not available\n", __func__);
818 return -ENODEV;
819 }
820
821
822 ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes);
823 if (ret)
824 goto err_put_nodes;
825
826
827
828
829
830 prcm_base = of_iomap(nodes.prcm_node, 0);
831 if (!prcm_base) {
832 pr_err("%s: failed to map PRCM registers\n", __func__);
833 ret = -ENOMEM;
834 goto err_put_nodes;
835 }
836
837 cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0,
838 "sunxi-mc-smp");
839 if (IS_ERR(cpucfg_base)) {
840 ret = PTR_ERR(cpucfg_base);
841 pr_err("%s: failed to map CPUCFG registers: %d\n",
842 __func__, ret);
843 goto err_unmap_prcm;
844 }
845
846 if (is_a83t) {
847 r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
848 0, "sunxi-mc-smp");
849 if (IS_ERR(r_cpucfg_base)) {
850 ret = PTR_ERR(r_cpucfg_base);
851 pr_err("%s: failed to map R-CPUCFG registers\n",
852 __func__);
853 goto err_unmap_release_cpucfg;
854 }
855 } else {
856 sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
857 "sunxi-mc-smp");
858 if (IS_ERR(sram_b_smp_base)) {
859 ret = PTR_ERR(sram_b_smp_base);
860 pr_err("%s: failed to map secure SRAM\n", __func__);
861 goto err_unmap_release_cpucfg;
862 }
863 }
864
865
866 ret = sunxi_mc_smp_loopback();
867 if (ret) {
868 pr_err("%s: failed to configure boot cluster: %d\n",
869 __func__, ret);
870 goto err_unmap_release_sram_rcpucfg;
871 }
872
873
874 sunxi_mc_smp_put_nodes(&nodes);
875
876
877 if (is_a83t)
878 addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
879 else
880 addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
881 writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
882
883
884 smp_set_ops(&sunxi_mc_smp_smp_ops);
885
886 pr_info("sunxi multi cluster SMP support installed\n");
887
888 return 0;
889
890err_unmap_release_sram_rcpucfg:
891 if (is_a83t) {
892 iounmap(r_cpucfg_base);
893 of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
894 } else {
895 iounmap(sram_b_smp_base);
896 of_address_to_resource(nodes.sram_node, 0, &res);
897 }
898 release_mem_region(res.start, resource_size(&res));
899err_unmap_release_cpucfg:
900 iounmap(cpucfg_base);
901 of_address_to_resource(nodes.cpucfg_node, 0, &res);
902 release_mem_region(res.start, resource_size(&res));
903err_unmap_prcm:
904 iounmap(prcm_base);
905err_put_nodes:
906 sunxi_mc_smp_put_nodes(&nodes);
907 return ret;
908}
909
910early_initcall(sunxi_mc_smp_init);
911