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5
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/mman.h>
12#include <linux/nodemask.h>
13#include <linux/memblock.h>
14#include <linux/fs.h>
15#include <linux/vmalloc.h>
16#include <linux/sizes.h>
17
18#include <asm/cp15.h>
19#include <asm/cputype.h>
20#include <asm/sections.h>
21#include <asm/cachetype.h>
22#include <asm/fixmap.h>
23#include <asm/sections.h>
24#include <asm/setup.h>
25#include <asm/smp_plat.h>
26#include <asm/tlb.h>
27#include <asm/highmem.h>
28#include <asm/system_info.h>
29#include <asm/traps.h>
30#include <asm/procinfo.h>
31#include <asm/memory.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/pci.h>
36#include <asm/fixmap.h>
37
38#include "fault.h"
39#include "mm.h"
40#include "tcm.h"
41
42
43
44
45
46struct page *empty_zero_page;
47EXPORT_SYMBOL(empty_zero_page);
48
49
50
51
52pmd_t *top_pmd;
53
54pmdval_t user_pmd_table = _PAGE_USER_TABLE;
55
56#define CPOLICY_UNCACHED 0
57#define CPOLICY_BUFFERED 1
58#define CPOLICY_WRITETHROUGH 2
59#define CPOLICY_WRITEBACK 3
60#define CPOLICY_WRITEALLOC 4
61
62static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
63static unsigned int ecc_mask __initdata = 0;
64pgprot_t pgprot_user;
65pgprot_t pgprot_kernel;
66pgprot_t pgprot_hyp_device;
67pgprot_t pgprot_s2;
68pgprot_t pgprot_s2_device;
69
70EXPORT_SYMBOL(pgprot_user);
71EXPORT_SYMBOL(pgprot_kernel);
72
73struct cachepolicy {
74 const char policy[16];
75 unsigned int cr_mask;
76 pmdval_t pmd;
77 pteval_t pte;
78 pteval_t pte_s2;
79};
80
81#ifdef CONFIG_ARM_LPAE
82#define s2_policy(policy) policy
83#else
84#define s2_policy(policy) 0
85#endif
86
87unsigned long kimage_voffset __ro_after_init;
88
89static struct cachepolicy cache_policies[] __initdata = {
90 {
91 .policy = "uncached",
92 .cr_mask = CR_W|CR_C,
93 .pmd = PMD_SECT_UNCACHED,
94 .pte = L_PTE_MT_UNCACHED,
95 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
96 }, {
97 .policy = "buffered",
98 .cr_mask = CR_C,
99 .pmd = PMD_SECT_BUFFERED,
100 .pte = L_PTE_MT_BUFFERABLE,
101 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
102 }, {
103 .policy = "writethrough",
104 .cr_mask = 0,
105 .pmd = PMD_SECT_WT,
106 .pte = L_PTE_MT_WRITETHROUGH,
107 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
108 }, {
109 .policy = "writeback",
110 .cr_mask = 0,
111 .pmd = PMD_SECT_WB,
112 .pte = L_PTE_MT_WRITEBACK,
113 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
114 }, {
115 .policy = "writealloc",
116 .cr_mask = 0,
117 .pmd = PMD_SECT_WBWA,
118 .pte = L_PTE_MT_WRITEALLOC,
119 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
120 }
121};
122
123#ifdef CONFIG_CPU_CP15
124static unsigned long initial_pmd_value __initdata = 0;
125
126
127
128
129
130
131
132
133void __init init_default_cache_policy(unsigned long pmd)
134{
135 int i;
136
137 initial_pmd_value = pmd;
138
139 pmd &= PMD_SECT_CACHE_MASK;
140
141 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
142 if (cache_policies[i].pmd == pmd) {
143 cachepolicy = i;
144 break;
145 }
146
147 if (i == ARRAY_SIZE(cache_policies))
148 pr_err("ERROR: could not find cache policy\n");
149}
150
151
152
153
154
155
156static int __init early_cachepolicy(char *p)
157{
158 int i, selected = -1;
159
160 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
161 int len = strlen(cache_policies[i].policy);
162
163 if (memcmp(p, cache_policies[i].policy, len) == 0) {
164 selected = i;
165 break;
166 }
167 }
168
169 if (selected == -1)
170 pr_err("ERROR: unknown or unsupported cache policy\n");
171
172
173
174
175
176
177
178
179 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
180 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
181 cache_policies[cachepolicy].policy);
182 return 0;
183 }
184
185 if (selected != cachepolicy) {
186 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
187 cachepolicy = selected;
188 flush_cache_all();
189 set_cr(cr);
190 }
191 return 0;
192}
193early_param("cachepolicy", early_cachepolicy);
194
195static int __init early_nocache(char *__unused)
196{
197 char *p = "buffered";
198 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
199 early_cachepolicy(p);
200 return 0;
201}
202early_param("nocache", early_nocache);
203
204static int __init early_nowrite(char *__unused)
205{
206 char *p = "uncached";
207 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
208 early_cachepolicy(p);
209 return 0;
210}
211early_param("nowb", early_nowrite);
212
213#ifndef CONFIG_ARM_LPAE
214static int __init early_ecc(char *p)
215{
216 if (memcmp(p, "on", 2) == 0)
217 ecc_mask = PMD_PROTECTION;
218 else if (memcmp(p, "off", 3) == 0)
219 ecc_mask = 0;
220 return 0;
221}
222early_param("ecc", early_ecc);
223#endif
224
225#else
226
227static int __init early_cachepolicy(char *p)
228{
229 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
230}
231early_param("cachepolicy", early_cachepolicy);
232
233static int __init noalign_setup(char *__unused)
234{
235 pr_warn("noalign kernel parameter not supported without cp15\n");
236}
237__setup("noalign", noalign_setup);
238
239#endif
240
241#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
242#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
243#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
244
245static struct mem_type mem_types[] __ro_after_init = {
246 [MT_DEVICE] = {
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
248 L_PTE_SHARED,
249 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
250 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
251 L_PTE_SHARED,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
254 .domain = DOMAIN_IO,
255 },
256 [MT_DEVICE_NONSHARED] = {
257 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
258 .prot_l1 = PMD_TYPE_TABLE,
259 .prot_sect = PROT_SECT_DEVICE,
260 .domain = DOMAIN_IO,
261 },
262 [MT_DEVICE_CACHED] = {
263 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
264 .prot_l1 = PMD_TYPE_TABLE,
265 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
266 .domain = DOMAIN_IO,
267 },
268 [MT_DEVICE_WC] = {
269 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .prot_sect = PROT_SECT_DEVICE,
272 .domain = DOMAIN_IO,
273 },
274 [MT_UNCACHED] = {
275 .prot_pte = PROT_PTE_DEVICE,
276 .prot_l1 = PMD_TYPE_TABLE,
277 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
278 .domain = DOMAIN_IO,
279 },
280 [MT_CACHECLEAN] = {
281 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
282 .domain = DOMAIN_KERNEL,
283 },
284#ifndef CONFIG_ARM_LPAE
285 [MT_MINICLEAN] = {
286 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
287 .domain = DOMAIN_KERNEL,
288 },
289#endif
290 [MT_LOW_VECTORS] = {
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
292 L_PTE_RDONLY,
293 .prot_l1 = PMD_TYPE_TABLE,
294 .domain = DOMAIN_VECTORS,
295 },
296 [MT_HIGH_VECTORS] = {
297 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
298 L_PTE_USER | L_PTE_RDONLY,
299 .prot_l1 = PMD_TYPE_TABLE,
300 .domain = DOMAIN_VECTORS,
301 },
302 [MT_MEMORY_RWX] = {
303 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
307 },
308 [MT_MEMORY_RW] = {
309 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
310 L_PTE_XN,
311 .prot_l1 = PMD_TYPE_TABLE,
312 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
313 .domain = DOMAIN_KERNEL,
314 },
315 [MT_ROM] = {
316 .prot_sect = PMD_TYPE_SECT,
317 .domain = DOMAIN_KERNEL,
318 },
319 [MT_MEMORY_RWX_NONCACHED] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_MT_BUFFERABLE,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
324 .domain = DOMAIN_KERNEL,
325 },
326 [MT_MEMORY_RW_DTCM] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
328 L_PTE_XN,
329 .prot_l1 = PMD_TYPE_TABLE,
330 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_MEMORY_RWX_ITCM] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
335 .prot_l1 = PMD_TYPE_TABLE,
336 .domain = DOMAIN_KERNEL,
337 },
338 [MT_MEMORY_RW_SO] = {
339 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
340 L_PTE_MT_UNCACHED | L_PTE_XN,
341 .prot_l1 = PMD_TYPE_TABLE,
342 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
343 PMD_SECT_UNCACHED | PMD_SECT_XN,
344 .domain = DOMAIN_KERNEL,
345 },
346 [MT_MEMORY_DMA_READY] = {
347 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
348 L_PTE_XN,
349 .prot_l1 = PMD_TYPE_TABLE,
350 .domain = DOMAIN_KERNEL,
351 },
352};
353
354const struct mem_type *get_mem_type(unsigned int type)
355{
356 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
357}
358EXPORT_SYMBOL(get_mem_type);
359
360static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
361
362static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
363 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
364
365static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
366{
367 return &bm_pte[pte_index(addr)];
368}
369
370static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
371{
372 return pte_offset_kernel(dir, addr);
373}
374
375static inline pmd_t * __init fixmap_pmd(unsigned long addr)
376{
377 pgd_t *pgd = pgd_offset_k(addr);
378 pud_t *pud = pud_offset(pgd, addr);
379 pmd_t *pmd = pmd_offset(pud, addr);
380
381 return pmd;
382}
383
384void __init early_fixmap_init(void)
385{
386 pmd_t *pmd;
387
388
389
390
391
392 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
393 != FIXADDR_TOP >> PMD_SHIFT);
394
395 pmd = fixmap_pmd(FIXADDR_TOP);
396 pmd_populate_kernel(&init_mm, pmd, bm_pte);
397
398 pte_offset_fixmap = pte_offset_early_fixmap;
399}
400
401
402
403
404
405
406void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
407{
408 unsigned long vaddr = __fix_to_virt(idx);
409 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
410
411
412 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
413 FIXADDR_END);
414 BUG_ON(idx >= __end_of_fixed_addresses);
415
416
417 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
418 pgprot_val(pgprot_kernel) == 0))
419 return;
420
421 if (pgprot_val(prot))
422 set_pte_at(NULL, vaddr, pte,
423 pfn_pte(phys >> PAGE_SHIFT, prot));
424 else
425 pte_clear(NULL, vaddr, pte);
426 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
427}
428
429
430
431
432static void __init build_mem_type_table(void)
433{
434 struct cachepolicy *cp;
435 unsigned int cr = get_cr();
436 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
437 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
438 int cpu_arch = cpu_architecture();
439 int i;
440
441 if (cpu_arch < CPU_ARCH_ARMv6) {
442#if defined(CONFIG_CPU_DCACHE_DISABLE)
443 if (cachepolicy > CPOLICY_BUFFERED)
444 cachepolicy = CPOLICY_BUFFERED;
445#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
446 if (cachepolicy > CPOLICY_WRITETHROUGH)
447 cachepolicy = CPOLICY_WRITETHROUGH;
448#endif
449 }
450 if (cpu_arch < CPU_ARCH_ARMv5) {
451 if (cachepolicy >= CPOLICY_WRITEALLOC)
452 cachepolicy = CPOLICY_WRITEBACK;
453 ecc_mask = 0;
454 }
455
456 if (is_smp()) {
457 if (cachepolicy != CPOLICY_WRITEALLOC) {
458 pr_warn("Forcing write-allocate cache policy for SMP\n");
459 cachepolicy = CPOLICY_WRITEALLOC;
460 }
461 if (!(initial_pmd_value & PMD_SECT_S)) {
462 pr_warn("Forcing shared mappings for SMP\n");
463 initial_pmd_value |= PMD_SECT_S;
464 }
465 }
466
467
468
469
470
471
472 if (cpu_arch < CPU_ARCH_ARMv5)
473 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
474 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
475 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
476 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
477 mem_types[i].prot_sect &= ~PMD_SECT_S;
478
479
480
481
482
483
484 if (cpu_is_xscale_family()) {
485 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
486 mem_types[i].prot_sect &= ~PMD_BIT4;
487 mem_types[i].prot_l1 &= ~PMD_BIT4;
488 }
489 } else if (cpu_arch < CPU_ARCH_ARMv6) {
490 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
491 if (mem_types[i].prot_l1)
492 mem_types[i].prot_l1 |= PMD_BIT4;
493 if (mem_types[i].prot_sect)
494 mem_types[i].prot_sect |= PMD_BIT4;
495 }
496 }
497
498
499
500
501 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
502 if (!cpu_is_xsc3()) {
503
504
505
506
507 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
508 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
509 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
510 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
511
512
513 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
514 }
515 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
516
517
518
519
520
521
522
523 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
524 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
525 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
526 } else if (cpu_is_xsc3()) {
527
528
529
530
531
532
533
534 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
535 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
536 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
537 } else {
538
539
540
541
542
543
544
545 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
546 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
547 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
548 }
549 } else {
550
551
552
553 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
554 }
555
556
557
558
559 cp = &cache_policies[cachepolicy];
560 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
561 s2_pgprot = cp->pte_s2;
562 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
563 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
564
565#ifndef CONFIG_ARM_LPAE
566
567
568
569
570
571 if (cpu_arch == CPU_ARCH_ARMv6)
572 vecs_pgprot |= L_PTE_MT_VECTORS;
573
574
575
576
577
578 if (cpu_arch == CPU_ARCH_ARMv7 &&
579 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
580 user_pmd_table |= PMD_PXNTABLE;
581 }
582#endif
583
584
585
586
587 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
588#ifndef CONFIG_ARM_LPAE
589
590
591
592
593 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
594 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
595 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
596#endif
597
598
599
600
601
602
603 if (initial_pmd_value & PMD_SECT_S) {
604 user_pgprot |= L_PTE_SHARED;
605 kern_pgprot |= L_PTE_SHARED;
606 vecs_pgprot |= L_PTE_SHARED;
607 s2_pgprot |= L_PTE_SHARED;
608 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
609 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
610 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
611 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
613 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
614 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
615 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
616 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
617 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
619 }
620 }
621
622
623
624
625
626 if (cpu_arch >= CPU_ARCH_ARMv6) {
627 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
628
629 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
630 PMD_SECT_BUFFERED;
631 } else {
632
633 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
634 PMD_SECT_TEX(1);
635 }
636 } else {
637 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
638 }
639
640#ifdef CONFIG_ARM_LPAE
641
642
643
644 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
645 mem_types[i].prot_pte |= PTE_EXT_AF;
646 if (mem_types[i].prot_sect)
647 mem_types[i].prot_sect |= PMD_SECT_AF;
648 }
649 kern_pgprot |= PTE_EXT_AF;
650 vecs_pgprot |= PTE_EXT_AF;
651
652
653
654
655 user_pgprot |= PTE_EXT_PXN;
656#endif
657
658 for (i = 0; i < 16; i++) {
659 pteval_t v = pgprot_val(protection_map[i]);
660 protection_map[i] = __pgprot(v | user_pgprot);
661 }
662
663 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
664 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
665
666 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
667 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
668 L_PTE_DIRTY | kern_pgprot);
669 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
670 pgprot_s2_device = __pgprot(s2_device_pgprot);
671 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
672
673 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
674 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
675 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
676 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
677 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
678 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
679 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
680 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
681 mem_types[MT_ROM].prot_sect |= cp->pmd;
682
683 switch (cp->pmd) {
684 case PMD_SECT_WT:
685 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
686 break;
687 case PMD_SECT_WB:
688 case PMD_SECT_WBWA:
689 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
690 break;
691 }
692 pr_info("Memory policy: %sData cache %s\n",
693 ecc_mask ? "ECC enabled, " : "", cp->policy);
694
695 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
696 struct mem_type *t = &mem_types[i];
697 if (t->prot_l1)
698 t->prot_l1 |= PMD_DOMAIN(t->domain);
699 if (t->prot_sect)
700 t->prot_sect |= PMD_DOMAIN(t->domain);
701 }
702}
703
704#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
705pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
706 unsigned long size, pgprot_t vma_prot)
707{
708 if (!pfn_valid(pfn))
709 return pgprot_noncached(vma_prot);
710 else if (file->f_flags & O_SYNC)
711 return pgprot_writecombine(vma_prot);
712 return vma_prot;
713}
714EXPORT_SYMBOL(phys_mem_access_prot);
715#endif
716
717#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
718
719static void __init *early_alloc(unsigned long sz)
720{
721 void *ptr = memblock_alloc(sz, sz);
722
723 if (!ptr)
724 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
725 __func__, sz, sz);
726
727 return ptr;
728}
729
730static void *__init late_alloc(unsigned long sz)
731{
732 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
733
734 if (!ptr || !pgtable_page_ctor(virt_to_page(ptr)))
735 BUG();
736 return ptr;
737}
738
739static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
740 unsigned long prot,
741 void *(*alloc)(unsigned long sz))
742{
743 if (pmd_none(*pmd)) {
744 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
745 __pmd_populate(pmd, __pa(pte), prot);
746 }
747 BUG_ON(pmd_bad(*pmd));
748 return pte_offset_kernel(pmd, addr);
749}
750
751static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
752 unsigned long prot)
753{
754 return arm_pte_alloc(pmd, addr, prot, early_alloc);
755}
756
757static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
758 unsigned long end, unsigned long pfn,
759 const struct mem_type *type,
760 void *(*alloc)(unsigned long sz),
761 bool ng)
762{
763 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
764 do {
765 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
766 ng ? PTE_EXT_NG : 0);
767 pfn++;
768 } while (pte++, addr += PAGE_SIZE, addr != end);
769}
770
771static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
772 unsigned long end, phys_addr_t phys,
773 const struct mem_type *type, bool ng)
774{
775 pmd_t *p = pmd;
776
777#ifndef CONFIG_ARM_LPAE
778
779
780
781
782
783
784
785
786
787 if (addr & SECTION_SIZE)
788 pmd++;
789#endif
790 do {
791 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
792 phys += SECTION_SIZE;
793 } while (pmd++, addr += SECTION_SIZE, addr != end);
794
795 flush_pmd_entry(p);
796}
797
798static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
799 unsigned long end, phys_addr_t phys,
800 const struct mem_type *type,
801 void *(*alloc)(unsigned long sz), bool ng)
802{
803 pmd_t *pmd = pmd_offset(pud, addr);
804 unsigned long next;
805
806 do {
807
808
809
810
811 next = pmd_addr_end(addr, end);
812
813
814
815
816
817 if (type->prot_sect &&
818 ((addr | next | phys) & ~SECTION_MASK) == 0) {
819 __map_init_section(pmd, addr, next, phys, type, ng);
820 } else {
821 alloc_init_pte(pmd, addr, next,
822 __phys_to_pfn(phys), type, alloc, ng);
823 }
824
825 phys += next - addr;
826
827 } while (pmd++, addr = next, addr != end);
828}
829
830static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
831 unsigned long end, phys_addr_t phys,
832 const struct mem_type *type,
833 void *(*alloc)(unsigned long sz), bool ng)
834{
835 pud_t *pud = pud_offset(pgd, addr);
836 unsigned long next;
837
838 do {
839 next = pud_addr_end(addr, end);
840 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
841 phys += next - addr;
842 } while (pud++, addr = next, addr != end);
843}
844
845#ifndef CONFIG_ARM_LPAE
846static void __init create_36bit_mapping(struct mm_struct *mm,
847 struct map_desc *md,
848 const struct mem_type *type,
849 bool ng)
850{
851 unsigned long addr, length, end;
852 phys_addr_t phys;
853 pgd_t *pgd;
854
855 addr = md->virtual;
856 phys = __pfn_to_phys(md->pfn);
857 length = PAGE_ALIGN(md->length);
858
859 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
860 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
861 (long long)__pfn_to_phys((u64)md->pfn), addr);
862 return;
863 }
864
865
866
867
868
869
870
871 if (type->domain) {
872 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
873 (long long)__pfn_to_phys((u64)md->pfn), addr);
874 return;
875 }
876
877 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
878 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
879 (long long)__pfn_to_phys((u64)md->pfn), addr);
880 return;
881 }
882
883
884
885
886
887 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
888
889 pgd = pgd_offset(mm, addr);
890 end = addr + length;
891 do {
892 pud_t *pud = pud_offset(pgd, addr);
893 pmd_t *pmd = pmd_offset(pud, addr);
894 int i;
895
896 for (i = 0; i < 16; i++)
897 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
898 (ng ? PMD_SECT_nG : 0));
899
900 addr += SUPERSECTION_SIZE;
901 phys += SUPERSECTION_SIZE;
902 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
903 } while (addr != end);
904}
905#endif
906
907static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
908 void *(*alloc)(unsigned long sz),
909 bool ng)
910{
911 unsigned long addr, length, end;
912 phys_addr_t phys;
913 const struct mem_type *type;
914 pgd_t *pgd;
915
916 type = &mem_types[md->type];
917
918#ifndef CONFIG_ARM_LPAE
919
920
921
922 if (md->pfn >= 0x100000) {
923 create_36bit_mapping(mm, md, type, ng);
924 return;
925 }
926#endif
927
928 addr = md->virtual & PAGE_MASK;
929 phys = __pfn_to_phys(md->pfn);
930 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
931
932 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
933 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
934 (long long)__pfn_to_phys(md->pfn), addr);
935 return;
936 }
937
938 pgd = pgd_offset(mm, addr);
939 end = addr + length;
940 do {
941 unsigned long next = pgd_addr_end(addr, end);
942
943 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
944
945 phys += next - addr;
946 addr = next;
947 } while (pgd++, addr != end);
948}
949
950
951
952
953
954
955
956
957static void __init create_mapping(struct map_desc *md)
958{
959 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
960 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
961 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
962 return;
963 }
964
965 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
966 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
967 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
968 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
969 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
970 }
971
972 __create_mapping(&init_mm, md, early_alloc, false);
973}
974
975void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
976 bool ng)
977{
978#ifdef CONFIG_ARM_LPAE
979 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
980 if (WARN_ON(!pud))
981 return;
982 pmd_alloc(mm, pud, 0);
983#endif
984 __create_mapping(mm, md, late_alloc, ng);
985}
986
987
988
989
990void __init iotable_init(struct map_desc *io_desc, int nr)
991{
992 struct map_desc *md;
993 struct vm_struct *vm;
994 struct static_vm *svm;
995
996 if (!nr)
997 return;
998
999 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1000 if (!svm)
1001 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1002 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1003
1004 for (md = io_desc; nr; md++, nr--) {
1005 create_mapping(md);
1006
1007 vm = &svm->vm;
1008 vm->addr = (void *)(md->virtual & PAGE_MASK);
1009 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1010 vm->phys_addr = __pfn_to_phys(md->pfn);
1011 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1012 vm->flags |= VM_ARM_MTYPE(md->type);
1013 vm->caller = iotable_init;
1014 add_static_vm_early(svm++);
1015 }
1016}
1017
1018void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1019 void *caller)
1020{
1021 struct vm_struct *vm;
1022 struct static_vm *svm;
1023
1024 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1025 if (!svm)
1026 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1027 __func__, sizeof(*svm), __alignof__(*svm));
1028
1029 vm = &svm->vm;
1030 vm->addr = (void *)addr;
1031 vm->size = size;
1032 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1033 vm->caller = caller;
1034 add_static_vm_early(svm);
1035}
1036
1037#ifndef CONFIG_ARM_LPAE
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052static void __init pmd_empty_section_gap(unsigned long addr)
1053{
1054 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1055}
1056
1057static void __init fill_pmd_gaps(void)
1058{
1059 struct static_vm *svm;
1060 struct vm_struct *vm;
1061 unsigned long addr, next = 0;
1062 pmd_t *pmd;
1063
1064 list_for_each_entry(svm, &static_vmlist, list) {
1065 vm = &svm->vm;
1066 addr = (unsigned long)vm->addr;
1067 if (addr < next)
1068 continue;
1069
1070
1071
1072
1073
1074
1075 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1076 pmd = pmd_off_k(addr);
1077 if (pmd_none(*pmd))
1078 pmd_empty_section_gap(addr & PMD_MASK);
1079 }
1080
1081
1082
1083
1084
1085
1086 addr += vm->size;
1087 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1088 pmd = pmd_off_k(addr) + 1;
1089 if (pmd_none(*pmd))
1090 pmd_empty_section_gap(addr);
1091 }
1092
1093
1094 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1095 }
1096}
1097
1098#else
1099#define fill_pmd_gaps() do { } while (0)
1100#endif
1101
1102#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1103static void __init pci_reserve_io(void)
1104{
1105 struct static_vm *svm;
1106
1107 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1108 if (svm)
1109 return;
1110
1111 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1112}
1113#else
1114#define pci_reserve_io() do { } while (0)
1115#endif
1116
1117#ifdef CONFIG_DEBUG_LL
1118void __init debug_ll_io_init(void)
1119{
1120 struct map_desc map;
1121
1122 debug_ll_addr(&map.pfn, &map.virtual);
1123 if (!map.pfn || !map.virtual)
1124 return;
1125 map.pfn = __phys_to_pfn(map.pfn);
1126 map.virtual &= PAGE_MASK;
1127 map.length = PAGE_SIZE;
1128 map.type = MT_DEVICE;
1129 iotable_init(&map, 1);
1130}
1131#endif
1132
1133static void * __initdata vmalloc_min =
1134 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1135
1136
1137
1138
1139
1140
1141static int __init early_vmalloc(char *arg)
1142{
1143 unsigned long vmalloc_reserve = memparse(arg, NULL);
1144
1145 if (vmalloc_reserve < SZ_16M) {
1146 vmalloc_reserve = SZ_16M;
1147 pr_warn("vmalloc area too small, limiting to %luMB\n",
1148 vmalloc_reserve >> 20);
1149 }
1150
1151 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1152 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1153 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1154 vmalloc_reserve >> 20);
1155 }
1156
1157 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1158 return 0;
1159}
1160early_param("vmalloc", early_vmalloc);
1161
1162phys_addr_t arm_lowmem_limit __initdata = 0;
1163
1164void __init adjust_lowmem_bounds(void)
1165{
1166 phys_addr_t memblock_limit = 0;
1167 u64 vmalloc_limit;
1168 struct memblock_region *reg;
1169 phys_addr_t lowmem_limit = 0;
1170
1171
1172
1173
1174
1175
1176
1177
1178 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1179
1180 for_each_memblock(memory, reg) {
1181 phys_addr_t block_start = reg->base;
1182 phys_addr_t block_end = reg->base + reg->size;
1183
1184 if (reg->base < vmalloc_limit) {
1185 if (block_end > lowmem_limit)
1186
1187
1188
1189
1190
1191
1192 lowmem_limit = min_t(u64,
1193 vmalloc_limit,
1194 block_end);
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209 if (!memblock_limit) {
1210 if (!IS_ALIGNED(block_start, PMD_SIZE))
1211 memblock_limit = block_start;
1212 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1213 memblock_limit = lowmem_limit;
1214 }
1215
1216 }
1217 }
1218
1219 arm_lowmem_limit = lowmem_limit;
1220
1221 high_memory = __va(arm_lowmem_limit - 1) + 1;
1222
1223 if (!memblock_limit)
1224 memblock_limit = arm_lowmem_limit;
1225
1226
1227
1228
1229
1230
1231 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1232
1233 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1234 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1235 phys_addr_t end = memblock_end_of_DRAM();
1236
1237 pr_notice("Ignoring RAM at %pa-%pa\n",
1238 &memblock_limit, &end);
1239 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1240
1241 memblock_remove(memblock_limit, end - memblock_limit);
1242 }
1243 }
1244
1245 memblock_set_current_limit(memblock_limit);
1246}
1247
1248static inline void prepare_page_table(void)
1249{
1250 unsigned long addr;
1251 phys_addr_t end;
1252
1253
1254
1255
1256 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1257 pmd_clear(pmd_off_k(addr));
1258
1259#ifdef CONFIG_XIP_KERNEL
1260
1261 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1262#endif
1263 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1264 pmd_clear(pmd_off_k(addr));
1265
1266
1267
1268
1269 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1270 if (end >= arm_lowmem_limit)
1271 end = arm_lowmem_limit;
1272
1273
1274
1275
1276
1277 for (addr = __phys_to_virt(end);
1278 addr < VMALLOC_START; addr += PMD_SIZE)
1279 pmd_clear(pmd_off_k(addr));
1280}
1281
1282#ifdef CONFIG_ARM_LPAE
1283
1284#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1285 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1286#else
1287#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1288#endif
1289
1290
1291
1292
1293void __init arm_mm_memblock_reserve(void)
1294{
1295
1296
1297
1298
1299 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1300
1301#ifdef CONFIG_SA1111
1302
1303
1304
1305
1306 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1307#endif
1308}
1309
1310
1311
1312
1313
1314
1315
1316
1317static void __init devicemaps_init(const struct machine_desc *mdesc)
1318{
1319 struct map_desc map;
1320 unsigned long addr;
1321 void *vectors;
1322
1323
1324
1325
1326 vectors = early_alloc(PAGE_SIZE * 2);
1327
1328 early_trap_init(vectors);
1329
1330
1331
1332
1333 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1334 pmd_clear(pmd_off_k(addr));
1335
1336
1337
1338
1339
1340#ifdef CONFIG_XIP_KERNEL
1341 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1342 map.virtual = MODULES_VADDR;
1343 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1344 map.type = MT_ROM;
1345 create_mapping(&map);
1346#endif
1347
1348
1349
1350
1351#ifdef FLUSH_BASE
1352 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1353 map.virtual = FLUSH_BASE;
1354 map.length = SZ_1M;
1355 map.type = MT_CACHECLEAN;
1356 create_mapping(&map);
1357#endif
1358#ifdef FLUSH_BASE_MINICACHE
1359 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1360 map.virtual = FLUSH_BASE_MINICACHE;
1361 map.length = SZ_1M;
1362 map.type = MT_MINICLEAN;
1363 create_mapping(&map);
1364#endif
1365
1366
1367
1368
1369
1370
1371 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1372 map.virtual = 0xffff0000;
1373 map.length = PAGE_SIZE;
1374#ifdef CONFIG_KUSER_HELPERS
1375 map.type = MT_HIGH_VECTORS;
1376#else
1377 map.type = MT_LOW_VECTORS;
1378#endif
1379 create_mapping(&map);
1380
1381 if (!vectors_high()) {
1382 map.virtual = 0;
1383 map.length = PAGE_SIZE * 2;
1384 map.type = MT_LOW_VECTORS;
1385 create_mapping(&map);
1386 }
1387
1388
1389 map.pfn += 1;
1390 map.virtual = 0xffff0000 + PAGE_SIZE;
1391 map.length = PAGE_SIZE;
1392 map.type = MT_LOW_VECTORS;
1393 create_mapping(&map);
1394
1395
1396
1397
1398 if (mdesc->map_io)
1399 mdesc->map_io();
1400 else
1401 debug_ll_io_init();
1402 fill_pmd_gaps();
1403
1404
1405 pci_reserve_io();
1406
1407
1408
1409
1410
1411
1412
1413 local_flush_tlb_all();
1414 flush_cache_all();
1415
1416
1417 early_abt_enable();
1418}
1419
1420static void __init kmap_init(void)
1421{
1422#ifdef CONFIG_HIGHMEM
1423 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1424 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1425#endif
1426
1427 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1428 _PAGE_KERNEL_TABLE);
1429}
1430
1431static void __init map_lowmem(void)
1432{
1433 struct memblock_region *reg;
1434 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1435 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1436
1437
1438 for_each_memblock(memory, reg) {
1439 phys_addr_t start = reg->base;
1440 phys_addr_t end = start + reg->size;
1441 struct map_desc map;
1442
1443 if (memblock_is_nomap(reg))
1444 continue;
1445
1446 if (end > arm_lowmem_limit)
1447 end = arm_lowmem_limit;
1448 if (start >= end)
1449 break;
1450
1451 if (end < kernel_x_start) {
1452 map.pfn = __phys_to_pfn(start);
1453 map.virtual = __phys_to_virt(start);
1454 map.length = end - start;
1455 map.type = MT_MEMORY_RWX;
1456
1457 create_mapping(&map);
1458 } else if (start >= kernel_x_end) {
1459 map.pfn = __phys_to_pfn(start);
1460 map.virtual = __phys_to_virt(start);
1461 map.length = end - start;
1462 map.type = MT_MEMORY_RW;
1463
1464 create_mapping(&map);
1465 } else {
1466
1467 if (start < kernel_x_start) {
1468 map.pfn = __phys_to_pfn(start);
1469 map.virtual = __phys_to_virt(start);
1470 map.length = kernel_x_start - start;
1471 map.type = MT_MEMORY_RW;
1472
1473 create_mapping(&map);
1474 }
1475
1476 map.pfn = __phys_to_pfn(kernel_x_start);
1477 map.virtual = __phys_to_virt(kernel_x_start);
1478 map.length = kernel_x_end - kernel_x_start;
1479 map.type = MT_MEMORY_RWX;
1480
1481 create_mapping(&map);
1482
1483 if (kernel_x_end < end) {
1484 map.pfn = __phys_to_pfn(kernel_x_end);
1485 map.virtual = __phys_to_virt(kernel_x_end);
1486 map.length = end - kernel_x_end;
1487 map.type = MT_MEMORY_RW;
1488
1489 create_mapping(&map);
1490 }
1491 }
1492 }
1493}
1494
1495#ifdef CONFIG_ARM_PV_FIXUP
1496extern unsigned long __atags_pointer;
1497typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1498pgtables_remap lpae_pgtables_remap_asm;
1499
1500
1501
1502
1503
1504static void __init early_paging_init(const struct machine_desc *mdesc)
1505{
1506 pgtables_remap *lpae_pgtables_remap;
1507 unsigned long pa_pgd;
1508 unsigned int cr, ttbcr;
1509 long long offset;
1510 void *boot_data;
1511
1512 if (!mdesc->pv_fixup)
1513 return;
1514
1515 offset = mdesc->pv_fixup();
1516 if (offset == 0)
1517 return;
1518
1519
1520
1521
1522
1523
1524
1525 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1526 pa_pgd = __pa(swapper_pg_dir);
1527 boot_data = __va(__atags_pointer);
1528 barrier();
1529
1530 pr_info("Switching physical address space to 0x%08llx\n",
1531 (u64)PHYS_OFFSET + offset);
1532
1533
1534 __pv_offset += offset;
1535 __pv_phys_pfn_offset += PFN_DOWN(offset);
1536
1537
1538 fixup_pv_table(&__pv_table_begin,
1539 (&__pv_table_end - &__pv_table_begin) << 2);
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550 cr = get_cr();
1551 set_cr(cr & ~(CR_I | CR_C));
1552 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1553 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1554 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1555 flush_cache_all();
1556
1557
1558
1559
1560
1561
1562
1563 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1564
1565
1566 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1567 set_cr(cr);
1568}
1569
1570#else
1571
1572static void __init early_paging_init(const struct machine_desc *mdesc)
1573{
1574 long long offset;
1575
1576 if (!mdesc->pv_fixup)
1577 return;
1578
1579 offset = mdesc->pv_fixup();
1580 if (offset == 0)
1581 return;
1582
1583 pr_crit("Physical address space modification is only to support Keystone2.\n");
1584 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1585 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1586 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1587}
1588
1589#endif
1590
1591static void __init early_fixmap_shutdown(void)
1592{
1593 int i;
1594 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1595
1596 pte_offset_fixmap = pte_offset_late_fixmap;
1597 pmd_clear(fixmap_pmd(va));
1598 local_flush_tlb_kernel_page(va);
1599
1600 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1601 pte_t *pte;
1602 struct map_desc map;
1603
1604 map.virtual = fix_to_virt(i);
1605 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1606
1607
1608 if (pte_none(*pte) ||
1609 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1610 continue;
1611
1612 map.pfn = pte_pfn(*pte);
1613 map.type = MT_DEVICE;
1614 map.length = PAGE_SIZE;
1615
1616 create_mapping(&map);
1617 }
1618}
1619
1620
1621
1622
1623
1624void __init paging_init(const struct machine_desc *mdesc)
1625{
1626 void *zero_page;
1627
1628 prepare_page_table();
1629 map_lowmem();
1630 memblock_set_current_limit(arm_lowmem_limit);
1631 dma_contiguous_remap();
1632 early_fixmap_shutdown();
1633 devicemaps_init(mdesc);
1634 kmap_init();
1635 tcm_init();
1636
1637 top_pmd = pmd_off_k(0xffff0000);
1638
1639
1640 zero_page = early_alloc(PAGE_SIZE);
1641
1642 bootmem_init();
1643
1644 empty_zero_page = virt_to_page(zero_page);
1645 __flush_dcache_page(NULL, empty_zero_page);
1646
1647
1648 kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset);
1649}
1650
1651void __init early_mm_init(const struct machine_desc *mdesc)
1652{
1653 build_mem_type_table();
1654 early_paging_init(mdesc);
1655}
1656