LXR linux/arch/arm64/include/asm/processor.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Based on arch/arm/include/asm/processor.h
   4 *
   5 * Copyright (C) 1995-1999 Russell King
   6 * Copyright (C) 2012 ARM Ltd.
   7 */
   8#ifndef __ASM_PROCESSOR_H
   9#define __ASM_PROCESSOR_H
  10
  11#define KERNEL_DS               UL(-1)
  12#define USER_DS                 ((UL(1) << MAX_USER_VA_BITS) - 1)
  13
  14/*
  15 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
  16 * no point in shifting all network buffers by 2 bytes just to make some IP
  17 * header fields appear aligned in memory, potentially sacrificing some DMA
  18 * performance on some platforms.
  19 */
  20#define NET_IP_ALIGN    0
  21
  22#ifndef __ASSEMBLY__
  23#ifdef __KERNEL__
  24
  25#include <linux/build_bug.h>
  26#include <linux/cache.h>
  27#include <linux/init.h>
  28#include <linux/stddef.h>
  29#include <linux/string.h>
  30
  31#include <asm/alternative.h>
  32#include <asm/cpufeature.h>
  33#include <asm/hw_breakpoint.h>
  34#include <asm/lse.h>
  35#include <asm/pgtable-hwdef.h>
  36#include <asm/pointer_auth.h>
  37#include <asm/ptrace.h>
  38#include <asm/types.h>
  39
  40/*
  41 * TASK_SIZE - the maximum size of a user space task.
  42 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  43 */
  44
  45#define DEFAULT_MAP_WINDOW_64   (UL(1) << VA_BITS)
  46#define TASK_SIZE_64            (UL(1) << vabits_user)
  47
  48#ifdef CONFIG_COMPAT
  49#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
  50/*
  51 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
  52 * by the compat vectors page.
  53 */
  54#define TASK_SIZE_32            UL(0x100000000)
  55#else
  56#define TASK_SIZE_32            (UL(0x100000000) - PAGE_SIZE)
  57#endif /* CONFIG_ARM64_64K_PAGES */
  58#define TASK_SIZE               (test_thread_flag(TIF_32BIT) ? \
  59                                TASK_SIZE_32 : TASK_SIZE_64)
  60#define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
  61                                TASK_SIZE_32 : TASK_SIZE_64)
  62#define DEFAULT_MAP_WINDOW      (test_thread_flag(TIF_32BIT) ? \
  63                                TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
  64#else
  65#define TASK_SIZE               TASK_SIZE_64
  66#define DEFAULT_MAP_WINDOW      DEFAULT_MAP_WINDOW_64
  67#endif /* CONFIG_COMPAT */
  68
  69#ifdef CONFIG_ARM64_FORCE_52BIT
  70#define STACK_TOP_MAX           TASK_SIZE_64
  71#define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 4))
  72#else
  73#define STACK_TOP_MAX           DEFAULT_MAP_WINDOW_64
  74#define TASK_UNMAPPED_BASE      (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
  75#endif /* CONFIG_ARM64_FORCE_52BIT */
  76
  77#ifdef CONFIG_COMPAT
  78#define AARCH32_VECTORS_BASE    0xffff0000
  79#define STACK_TOP               (test_thread_flag(TIF_32BIT) ? \
  80                                AARCH32_VECTORS_BASE : STACK_TOP_MAX)
  81#else
  82#define STACK_TOP               STACK_TOP_MAX
  83#endif /* CONFIG_COMPAT */
  84
  85#ifndef CONFIG_ARM64_FORCE_52BIT
  86#define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
  87                                DEFAULT_MAP_WINDOW)
  88
  89#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
  90                                        base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
  91                                        base)
  92#endif /* CONFIG_ARM64_FORCE_52BIT */
  93
  94extern phys_addr_t arm64_dma_phys_limit;
  95#define ARCH_LOW_ADDRESS_LIMIT  (arm64_dma_phys_limit - 1)
  96
  97struct debug_info {
  98#ifdef CONFIG_HAVE_HW_BREAKPOINT
  99        /* Have we suspended stepping by a debugger? */
 100        int                     suspended_step;
 101        /* Allow breakpoints and watchpoints to be disabled for this thread. */
 102        int                     bps_disabled;
 103        int                     wps_disabled;
 104        /* Hardware breakpoints pinned to this task. */
 105        struct perf_event       *hbp_break[ARM_MAX_BRP];
 106        struct perf_event       *hbp_watch[ARM_MAX_WRP];
 107#endif
 108};
 109
 110struct cpu_context {
 111        unsigned long x19;
 112        unsigned long x20;
 113        unsigned long x21;
 114        unsigned long x22;
 115        unsigned long x23;
 116        unsigned long x24;
 117        unsigned long x25;
 118        unsigned long x26;
 119        unsigned long x27;
 120        unsigned long x28;
 121        unsigned long fp;
 122        unsigned long sp;
 123        unsigned long pc;
 124};
 125
 126struct thread_struct {
 127        struct cpu_context      cpu_context;    /* cpu context */
 128
 129        /*
 130         * Whitelisted fields for hardened usercopy:
 131         * Maintainers must ensure manually that this contains no
 132         * implicit padding.
 133         */
 134        struct {
 135                unsigned long   tp_value;       /* TLS register */
 136                unsigned long   tp2_value;
 137                struct user_fpsimd_state fpsimd_state;
 138        } uw;
 139
 140        unsigned int            fpsimd_cpu;
 141        void                    *sve_state;     /* SVE registers, if any */
 142        unsigned int            sve_vl;         /* SVE vector length */
 143        unsigned int            sve_vl_onexec;  /* SVE vl after next exec */
 144        unsigned long           fault_address;  /* fault info */
 145        unsigned long           fault_code;     /* ESR_EL1 value */
 146        struct debug_info       debug;          /* debugging */
 147#ifdef CONFIG_ARM64_PTR_AUTH
 148        struct ptrauth_keys     keys_user;
 149#endif
 150};
 151
 152static inline void arch_thread_struct_whitelist(unsigned long *offset,
 153                                                unsigned long *size)
 154{
 155        /* Verify that there is no padding among the whitelisted fields: */
 156        BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
 157                     sizeof_field(struct thread_struct, uw.tp_value) +
 158                     sizeof_field(struct thread_struct, uw.tp2_value) +
 159                     sizeof_field(struct thread_struct, uw.fpsimd_state));
 160
 161        *offset = offsetof(struct thread_struct, uw);
 162        *size = sizeof_field(struct thread_struct, uw);
 163}
 164
 165#ifdef CONFIG_COMPAT
 166#define task_user_tls(t)                                                \
 167({                                                                      \
 168        unsigned long *__tls;                                           \
 169        if (is_compat_thread(task_thread_info(t)))                      \
 170                __tls = &(t)->thread.uw.tp2_value;                      \
 171        else                                                            \
 172                __tls = &(t)->thread.uw.tp_value;                       \
 173        __tls;                                                          \
 174 })
 175#else
 176#define task_user_tls(t)        (&(t)->thread.uw.tp_value)
 177#endif
 178
 179/* Sync TPIDR_EL0 back to thread_struct for current */
 180void tls_preserve_current_state(void);
 181
 182#define INIT_THREAD {                           \
 183        .fpsimd_cpu = NR_CPUS,                  \
 184}
 185
 186static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
 187{
 188        memset(regs, 0, sizeof(*regs));
 189        forget_syscall(regs);
 190        regs->pc = pc;
 191
 192        if (system_uses_irq_prio_masking())
 193                regs->pmr_save = GIC_PRIO_IRQON;
 194}
 195
 196static inline void set_ssbs_bit(struct pt_regs *regs)
 197{
 198        regs->pstate |= PSR_SSBS_BIT;
 199}
 200
 201static inline void set_compat_ssbs_bit(struct pt_regs *regs)
 202{
 203        regs->pstate |= PSR_AA32_SSBS_BIT;
 204}
 205
 206static inline void start_thread(struct pt_regs *regs, unsigned long pc,
 207                                unsigned long sp)
 208{
 209        start_thread_common(regs, pc);
 210        regs->pstate = PSR_MODE_EL0t;
 211
 212        if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
 213                set_ssbs_bit(regs);
 214
 215        regs->sp = sp;
 216}
 217
 218#ifdef CONFIG_COMPAT
 219static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
 220                                       unsigned long sp)
 221{
 222        start_thread_common(regs, pc);
 223        regs->pstate = PSR_AA32_MODE_USR;
 224        if (pc & 1)
 225                regs->pstate |= PSR_AA32_T_BIT;
 226
 227#ifdef __AARCH64EB__
 228        regs->pstate |= PSR_AA32_E_BIT;
 229#endif
 230
 231        if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
 232                set_compat_ssbs_bit(regs);
 233
 234        regs->compat_sp = sp;
 235}
 236#endif
 237
 238/* Forward declaration, a strange C thing */
 239struct task_struct;
 240
 241/* Free all resources held by a thread. */
 242extern void release_thread(struct task_struct *);
 243
 244unsigned long get_wchan(struct task_struct *p);
 245
 246static inline void cpu_relax(void)
 247{
 248        asm volatile("yield" ::: "memory");
 249}
 250
 251/* Thread switching */
 252extern struct task_struct *cpu_switch_to(struct task_struct *prev,
 253                                         struct task_struct *next);
 254
 255#define task_pt_regs(p) \
 256        ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
 257
 258#define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
 259#define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 260
 261/*
 262 * Prefetching support
 263 */
 264#define ARCH_HAS_PREFETCH
 265static inline void prefetch(const void *ptr)
 266{
 267        asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
 268}
 269
 270#define ARCH_HAS_PREFETCHW
 271static inline void prefetchw(const void *ptr)
 272{
 273        asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
 274}
 275
 276#define ARCH_HAS_SPINLOCK_PREFETCH
 277static inline void spin_lock_prefetch(const void *ptr)
 278{
 279        asm volatile(ARM64_LSE_ATOMIC_INSN(
 280                     "prfm pstl1strm, %a0",
 281                     "nop") : : "p" (ptr));
 282}
 283
 284#define HAVE_ARCH_PICK_MMAP_LAYOUT
 285
 286#endif
 287
 288extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
 289extern void __init minsigstksz_setup(void);
 290
 291/*
 292 * Not at the top of the file due to a direct #include cycle between
 293 * <asm/fpsimd.h> and <asm/processor.h>.  Deferring this #include
 294 * ensures that contents of processor.h are visible to fpsimd.h even if
 295 * processor.h is included first.
 296 *
 297 * These prctl helpers are the only things in this file that require
 298 * fpsimd.h.  The core code expects them to be in this header.
 299 */
 300#include <asm/fpsimd.h>
 301
 302/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
 303#define SVE_SET_VL(arg) sve_set_current_vl(arg)
 304#define SVE_GET_VL()    sve_get_current_vl()
 305
 306/* PR_PAC_RESET_KEYS prctl */
 307#define PAC_RESET_KEYS(tsk, arg)        ptrauth_prctl_reset_keys(tsk, arg)
 308
 309/*
 310 * For CONFIG_GCC_PLUGIN_STACKLEAK
 311 *
 312 * These need to be macros because otherwise we get stuck in a nightmare
 313 * of header definitions for the use of task_stack_page.
 314 */
 315
 316#define current_top_of_stack()                                                  \
 317({                                                                              \
 318        struct stack_info _info;                                                \
 319        BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info));   \
 320        _info.high;                                                             \
 321})
 322#define on_thread_stack()       (on_task_stack(current, current_stack_pointer, NULL))
 323
 324#endif /* __ASSEMBLY__ */
 325#endif /* __ASM_PROCESSOR_H */
 326