1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_HASH_H 3#define _ASM_HASH_H 4 5/* 6 * The later H8SX models have a 32x32-bit multiply, but the H8/300H 7 * and H8S have only 16x16->32. Since it's tolerably compact, this is 8 * basically an inlined version of the __mulsi3 code. Since the inputs 9 * are not expected to be small, it's also simplfied by skipping the 10 * early-out checks. 11 * 12 * (Since neither CPU has any multi-bit shift instructions, a 13 * shift-and-add version is a non-starter.) 14 * 15 * TODO: come up with an arch-specific version of the hashing in fs/namei.c, 16 * since that is heavily dependent on rotates. Which, as mentioned, suck 17 * horribly on H8. 18 */ 19 20#if defined(CONFIG_CPU_H300H) || defined(CONFIG_CPU_H8S) 21 22#define HAVE_ARCH__HASH_32 1 23 24/* 25 * Multiply by k = 0x61C88647. Fitting this into three registers requires 26 * one extra instruction, but reducing register pressure will probably 27 * make that back and then some. 28 * 29 * GCC asm note: %e1 is the high half of operand %1, while %f1 is the 30 * low half. So if %1 is er4, then %e1 is e4 and %f1 is r4. 31 * 32 * This has been designed to modify x in place, since that's the most 33 * common usage, but preserve k, since hash_64() makes two calls in 34 * quick succession. 35 */ 36static inline u32 __attribute_const__ __hash_32(u32 x) 37{ 38 u32 temp; 39 40 asm( "mov.w %e1,%f0" 41 "\n mulxu.w %f2,%0" /* klow * xhigh */ 42 "\n mov.w %f0,%e1" /* The extra instruction */ 43 "\n mov.w %f1,%f0" 44 "\n mulxu.w %e2,%0" /* khigh * xlow */ 45 "\n add.w %e1,%f0" 46 "\n mulxu.w %f2,%1" /* klow * xlow */ 47 "\n add.w %f0,%e1" 48 : "=&r" (temp), "=r" (x) 49 : "%r" (GOLDEN_RATIO_32), "1" (x)); 50 return x; 51} 52 53#endif 54#endif /* _ASM_HASH_H */ 55