LXR linux/arch/ia64/include/asm/sn/pda.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   7 */
   8#ifndef _ASM_IA64_SN_PDA_H
   9#define _ASM_IA64_SN_PDA_H
  10
  11#include <linux/cache.h>
  12#include <asm/percpu.h>
  13
  14
  15/*
  16 * CPU-specific data structure.
  17 *
  18 * One of these structures is allocated for each cpu of a NUMA system.
  19 *
  20 * This structure provides a convenient way of keeping together 
  21 * all SN per-cpu data structures. 
  22 */
  23
  24typedef struct pda_s {
  25
  26        /*
  27         * Support for SN LEDs
  28         */
  29        volatile short  *led_address;
  30        u8              led_state;
  31        u8              hb_state;       /* supports blinking heartbeat leds */
  32        unsigned int    hb_count;
  33
  34        unsigned int    idle_flag;
  35        
  36        volatile unsigned long *bedrock_rev_id;
  37        volatile unsigned long *pio_write_status_addr;
  38        unsigned long pio_write_status_val;
  39        volatile unsigned long *pio_shub_war_cam_addr;
  40
  41        unsigned long   sn_in_service_ivecs[4];
  42        int             sn_lb_int_war_ticks;
  43        int             sn_last_irq;
  44        int             sn_first_irq;
  45} pda_t;
  46
  47
  48#define CACHE_ALIGN(x)  (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
  49
  50/*
  51 * PDA
  52 * Per-cpu private data area for each cpu. The PDA is located immediately after
  53 * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
  54 * cpu but only a small amout of the page is actually used. We put the SNIA PDA
  55 * in the same page as the cpu_data area. Note that there is a check in the setup
  56 * code to verify that we don't overflow the page.
  57 *
  58 * Seems like we should should cache-line align the pda so that any changes in the
  59 * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
  60 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
  61 */
  62DECLARE_PER_CPU(struct pda_s, pda_percpu);
  63
  64#define pda             (&__ia64_per_cpu_var(pda_percpu))
  65
  66#define pdacpu(cpu)     (&per_cpu(pda_percpu, cpu))
  67
  68#endif /* _ASM_IA64_SN_PDA_H */
  69