LXR linux/arch/m68k/coldfire/m520x.c

   1// SPDX-License-Identifier: GPL-2.0
   2/***************************************************************************/
   3
   4/*
   5 *  m520x.c  -- platform support for ColdFire 520x based boards
   6 *
   7 *  Copyright (C) 2005,      Freescale (www.freescale.com)
   8 *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
   9 *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
  10 *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  11 */
  12
  13/***************************************************************************/
  14
  15#include <linux/kernel.h>
  16#include <linux/param.h>
  17#include <linux/init.h>
  18#include <linux/io.h>
  19#include <asm/machdep.h>
  20#include <asm/coldfire.h>
  21#include <asm/mcfsim.h>
  22#include <asm/mcfuart.h>
  23#include <asm/mcfclk.h>
  24
  25/***************************************************************************/
  26
  27DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
  28DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
  29DEFINE_CLK(0, "edma", 17, MCF_CLK);
  30DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
  31DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
  32DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
  33DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
  34DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
  35DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
  36DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
  37DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
  38DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
  39DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
  40DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
  41
  42DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
  43DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
  44DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
  45DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
  46DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
  47DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
  48DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
  49DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
  50
  51struct clk *mcf_clks[] = {
  52        &__clk_0_2, /* flexbus */
  53        &__clk_0_12, /* fec.0 */
  54        &__clk_0_17, /* edma */
  55        &__clk_0_18, /* intc.0 */
  56        &__clk_0_21, /* iack.0 */
  57        &__clk_0_22, /* imx1-i2c.0 */
  58        &__clk_0_23, /* mcfqspi.0 */
  59        &__clk_0_24, /* mcfuart.0 */
  60        &__clk_0_25, /* mcfuart.1 */
  61        &__clk_0_26, /* mcfuart.2 */
  62        &__clk_0_28, /* mcftmr.0 */
  63        &__clk_0_29, /* mcftmr.1 */
  64        &__clk_0_30, /* mcftmr.2 */
  65        &__clk_0_31, /* mcftmr.3 */
  66
  67        &__clk_0_32, /* mcfpit.0 */
  68        &__clk_0_33, /* mcfpit.1 */
  69        &__clk_0_34, /* mcfeport.0 */
  70        &__clk_0_35, /* mcfwdt.0 */
  71        &__clk_0_36, /* pll.0 */
  72        &__clk_0_40, /* sys.0 */
  73        &__clk_0_41, /* gpio.0 */
  74        &__clk_0_42, /* sdram.0 */
  75        NULL,
  76};
  77
  78static struct clk * const enable_clks[] __initconst = {
  79        &__clk_0_2, /* flexbus */
  80        &__clk_0_18, /* intc.0 */
  81        &__clk_0_21, /* iack.0 */
  82        &__clk_0_24, /* mcfuart.0 */
  83        &__clk_0_25, /* mcfuart.1 */
  84        &__clk_0_26, /* mcfuart.2 */
  85
  86        &__clk_0_32, /* mcfpit.0 */
  87        &__clk_0_33, /* mcfpit.1 */
  88        &__clk_0_34, /* mcfeport.0 */
  89        &__clk_0_36, /* pll.0 */
  90        &__clk_0_40, /* sys.0 */
  91        &__clk_0_41, /* gpio.0 */
  92        &__clk_0_42, /* sdram.0 */
  93};
  94
  95static struct clk * const disable_clks[] __initconst = {
  96        &__clk_0_12, /* fec.0 */
  97        &__clk_0_17, /* edma */
  98        &__clk_0_22, /* imx1-i2c.0 */
  99        &__clk_0_23, /* mcfqspi.0 */
 100        &__clk_0_28, /* mcftmr.0 */
 101        &__clk_0_29, /* mcftmr.1 */
 102        &__clk_0_30, /* mcftmr.2 */
 103        &__clk_0_31, /* mcftmr.3 */
 104        &__clk_0_35, /* mcfwdt.0 */
 105};
 106
 107
 108static void __init m520x_clk_init(void)
 109{
 110        unsigned i;
 111
 112        /* make sure these clocks are enabled */
 113        for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
 114                __clk_init_enabled(enable_clks[i]);
 115        /* make sure these clocks are disabled */
 116        for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
 117                __clk_init_disabled(disable_clks[i]);
 118}
 119
 120/***************************************************************************/
 121
 122static void __init m520x_qspi_init(void)
 123{
 124#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 125        u16 par;
 126        /* setup Port QS for QSPI with gpio CS control */
 127        writeb(0x3f, MCF_GPIO_PAR_QSPI);
 128        /* make U1CTS and U2RTS gpio for cs_control */
 129        par = readw(MCF_GPIO_PAR_UART);
 130        par &= 0x00ff;
 131        writew(par, MCF_GPIO_PAR_UART);
 132#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 133}
 134
 135/***************************************************************************/
 136
 137static void __init m520x_i2c_init(void)
 138{
 139#if IS_ENABLED(CONFIG_I2C_IMX)
 140        u8 par;
 141
 142        /* setup Port FECI2C Pin Assignment Register for I2C */
 143        /*  set PAR_SCL to SCL and PAR_SDA to SDA */
 144        par = readb(MCF_GPIO_PAR_FECI2C);
 145        par |= 0x0f;
 146        writeb(par, MCF_GPIO_PAR_FECI2C);
 147#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
 148}
 149
 150/***************************************************************************/
 151
 152static void __init m520x_uarts_init(void)
 153{
 154        u16 par;
 155        u8 par2;
 156
 157        /* UART0 and UART1 GPIO pin setup */
 158        par = readw(MCF_GPIO_PAR_UART);
 159        par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
 160        par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
 161        writew(par, MCF_GPIO_PAR_UART);
 162
 163        /* UART1 GPIO pin setup */
 164        par2 = readb(MCF_GPIO_PAR_FECI2C);
 165        par2 &= ~0x0F;
 166        par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
 167                MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
 168        writeb(par2, MCF_GPIO_PAR_FECI2C);
 169}
 170
 171/***************************************************************************/
 172
 173static void __init m520x_fec_init(void)
 174{
 175        u8 v;
 176
 177        /* Set multi-function pins to ethernet mode */
 178        v = readb(MCF_GPIO_PAR_FEC);
 179        writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
 180
 181        v = readb(MCF_GPIO_PAR_FECI2C);
 182        writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
 183}
 184
 185/***************************************************************************/
 186
 187void __init config_BSP(char *commandp, int size)
 188{
 189        mach_sched_init = hw_timer_init;
 190        m520x_clk_init();
 191        m520x_uarts_init();
 192        m520x_fec_init();
 193        m520x_qspi_init();
 194        m520x_i2c_init();
 195}
 196
 197/***************************************************************************/
 198