LXR linux/arch/m68k/include/asm/motorola

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _MOTOROLA_PGTABLE_H
   3#define _MOTOROLA_PGTABLE_H
   4
   5
   6/*
   7 * Definitions for MMU descriptors
   8 */
   9#define _PAGE_PRESENT   0x001
  10#define _PAGE_SHORT     0x002
  11#define _PAGE_RONLY     0x004
  12#define _PAGE_READWRITE 0x000
  13#define _PAGE_ACCESSED  0x008
  14#define _PAGE_DIRTY     0x010
  15#define _PAGE_SUPER     0x080   /* 68040 supervisor only */
  16#define _PAGE_GLOBAL040 0x400   /* 68040 global bit, used for kva descs */
  17#define _PAGE_NOCACHE030 0x040  /* 68030 no-cache mode */
  18#define _PAGE_NOCACHE   0x060   /* 68040 cache mode, non-serialized */
  19#define _PAGE_NOCACHE_S 0x040   /* 68040 no-cache mode, serialized */
  20#define _PAGE_CACHE040  0x020   /* 68040 cache mode, cachable, copyback */
  21#define _PAGE_CACHE040W 0x000   /* 68040 cache mode, cachable, write-through */
  22
  23#define _DESCTYPE_MASK  0x003
  24
  25#define _CACHEMASK040   (~0x060)
  26#define _TABLE_MASK     (0xfffffe00)
  27
  28#define _PAGE_TABLE     (_PAGE_SHORT)
  29#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE)
  30
  31#define _PAGE_PROTNONE  0x004
  32
  33#ifndef __ASSEMBLY__
  34
  35/* This is the cache mode to be used for pages containing page descriptors for
  36 * processors >= '040. It is in pte_mknocache(), and the variable is defined
  37 * and initialized in head.S */
  38extern int m68k_pgtable_cachemode;
  39
  40/* This is the cache mode for normal pages, for supervisor access on
  41 * processors >= '040. It is used in pte_mkcache(), and the variable is
  42 * defined and initialized in head.S */
  43
  44#if defined(CPU_M68060_ONLY) && defined(CONFIG_060_WRITETHROUGH)
  45#define m68k_supervisor_cachemode _PAGE_CACHE040W
  46#elif defined(CPU_M68040_OR_M68060_ONLY)
  47#define m68k_supervisor_cachemode _PAGE_CACHE040
  48#elif defined(CPU_M68020_OR_M68030_ONLY)
  49#define m68k_supervisor_cachemode 0
  50#else
  51extern int m68k_supervisor_cachemode;
  52#endif
  53
  54#if defined(CPU_M68040_OR_M68060_ONLY)
  55#define mm_cachebits _PAGE_CACHE040
  56#elif defined(CPU_M68020_OR_M68030_ONLY)
  57#define mm_cachebits 0
  58#else
  59extern unsigned long mm_cachebits;
  60#endif
  61
  62#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED | mm_cachebits)
  63#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | mm_cachebits)
  64#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
  65#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
  66#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | mm_cachebits)
  67
  68/* Alternate definitions that are compile time constants, for
  69   initializing protection_map.  The cachebits are fixed later.  */
  70#define PAGE_NONE_C     __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
  71#define PAGE_SHARED_C   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
  72#define PAGE_COPY_C     __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
  73#define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
  74
  75/*
  76 * The m68k can't do page protection for execute, and considers that the same are read.
  77 * Also, write permissions imply read permissions. This is the closest we can get..
  78 */
  79#define __P000  PAGE_NONE_C
  80#define __P001  PAGE_READONLY_C
  81#define __P010  PAGE_COPY_C
  82#define __P011  PAGE_COPY_C
  83#define __P100  PAGE_READONLY_C
  84#define __P101  PAGE_READONLY_C
  85#define __P110  PAGE_COPY_C
  86#define __P111  PAGE_COPY_C
  87
  88#define __S000  PAGE_NONE_C
  89#define __S001  PAGE_READONLY_C
  90#define __S010  PAGE_SHARED_C
  91#define __S011  PAGE_SHARED_C
  92#define __S100  PAGE_READONLY_C
  93#define __S101  PAGE_READONLY_C
  94#define __S110  PAGE_SHARED_C
  95#define __S111  PAGE_SHARED_C
  96
  97/*
  98 * Conversion functions: convert a page and protection to a page entry,
  99 * and a page entry and page directory to the page they refer to.
 100 */
 101#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
 102
 103static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 104{
 105        pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 106        return pte;
 107}
 108
 109static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 110{
 111        unsigned long ptbl = virt_to_phys(ptep) | _PAGE_TABLE | _PAGE_ACCESSED;
 112        unsigned long *ptr = pmdp->pmd;
 113        short i = 16;
 114        while (--i >= 0) {
 115                *ptr++ = ptbl;
 116                ptbl += (sizeof(pte_t)*PTRS_PER_PTE/16);
 117        }
 118}
 119
 120static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
 121{
 122        pgd_val(*pgdp) = _PAGE_TABLE | _PAGE_ACCESSED | __pa(pmdp);
 123}
 124
 125#define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK))
 126#define __pmd_page(pmd) ((unsigned long)__va(pmd_val(pmd) & _TABLE_MASK))
 127#define __pgd_page(pgd) ((unsigned long)__va(pgd_val(pgd) & _TABLE_MASK))
 128
 129
 130#define pte_none(pte)           (!pte_val(pte))
 131#define pte_present(pte)        (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE))
 132#define pte_clear(mm,addr,ptep)         ({ pte_val(*(ptep)) = 0; })
 133
 134#define pte_page(pte)           virt_to_page(__va(pte_val(pte)))
 135#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 136#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 137
 138#define pmd_none(pmd)           (!pmd_val(pmd))
 139#define pmd_bad(pmd)            ((pmd_val(pmd) & _DESCTYPE_MASK) != _PAGE_TABLE)
 140#define pmd_present(pmd)        (pmd_val(pmd) & _PAGE_TABLE)
 141#define pmd_clear(pmdp) ({                      \
 142        unsigned long *__ptr = pmdp->pmd;       \
 143        short __i = 16;                         \
 144        while (--__i >= 0)                      \
 145                *__ptr++ = 0;                   \
 146})
 147#define pmd_page(pmd)           virt_to_page(__va(pmd_val(pmd)))
 148
 149
 150#define pgd_none(pgd)           (!pgd_val(pgd))
 151#define pgd_bad(pgd)            ((pgd_val(pgd) & _DESCTYPE_MASK) != _PAGE_TABLE)
 152#define pgd_present(pgd)        (pgd_val(pgd) & _PAGE_TABLE)
 153#define pgd_clear(pgdp)         ({ pgd_val(*pgdp) = 0; })
 154#define pgd_page(pgd)           (mem_map + ((unsigned long)(__va(pgd_val(pgd)) - PAGE_OFFSET) >> PAGE_SHIFT))
 155
 156#define pte_ERROR(e) \
 157        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 158#define pmd_ERROR(e) \
 159        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 160#define pgd_ERROR(e) \
 161        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 162
 163
 164/*
 165 * The following only work if pte_present() is true.
 166 * Undefined behaviour if not..
 167 */
 168static inline int pte_write(pte_t pte)          { return !(pte_val(pte) & _PAGE_RONLY); }
 169static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 170static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 171static inline int pte_special(pte_t pte)        { return 0; }
 172
 173static inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) |= _PAGE_RONLY; return pte; }
 174static inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 175static inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 176static inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) &= ~_PAGE_RONLY; return pte; }
 177static inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 178static inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 179static inline pte_t pte_mknocache(pte_t pte)
 180{
 181        pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_pgtable_cachemode;
 182        return pte;
 183}
 184static inline pte_t pte_mkcache(pte_t pte)
 185{
 186        pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_supervisor_cachemode;
 187        return pte;
 188}
 189static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
 190
 191#define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
 192
 193#define pgd_index(address)     ((address) >> PGDIR_SHIFT)
 194
 195/* to find an entry in a page-table-directory */
 196static inline pgd_t *pgd_offset(const struct mm_struct *mm,
 197                                unsigned long address)
 198{
 199        return mm->pgd + pgd_index(address);
 200}
 201
 202#define swapper_pg_dir kernel_pg_dir
 203extern pgd_t kernel_pg_dir[128];
 204
 205static inline pgd_t *pgd_offset_k(unsigned long address)
 206{
 207        return kernel_pg_dir + (address >> PGDIR_SHIFT);
 208}
 209
 210
 211/* Find an entry in the second-level page table.. */
 212static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
 213{
 214        return (pmd_t *)__pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1));
 215}
 216
 217/* Find an entry in the third-level page table.. */
 218static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address)
 219{
 220        return (pte_t *)__pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 221}
 222
 223#define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 224#define pte_unmap(pte)          ((void)0)
 225
 226/*
 227 * Allocate and free page tables. The xxx_kernel() versions are
 228 * used to allocate a kernel page table - this turns on ASN bits
 229 * if any.
 230 */
 231
 232/* Prior to calling these routines, the page should have been flushed
 233 * from both the cache and ATC, or the CPU might not notice that the
 234 * cache setting for the page has been changed. -jskov
 235 */
 236static inline void nocache_page(void *vaddr)
 237{
 238        unsigned long addr = (unsigned long)vaddr;
 239
 240        if (CPU_IS_040_OR_060) {
 241                pgd_t *dir;
 242                pmd_t *pmdp;
 243                pte_t *ptep;
 244
 245                dir = pgd_offset_k(addr);
 246                pmdp = pmd_offset(dir, addr);
 247                ptep = pte_offset_kernel(pmdp, addr);
 248                *ptep = pte_mknocache(*ptep);
 249        }
 250}
 251
 252static inline void cache_page(void *vaddr)
 253{
 254        unsigned long addr = (unsigned long)vaddr;
 255
 256        if (CPU_IS_040_OR_060) {
 257                pgd_t *dir;
 258                pmd_t *pmdp;
 259                pte_t *ptep;
 260
 261                dir = pgd_offset_k(addr);
 262                pmdp = pmd_offset(dir, addr);
 263                ptep = pte_offset_kernel(pmdp, addr);
 264                *ptep = pte_mkcache(*ptep);
 265        }
 266}
 267
 268/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
 269#define __swp_type(x)           (((x).val >> 4) & 0xff)
 270#define __swp_offset(x)         ((x).val >> 12)
 271#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 12) })
 272#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 273#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 274
 275#endif  /* !__ASSEMBLY__ */
 276#endif /* _MOTOROLA_PGTABLE_H */
 277