LXR linux/arch/mips/alchemy/common/setup.c

   1/*
   2 * Copyright 2000, 2007-2008 MontaVista Software Inc.
   3 * Author: MontaVista Software, Inc. <source@mvista.com
   4 *
   5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
   6 *
   7 *  This program is free software; you can redistribute  it and/or modify it
   8 *  under  the terms of  the GNU General  Public License as published by the
   9 *  Free Software Foundation;  either version 2 of the  License, or (at your
  10 *  option) any later version.
  11 *
  12 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22 *
  23 *  You should have received a copy of the  GNU General Public License along
  24 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25 *  675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27
  28#include <linux/init.h>
  29#include <linux/ioport.h>
  30
  31#include <asm/dma-coherence.h>
  32#include <asm/mipsregs.h>
  33
  34#include <au1000.h>
  35
  36extern void __init board_setup(void);
  37extern void __init alchemy_set_lpj(void);
  38
  39void __init plat_mem_setup(void)
  40{
  41        alchemy_set_lpj();
  42
  43        if (au1xxx_cpu_needs_config_od())
  44                /* Various early Au1xx0 errata corrected by this */
  45                set_c0_config(1 << 19); /* Set Config[OD] */
  46        else
  47                /* Clear to obtain best system bus performance */
  48                clear_c0_config(1 << 19); /* Clear Config[OD] */
  49
  50        hw_coherentio = 0;
  51        coherentio = IO_COHERENCE_ENABLED;
  52        switch (alchemy_get_cputype()) {
  53        case ALCHEMY_CPU_AU1000:
  54        case ALCHEMY_CPU_AU1500:
  55        case ALCHEMY_CPU_AU1100:
  56                coherentio = IO_COHERENCE_DISABLED;
  57                break;
  58        case ALCHEMY_CPU_AU1200:
  59                /* Au1200 AB USB does not support coherent memory */
  60                if (0 == (read_c0_prid() & PRID_REV_MASK))
  61                        coherentio = IO_COHERENCE_DISABLED;
  62                break;
  63        }
  64
  65        board_setup();  /* board specific setup */
  66
  67        /* IO/MEM resources. */
  68        set_io_port_base(0);
  69        ioport_resource.start = IOPORT_RESOURCE_START;
  70        ioport_resource.end = IOPORT_RESOURCE_END;
  71        iomem_resource.start = IOMEM_RESOURCE_START;
  72        iomem_resource.end = IOMEM_RESOURCE_END;
  73}
  74
  75#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
  76/* This routine should be valid for all Au1x based boards */
  77phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
  78{
  79        unsigned long start = ALCHEMY_PCI_MEMWIN_START;
  80        unsigned long end = ALCHEMY_PCI_MEMWIN_END;
  81
  82        /* Don't fixup 36-bit addresses */
  83        if ((phys_addr >> 32) != 0)
  84                return phys_addr;
  85
  86        /* Check for PCI memory window */
  87        if (phys_addr >= start && (phys_addr + size - 1) <= end)
  88                return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
  89
  90        /* default nop */
  91        return phys_addr;
  92}
  93EXPORT_SYMBOL(__fixup_bigphys_addr);
  94#endif
  95