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17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/bitops.h>
20#include <linux/irqdomain.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/reboot.h>
24#include <asm/bootinfo.h>
25#include <asm/reboot.h>
26#include <asm/time.h>
27
28#include <ath25_platform.h>
29
30#include "devices.h"
31#include "ar2315.h"
32#include "ar2315_regs.h"
33
34static void __iomem *ar2315_rst_base;
35static struct irq_domain *ar2315_misc_irq_domain;
36
37static inline u32 ar2315_rst_reg_read(u32 reg)
38{
39 return __raw_readl(ar2315_rst_base + reg);
40}
41
42static inline void ar2315_rst_reg_write(u32 reg, u32 val)
43{
44 __raw_writel(val, ar2315_rst_base + reg);
45}
46
47static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
48{
49 u32 ret = ar2315_rst_reg_read(reg);
50
51 ret &= ~mask;
52 ret |= val;
53 ar2315_rst_reg_write(reg, ret);
54}
55
56static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
57{
58 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
59 ar2315_rst_reg_read(AR2315_AHB_ERR1);
60
61 pr_emerg("AHB fatal error\n");
62 machine_restart("AHB error");
63
64 return IRQ_HANDLED;
65}
66
67static struct irqaction ar2315_ahb_err_interrupt = {
68 .handler = ar2315_ahb_err_handler,
69 .name = "ar2315-ahb-error",
70};
71
72static void ar2315_misc_irq_handler(struct irq_desc *desc)
73{
74 u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
75 ar2315_rst_reg_read(AR2315_IMR);
76 unsigned nr, misc_irq = 0;
77
78 if (pending) {
79 struct irq_domain *domain = irq_desc_get_handler_data(desc);
80
81 nr = __ffs(pending);
82 misc_irq = irq_find_mapping(domain, nr);
83 }
84
85 if (misc_irq) {
86 if (nr == AR2315_MISC_IRQ_GPIO)
87 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
88 else if (nr == AR2315_MISC_IRQ_WATCHDOG)
89 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
90 generic_handle_irq(misc_irq);
91 } else {
92 spurious_interrupt();
93 }
94}
95
96static void ar2315_misc_irq_unmask(struct irq_data *d)
97{
98 ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
99}
100
101static void ar2315_misc_irq_mask(struct irq_data *d)
102{
103 ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
104}
105
106static struct irq_chip ar2315_misc_irq_chip = {
107 .name = "ar2315-misc",
108 .irq_unmask = ar2315_misc_irq_unmask,
109 .irq_mask = ar2315_misc_irq_mask,
110};
111
112static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
113 irq_hw_number_t hw)
114{
115 irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
116 return 0;
117}
118
119static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
120 .map = ar2315_misc_irq_map,
121};
122
123
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127
128
129
130
131static void ar2315_irq_dispatch(void)
132{
133 u32 pending = read_c0_status() & read_c0_cause();
134
135 if (pending & CAUSEF_IP3)
136 do_IRQ(AR2315_IRQ_WLAN0);
137#ifdef CONFIG_PCI_AR2315
138 else if (pending & CAUSEF_IP5)
139 do_IRQ(AR2315_IRQ_LCBUS_PCI);
140#endif
141 else if (pending & CAUSEF_IP2)
142 do_IRQ(AR2315_IRQ_MISC);
143 else if (pending & CAUSEF_IP7)
144 do_IRQ(ATH25_IRQ_CPU_CLOCK);
145 else
146 spurious_interrupt();
147}
148
149void __init ar2315_arch_init_irq(void)
150{
151 struct irq_domain *domain;
152 unsigned irq;
153
154 ath25_irq_dispatch = ar2315_irq_dispatch;
155
156 domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
157 &ar2315_misc_irq_domain_ops, NULL);
158 if (!domain)
159 panic("Failed to add IRQ domain");
160
161 irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
162 setup_irq(irq, &ar2315_ahb_err_interrupt);
163
164 irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
165 ar2315_misc_irq_handler, domain);
166
167 ar2315_misc_irq_domain = domain;
168}
169
170void __init ar2315_init_devices(void)
171{
172
173 ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
174
175 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
176}
177
178static void ar2315_restart(char *command)
179{
180 void (*mips_reset_vec)(void) = (void *)0xbfc00000;
181
182 local_irq_disable();
183
184
185 ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
186
187
188
189
190
191
192
193
194
195
196 mips_reset_vec();
197}
198
199
200
201
202
203static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
204static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
205
206static unsigned __init ar2315_sys_clk(u32 clock_ctl)
207{
208 unsigned int pllc_ctrl, cpu_div;
209 unsigned int pllc_out, refdiv, fdiv, divby2;
210 unsigned int clk_div;
211
212 pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
213 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
214 refdiv = clockctl1_predivide_table[refdiv];
215 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
216 divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
217 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
218
219
220 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
221 case 0:
222 case 1:
223 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
224 clk_div = pllc_divide_table[clk_div];
225 break;
226 case 2:
227 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
228 clk_div = pllc_divide_table[clk_div];
229 break;
230 default:
231 pllc_out = 40000000;
232 clk_div = 1;
233 break;
234 }
235
236 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
237 cpu_div = cpu_div * 2 ?: 1;
238
239 return pllc_out / (clk_div * cpu_div);
240}
241
242static inline unsigned ar2315_cpu_frequency(void)
243{
244 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
245}
246
247static inline unsigned ar2315_apb_frequency(void)
248{
249 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
250}
251
252void __init ar2315_plat_time_init(void)
253{
254 mips_hpt_frequency = ar2315_cpu_frequency() / 2;
255}
256
257void __init ar2315_plat_mem_setup(void)
258{
259 void __iomem *sdram_base;
260 u32 memsize, memcfg;
261 u32 devid;
262 u32 config;
263
264
265 sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
266 AR2315_SDRAMCTL_SIZE);
267 memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
268 memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
269 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
270 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
271 memsize <<= 3;
272 add_memory_region(0, memsize, BOOT_MEM_RAM);
273 iounmap(sdram_base);
274
275 ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
276
277
278 devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
279 switch (devid) {
280 case 0x91:
281 ath25_soc = ATH25_SOC_AR2318;
282 break;
283 case 0x90:
284 ath25_soc = ATH25_SOC_AR2317;
285 break;
286 case 0x87:
287 ath25_soc = ATH25_SOC_AR2316;
288 break;
289 case 0x86:
290 default:
291 ath25_soc = ATH25_SOC_AR2315;
292 break;
293 }
294 ath25_board.devid = devid;
295
296
297 config = read_c0_config();
298 write_c0_config(config & ~0x3);
299 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
300 ar2315_rst_reg_read(AR2315_AHB_ERR1);
301 ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
302
303 _machine_restart = ar2315_restart;
304}
305
306#ifdef CONFIG_PCI_AR2315
307static struct resource ar2315_pci_res[] = {
308 {
309 .name = "ar2315-pci-ctrl",
310 .flags = IORESOURCE_MEM,
311 .start = AR2315_PCI_BASE,
312 .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
313 },
314 {
315 .name = "ar2315-pci-ext",
316 .flags = IORESOURCE_MEM,
317 .start = AR2315_PCI_EXT_BASE,
318 .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
319 },
320 {
321 .name = "ar2315-pci",
322 .flags = IORESOURCE_IRQ,
323 .start = AR2315_IRQ_LCBUS_PCI,
324 .end = AR2315_IRQ_LCBUS_PCI,
325 },
326};
327#endif
328
329void __init ar2315_arch_init(void)
330{
331 unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
332 AR2315_MISC_IRQ_UART0);
333
334 ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
335
336#ifdef CONFIG_PCI_AR2315
337 if (ath25_soc == ATH25_SOC_AR2315) {
338
339 ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
340 msleep(20);
341 ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
342 msleep(20);
343
344
345 ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
346 AR2315_CONFIG_PCIAHB_BRIDGE);
347
348
349 ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
350 (AR2315_PCICLK_IN_FREQ_DIV_6 <<
351 AR2315_PCICLK_DIV_S));
352 ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
353 ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
354 AR2315_IF_MASK, AR2315_IF_PCI |
355 AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
356 (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
357 AR2315_IF_PCI_CLK_SHIFT));
358
359 platform_device_register_simple("ar2315-pci", -1,
360 ar2315_pci_res,
361 ARRAY_SIZE(ar2315_pci_res));
362 }
363#endif
364}
365
