LXR linux/arch/mips/include/asm/kvm

   1/*
   2* This file is subject to the terms and conditions of the GNU General Public
   3* License.  See the file "COPYING" in the main directory of this archive
   4* for more details.
   5*
   6* Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7* Authors: Sanjay Lal <sanjayl@kymasys.com>
   8*/
   9
  10#ifndef __MIPS_KVM_HOST_H__
  11#define __MIPS_KVM_HOST_H__
  12
  13#include <linux/cpumask.h>
  14#include <linux/mutex.h>
  15#include <linux/hrtimer.h>
  16#include <linux/interrupt.h>
  17#include <linux/types.h>
  18#include <linux/kvm.h>
  19#include <linux/kvm_types.h>
  20#include <linux/threads.h>
  21#include <linux/spinlock.h>
  22
  23#include <asm/inst.h>
  24#include <asm/mipsregs.h>
  25
  26/* MIPS KVM register ids */
  27#define MIPS_CP0_32(_R, _S)                                     \
  28        (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  29
  30#define MIPS_CP0_64(_R, _S)                                     \
  31        (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  32
  33#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  34#define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  35#define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  36#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  37#define KVM_REG_MIPS_CP0_CONTEXTCONFIG  MIPS_CP0_32(4, 1)
  38#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  39#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
  40#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  41#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  42#define KVM_REG_MIPS_CP0_SEGCTL0        MIPS_CP0_64(5, 2)
  43#define KVM_REG_MIPS_CP0_SEGCTL1        MIPS_CP0_64(5, 3)
  44#define KVM_REG_MIPS_CP0_SEGCTL2        MIPS_CP0_64(5, 4)
  45#define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)
  46#define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)
  47#define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)
  48#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  49#define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)
  50#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  51#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  52#define KVM_REG_MIPS_CP0_BADINSTR       MIPS_CP0_32(8, 1)
  53#define KVM_REG_MIPS_CP0_BADINSTRP      MIPS_CP0_32(8, 2)
  54#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  55#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  56#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  57#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  58#define KVM_REG_MIPS_CP0_INTCTL         MIPS_CP0_32(12, 1)
  59#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  60#define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  61#define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  62#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  63#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  64#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  65#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  66#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  67#define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  68#define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  69#define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  70#define KVM_REG_MIPS_CP0_MAARI          MIPS_CP0_64(17, 2)
  71#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  72#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  73#define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
  74#define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
  75#define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
  76#define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
  77#define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
  78#define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
  79
  80
  81#define KVM_MAX_VCPUS           8
  82#define KVM_USER_MEM_SLOTS      8
  83/* memory slots that does not exposed to userspace */
  84#define KVM_PRIVATE_MEM_SLOTS   0
  85
  86#define KVM_HALT_POLL_NS_DEFAULT 500000
  87
  88#ifdef CONFIG_KVM_MIPS_VZ
  89extern unsigned long GUESTID_MASK;
  90extern unsigned long GUESTID_FIRST_VERSION;
  91extern unsigned long GUESTID_VERSION_MASK;
  92#endif
  93
  94
  95/*
  96 * Special address that contains the comm page, used for reducing # of traps
  97 * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
  98 * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
  99 * caught.
 100 */
 101#define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
 102                                         (0x8000 - PAGE_SIZE))
 103
 104#define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
 105                                        ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
 106
 107#define KVM_GUEST_KUSEG                 0x00000000UL
 108#define KVM_GUEST_KSEG0                 0x40000000UL
 109#define KVM_GUEST_KSEG1                 0x40000000UL
 110#define KVM_GUEST_KSEG23                0x60000000UL
 111#define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
 112#define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
 113
 114#define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 115#define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 116#define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 117
 118/*
 119 * Map an address to a certain kernel segment
 120 */
 121#define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 122#define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 123#define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 124
 125#define KVM_INVALID_PAGE                0xdeadbeef
 126#define KVM_INVALID_ADDR                0xdeadbeef
 127
 128/*
 129 * EVA has overlapping user & kernel address spaces, so user VAs may be >
 130 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
 131 * PAGE_OFFSET.
 132 */
 133
 134#define KVM_HVA_ERR_BAD                 (-1UL)
 135#define KVM_HVA_ERR_RO_BAD              (-2UL)
 136
 137static inline bool kvm_is_error_hva(unsigned long addr)
 138{
 139        return IS_ERR_VALUE(addr);
 140}
 141
 142struct kvm_vm_stat {
 143        ulong remote_tlb_flush;
 144};
 145
 146struct kvm_vcpu_stat {
 147        u64 wait_exits;
 148        u64 cache_exits;
 149        u64 signal_exits;
 150        u64 int_exits;
 151        u64 cop_unusable_exits;
 152        u64 tlbmod_exits;
 153        u64 tlbmiss_ld_exits;
 154        u64 tlbmiss_st_exits;
 155        u64 addrerr_st_exits;
 156        u64 addrerr_ld_exits;
 157        u64 syscall_exits;
 158        u64 resvd_inst_exits;
 159        u64 break_inst_exits;
 160        u64 trap_inst_exits;
 161        u64 msa_fpe_exits;
 162        u64 fpe_exits;
 163        u64 msa_disabled_exits;
 164        u64 flush_dcache_exits;
 165#ifdef CONFIG_KVM_MIPS_VZ
 166        u64 vz_gpsi_exits;
 167        u64 vz_gsfc_exits;
 168        u64 vz_hc_exits;
 169        u64 vz_grr_exits;
 170        u64 vz_gva_exits;
 171        u64 vz_ghfc_exits;
 172        u64 vz_gpa_exits;
 173        u64 vz_resvd_exits;
 174#endif
 175        u64 halt_successful_poll;
 176        u64 halt_attempted_poll;
 177        u64 halt_poll_invalid;
 178        u64 halt_wakeup;
 179};
 180
 181struct kvm_arch_memory_slot {
 182};
 183
 184struct kvm_arch {
 185        /* Guest physical mm */
 186        struct mm_struct gpa_mm;
 187        /* Mask of CPUs needing GPA ASID flush */
 188        cpumask_t asid_flush_mask;
 189};
 190
 191#define N_MIPS_COPROC_REGS      32
 192#define N_MIPS_COPROC_SEL       8
 193
 194struct mips_coproc {
 195        unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 196#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 197        unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 198#endif
 199};
 200
 201/*
 202 * Coprocessor 0 register names
 203 */
 204#define MIPS_CP0_TLB_INDEX      0
 205#define MIPS_CP0_TLB_RANDOM     1
 206#define MIPS_CP0_TLB_LOW        2
 207#define MIPS_CP0_TLB_LO0        2
 208#define MIPS_CP0_TLB_LO1        3
 209#define MIPS_CP0_TLB_CONTEXT    4
 210#define MIPS_CP0_TLB_PG_MASK    5
 211#define MIPS_CP0_TLB_WIRED      6
 212#define MIPS_CP0_HWRENA         7
 213#define MIPS_CP0_BAD_VADDR      8
 214#define MIPS_CP0_COUNT          9
 215#define MIPS_CP0_TLB_HI         10
 216#define MIPS_CP0_COMPARE        11
 217#define MIPS_CP0_STATUS         12
 218#define MIPS_CP0_CAUSE          13
 219#define MIPS_CP0_EXC_PC         14
 220#define MIPS_CP0_PRID           15
 221#define MIPS_CP0_CONFIG         16
 222#define MIPS_CP0_LLADDR         17
 223#define MIPS_CP0_WATCH_LO       18
 224#define MIPS_CP0_WATCH_HI       19
 225#define MIPS_CP0_TLB_XCONTEXT   20
 226#define MIPS_CP0_ECC            26
 227#define MIPS_CP0_CACHE_ERR      27
 228#define MIPS_CP0_TAG_LO         28
 229#define MIPS_CP0_TAG_HI         29
 230#define MIPS_CP0_ERROR_PC       30
 231#define MIPS_CP0_DEBUG          23
 232#define MIPS_CP0_DEPC           24
 233#define MIPS_CP0_PERFCNT        25
 234#define MIPS_CP0_ERRCTL         26
 235#define MIPS_CP0_DATA_LO        28
 236#define MIPS_CP0_DATA_HI        29
 237#define MIPS_CP0_DESAVE         31
 238
 239#define MIPS_CP0_CONFIG_SEL     0
 240#define MIPS_CP0_CONFIG1_SEL    1
 241#define MIPS_CP0_CONFIG2_SEL    2
 242#define MIPS_CP0_CONFIG3_SEL    3
 243#define MIPS_CP0_CONFIG4_SEL    4
 244#define MIPS_CP0_CONFIG5_SEL    5
 245
 246#define MIPS_CP0_GUESTCTL2      10
 247#define MIPS_CP0_GUESTCTL2_SEL  5
 248#define MIPS_CP0_GTOFFSET       12
 249#define MIPS_CP0_GTOFFSET_SEL   7
 250
 251/* Resume Flags */
 252#define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 253#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 254
 255#define RESUME_GUEST            0
 256#define RESUME_GUEST_DR         RESUME_FLAG_DR
 257#define RESUME_HOST             RESUME_FLAG_HOST
 258
 259enum emulation_result {
 260        EMULATE_DONE,           /* no further processing */
 261        EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 262        EMULATE_FAIL,           /* can't emulate this instruction */
 263        EMULATE_WAIT,           /* WAIT instruction */
 264        EMULATE_PRIV_FAIL,
 265        EMULATE_EXCEPT,         /* A guest exception has been generated */
 266        EMULATE_HYPERCALL,      /* HYPCALL instruction */
 267};
 268
 269#define mips3_paddr_to_tlbpfn(x) \
 270        (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 271#define mips3_tlbpfn_to_paddr(x) \
 272        ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 273
 274#define MIPS3_PG_SHIFT          6
 275#define MIPS3_PG_FRAME          0x3fffffc0
 276
 277#define VPN2_MASK               0xffffe000
 278#define KVM_ENTRYHI_ASID        MIPS_ENTRYHI_ASID
 279#define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 280#define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 281#define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 282#define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
 283#define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
 284#define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
 285#define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 286                                 ((y) & VPN2_MASK & ~(x).tlb_mask))
 287#define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 288                                 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 289
 290struct kvm_mips_tlb {
 291        long tlb_mask;
 292        long tlb_hi;
 293        long tlb_lo[2];
 294};
 295
 296#define KVM_NR_MEM_OBJS     4
 297
 298/*
 299 * We don't want allocation failures within the mmu code, so we preallocate
 300 * enough memory for a single page fault in a cache.
 301 */
 302struct kvm_mmu_memory_cache {
 303        int nobjs;
 304        void *objects[KVM_NR_MEM_OBJS];
 305};
 306
 307#define KVM_MIPS_AUX_FPU        0x1
 308#define KVM_MIPS_AUX_MSA        0x2
 309
 310#define KVM_MIPS_GUEST_TLB_SIZE 64
 311struct kvm_vcpu_arch {
 312        void *guest_ebase;
 313        int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 314
 315        /* Host registers preserved across guest mode execution */
 316        unsigned long host_stack;
 317        unsigned long host_gp;
 318        unsigned long host_pgd;
 319        unsigned long host_entryhi;
 320
 321        /* Host CP0 registers used when handling exits from guest */
 322        unsigned long host_cp0_badvaddr;
 323        unsigned long host_cp0_epc;
 324        u32 host_cp0_cause;
 325        u32 host_cp0_guestctl0;
 326        u32 host_cp0_badinstr;
 327        u32 host_cp0_badinstrp;
 328
 329        /* GPRS */
 330        unsigned long gprs[32];
 331        unsigned long hi;
 332        unsigned long lo;
 333        unsigned long pc;
 334
 335        /* FPU State */
 336        struct mips_fpu_struct fpu;
 337        /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
 338        unsigned int aux_inuse;
 339
 340        /* COP0 State */
 341        struct mips_coproc *cop0;
 342
 343        /* Host KSEG0 address of the EI/DI offset */
 344        void *kseg0_commpage;
 345
 346        /* Resume PC after MMIO completion */
 347        unsigned long io_pc;
 348        /* GPR used as IO source/target */
 349        u32 io_gpr;
 350
 351        struct hrtimer comparecount_timer;
 352        /* Count timer control KVM register */
 353        u32 count_ctl;
 354        /* Count bias from the raw time */
 355        u32 count_bias;
 356        /* Frequency of timer in Hz */
 357        u32 count_hz;
 358        /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 359        s64 count_dyn_bias;
 360        /* Resume time */
 361        ktime_t count_resume;
 362        /* Period of timer tick in ns */
 363        u64 count_period;
 364
 365        /* Bitmask of exceptions that are pending */
 366        unsigned long pending_exceptions;
 367
 368        /* Bitmask of pending exceptions to be cleared */
 369        unsigned long pending_exceptions_clr;
 370
 371        /* S/W Based TLB for guest */
 372        struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 373
 374        /* Guest kernel/user [partial] mm */
 375        struct mm_struct guest_kernel_mm, guest_user_mm;
 376
 377        /* Guest ASID of last user mode execution */
 378        unsigned int last_user_gasid;
 379
 380        /* Cache some mmu pages needed inside spinlock regions */
 381        struct kvm_mmu_memory_cache mmu_page_cache;
 382
 383#ifdef CONFIG_KVM_MIPS_VZ
 384        /* vcpu's vzguestid is different on each host cpu in an smp system */
 385        u32 vzguestid[NR_CPUS];
 386
 387        /* wired guest TLB entries */
 388        struct kvm_mips_tlb *wired_tlb;
 389        unsigned int wired_tlb_limit;
 390        unsigned int wired_tlb_used;
 391
 392        /* emulated guest MAAR registers */
 393        unsigned long maar[6];
 394#endif
 395
 396        /* Last CPU the VCPU state was loaded on */
 397        int last_sched_cpu;
 398        /* Last CPU the VCPU actually executed guest code on */
 399        int last_exec_cpu;
 400
 401        /* WAIT executed */
 402        int wait;
 403
 404        u8 fpu_enabled;
 405        u8 msa_enabled;
 406};
 407
 408static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 409                                                unsigned long val)
 410{
 411        unsigned long temp;
 412        do {
 413                __asm__ __volatile__(
 414                "       .set    push                            \n"
 415                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 416                "       " __LL "%0, %1                          \n"
 417                "       or      %0, %2                          \n"
 418                "       " __SC  "%0, %1                         \n"
 419                "       .set    pop                             \n"
 420                : "=&r" (temp), "+m" (*reg)
 421                : "r" (val));
 422        } while (unlikely(!temp));
 423}
 424
 425static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 426                                                  unsigned long val)
 427{
 428        unsigned long temp;
 429        do {
 430                __asm__ __volatile__(
 431                "       .set    push                            \n"
 432                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 433                "       " __LL "%0, %1                          \n"
 434                "       and     %0, %2                          \n"
 435                "       " __SC  "%0, %1                         \n"
 436                "       .set    pop                             \n"
 437                : "=&r" (temp), "+m" (*reg)
 438                : "r" (~val));
 439        } while (unlikely(!temp));
 440}
 441
 442static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 443                                                   unsigned long change,
 444                                                   unsigned long val)
 445{
 446        unsigned long temp;
 447        do {
 448                __asm__ __volatile__(
 449                "       .set    push                            \n"
 450                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 451                "       " __LL "%0, %1                          \n"
 452                "       and     %0, %2                          \n"
 453                "       or      %0, %3                          \n"
 454                "       " __SC  "%0, %1                         \n"
 455                "       .set    pop                             \n"
 456                : "=&r" (temp), "+m" (*reg)
 457                : "r" (~change), "r" (val & change));
 458        } while (unlikely(!temp));
 459}
 460
 461/* Guest register types, used in accessor build below */
 462#define __KVMT32        u32
 463#define __KVMTl unsigned long
 464
 465/*
 466 * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
 467 * These operate on the saved guest C0 state in RAM.
 468 */
 469
 470/* Generate saved context simple accessors */
 471#define __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 472static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
 473{                                                                       \
 474        return cop0->reg[(_reg)][(sel)];                                \
 475}                                                                       \
 476static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0,    \
 477                                           __KVMT##type val)            \
 478{                                                                       \
 479        cop0->reg[(_reg)][(sel)] = val;                                 \
 480}
 481
 482/* Generate saved context bitwise modifiers */
 483#define __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 484static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 485                                         __KVMT##type val)              \
 486{                                                                       \
 487        cop0->reg[(_reg)][(sel)] |= val;                                \
 488}                                                                       \
 489static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 490                                           __KVMT##type val)            \
 491{                                                                       \
 492        cop0->reg[(_reg)][(sel)] &= ~val;                               \
 493}                                                                       \
 494static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 495                                            __KVMT##type mask,          \
 496                                            __KVMT##type val)           \
 497{                                                                       \
 498        unsigned long _mask = mask;                                     \
 499        cop0->reg[(_reg)][(sel)] &= ~_mask;                             \
 500        cop0->reg[(_reg)][(sel)] |= val & _mask;                        \
 501}
 502
 503/* Generate saved context atomic bitwise modifiers */
 504#define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 505static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 506                                         __KVMT##type val)              \
 507{                                                                       \
 508        _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val);   \
 509}                                                                       \
 510static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 511                                           __KVMT##type val)            \
 512{                                                                       \
 513        _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
 514}                                                                       \
 515static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 516                                            __KVMT##type mask,          \
 517                                            __KVMT##type val)           \
 518{                                                                       \
 519        _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
 520                                        val);                           \
 521}
 522
 523/*
 524 * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
 525 * These operate on the VZ guest C0 context in hardware.
 526 */
 527
 528/* Generate VZ guest context simple accessors */
 529#define __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 530static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
 531{                                                                       \
 532        return read_gc0_##name();                                       \
 533}                                                                       \
 534static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0,    \
 535                                           __KVMT##type val)            \
 536{                                                                       \
 537        write_gc0_##name(val);                                          \
 538}
 539
 540/* Generate VZ guest context bitwise modifiers */
 541#define __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 542static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0,      \
 543                                         __KVMT##type val)              \
 544{                                                                       \
 545        set_gc0_##name(val);                                            \
 546}                                                                       \
 547static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0,    \
 548                                           __KVMT##type val)            \
 549{                                                                       \
 550        clear_gc0_##name(val);                                          \
 551}                                                                       \
 552static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0,   \
 553                                            __KVMT##type mask,          \
 554                                            __KVMT##type val)           \
 555{                                                                       \
 556        change_gc0_##name(mask, val);                                   \
 557}
 558
 559/* Generate VZ guest context save/restore to/from saved context */
 560#define __BUILD_KVM_SAVE_VZ(name, _reg, sel)                    \
 561static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0)     \
 562{                                                                       \
 563        write_gc0_##name(cop0->reg[(_reg)][(sel)]);                     \
 564}                                                                       \
 565static inline void kvm_save_gc0_##name(struct mips_coproc *cop0)        \
 566{                                                                       \
 567        cop0->reg[(_reg)][(sel)] = read_gc0_##name();                   \
 568}
 569
 570/*
 571 * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
 572 * These wrap a set of operations to provide them with a different name.
 573 */
 574
 575/* Generate simple accessor wrapper */
 576#define __BUILD_KVM_RW_WRAP(name1, name2, type)                         \
 577static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0)   \
 578{                                                                       \
 579        return kvm_read_##name2(cop0);                                  \
 580}                                                                       \
 581static inline void kvm_write_##name1(struct mips_coproc *cop0,          \
 582                                     __KVMT##type val)                  \
 583{                                                                       \
 584        kvm_write_##name2(cop0, val);                                   \
 585}
 586
 587/* Generate bitwise modifier wrapper */
 588#define __BUILD_KVM_SET_WRAP(name1, name2, type)                        \
 589static inline void kvm_set_##name1(struct mips_coproc *cop0,            \
 590                                   __KVMT##type val)                    \
 591{                                                                       \
 592        kvm_set_##name2(cop0, val);                                     \
 593}                                                                       \
 594static inline void kvm_clear_##name1(struct mips_coproc *cop0,          \
 595                                     __KVMT##type val)                  \
 596{                                                                       \
 597        kvm_clear_##name2(cop0, val);                                   \
 598}                                                                       \
 599static inline void kvm_change_##name1(struct mips_coproc *cop0,         \
 600                                      __KVMT##type mask,                \
 601                                      __KVMT##type val)                 \
 602{                                                                       \
 603        kvm_change_##name2(cop0, mask, val);                            \
 604}
 605
 606/*
 607 * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
 608 * These generate accessors operating on the saved context in RAM, and wrap them
 609 * with the common guest C0 accessors (for use by common emulation code).
 610 */
 611
 612#define __BUILD_KVM_RW_SW(name, type, _reg, sel)                        \
 613        __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 614        __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
 615
 616#define __BUILD_KVM_SET_SW(name, type, _reg, sel)                       \
 617        __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 618        __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 619
 620#define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel)                    \
 621        __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 622        __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 623
 624#ifndef CONFIG_KVM_MIPS_VZ
 625
 626/*
 627 * T&E (trap & emulate software based virtualisation)
 628 * We generate the common accessors operating exclusively on the saved context
 629 * in RAM.
 630 */
 631
 632#define __BUILD_KVM_RW_HW       __BUILD_KVM_RW_SW
 633#define __BUILD_KVM_SET_HW      __BUILD_KVM_SET_SW
 634#define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_ATOMIC_SW
 635
 636#else
 637
 638/*
 639 * VZ (hardware assisted virtualisation)
 640 * These macros use the active guest state in VZ mode (hardware registers),
 641 */
 642
 643/*
 644 * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
 645 * These generate accessors operating on the VZ guest context in hardware, and
 646 * wrap them with the common guest C0 accessors (for use by common emulation
 647 * code).
 648 *
 649 * Accessors operating on the saved context in RAM are also generated to allow
 650 * convenient explicit saving and restoring of the state.
 651 */
 652
 653#define __BUILD_KVM_RW_HW(name, type, _reg, sel)                        \
 654        __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 655        __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 656        __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type)       \
 657        __BUILD_KVM_SAVE_VZ(name, _reg, sel)
 658
 659#define __BUILD_KVM_SET_HW(name, type, _reg, sel)                       \
 660        __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 661        __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 662        __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
 663
 664/*
 665 * We can't do atomic modifications of COP0 state if hardware can modify it.
 666 * Races must be handled explicitly.
 667 */
 668#define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_SET_HW
 669
 670#endif
 671
 672/*
 673 * Define accessors for CP0 registers that are accessible to the guest. These
 674 * are primarily used by common emulation code, which may need to access the
 675 * registers differently depending on the implementation.
 676 *
 677 *    fns_hw/sw    name     type    reg num         select
 678 */
 679__BUILD_KVM_RW_HW(index,          32, MIPS_CP0_TLB_INDEX,    0)
 680__BUILD_KVM_RW_HW(entrylo0,       l,  MIPS_CP0_TLB_LO0,      0)
 681__BUILD_KVM_RW_HW(entrylo1,       l,  MIPS_CP0_TLB_LO1,      0)
 682__BUILD_KVM_RW_HW(context,        l,  MIPS_CP0_TLB_CONTEXT,  0)
 683__BUILD_KVM_RW_HW(contextconfig,  32, MIPS_CP0_TLB_CONTEXT,  1)
 684__BUILD_KVM_RW_HW(userlocal,      l,  MIPS_CP0_TLB_CONTEXT,  2)
 685__BUILD_KVM_RW_HW(xcontextconfig, l,  MIPS_CP0_TLB_CONTEXT,  3)
 686__BUILD_KVM_RW_HW(pagemask,       l,  MIPS_CP0_TLB_PG_MASK,  0)
 687__BUILD_KVM_RW_HW(pagegrain,      32, MIPS_CP0_TLB_PG_MASK,  1)
 688__BUILD_KVM_RW_HW(segctl0,        l,  MIPS_CP0_TLB_PG_MASK,  2)
 689__BUILD_KVM_RW_HW(segctl1,        l,  MIPS_CP0_TLB_PG_MASK,  3)
 690__BUILD_KVM_RW_HW(segctl2,        l,  MIPS_CP0_TLB_PG_MASK,  4)
 691__BUILD_KVM_RW_HW(pwbase,         l,  MIPS_CP0_TLB_PG_MASK,  5)
 692__BUILD_KVM_RW_HW(pwfield,        l,  MIPS_CP0_TLB_PG_MASK,  6)
 693__BUILD_KVM_RW_HW(pwsize,         l,  MIPS_CP0_TLB_PG_MASK,  7)
 694__BUILD_KVM_RW_HW(wired,          32, MIPS_CP0_TLB_WIRED,    0)
 695__BUILD_KVM_RW_HW(pwctl,          32, MIPS_CP0_TLB_WIRED,    6)
 696__BUILD_KVM_RW_HW(hwrena,         32, MIPS_CP0_HWRENA,       0)
 697__BUILD_KVM_RW_HW(badvaddr,       l,  MIPS_CP0_BAD_VADDR,    0)
 698__BUILD_KVM_RW_HW(badinstr,       32, MIPS_CP0_BAD_VADDR,    1)
 699__BUILD_KVM_RW_HW(badinstrp,      32, MIPS_CP0_BAD_VADDR,    2)
 700__BUILD_KVM_RW_SW(count,          32, MIPS_CP0_COUNT,        0)
 701__BUILD_KVM_RW_HW(entryhi,        l,  MIPS_CP0_TLB_HI,       0)
 702__BUILD_KVM_RW_HW(compare,        32, MIPS_CP0_COMPARE,      0)
 703__BUILD_KVM_RW_HW(status,         32, MIPS_CP0_STATUS,       0)
 704__BUILD_KVM_RW_HW(intctl,         32, MIPS_CP0_STATUS,       1)
 705__BUILD_KVM_RW_HW(cause,          32, MIPS_CP0_CAUSE,        0)
 706__BUILD_KVM_RW_HW(epc,            l,  MIPS_CP0_EXC_PC,       0)
 707__BUILD_KVM_RW_SW(prid,           32, MIPS_CP0_PRID,         0)
 708__BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
 709__BUILD_KVM_RW_HW(config,         32, MIPS_CP0_CONFIG,       0)
 710__BUILD_KVM_RW_HW(config1,        32, MIPS_CP0_CONFIG,       1)
 711__BUILD_KVM_RW_HW(config2,        32, MIPS_CP0_CONFIG,       2)
 712__BUILD_KVM_RW_HW(config3,        32, MIPS_CP0_CONFIG,       3)
 713__BUILD_KVM_RW_HW(config4,        32, MIPS_CP0_CONFIG,       4)
 714__BUILD_KVM_RW_HW(config5,        32, MIPS_CP0_CONFIG,       5)
 715__BUILD_KVM_RW_HW(config6,        32, MIPS_CP0_CONFIG,       6)
 716__BUILD_KVM_RW_HW(config7,        32, MIPS_CP0_CONFIG,       7)
 717__BUILD_KVM_RW_SW(maari,          l,  MIPS_CP0_LLADDR,       2)
 718__BUILD_KVM_RW_HW(xcontext,       l,  MIPS_CP0_TLB_XCONTEXT, 0)
 719__BUILD_KVM_RW_HW(errorepc,       l,  MIPS_CP0_ERROR_PC,     0)
 720__BUILD_KVM_RW_HW(kscratch1,      l,  MIPS_CP0_DESAVE,       2)
 721__BUILD_KVM_RW_HW(kscratch2,      l,  MIPS_CP0_DESAVE,       3)
 722__BUILD_KVM_RW_HW(kscratch3,      l,  MIPS_CP0_DESAVE,       4)
 723__BUILD_KVM_RW_HW(kscratch4,      l,  MIPS_CP0_DESAVE,       5)
 724__BUILD_KVM_RW_HW(kscratch5,      l,  MIPS_CP0_DESAVE,       6)
 725__BUILD_KVM_RW_HW(kscratch6,      l,  MIPS_CP0_DESAVE,       7)
 726
 727/* Bitwise operations (on HW state) */
 728__BUILD_KVM_SET_HW(status,        32, MIPS_CP0_STATUS,       0)
 729/* Cause can be modified asynchronously from hardirq hrtimer callback */
 730__BUILD_KVM_ATOMIC_HW(cause,      32, MIPS_CP0_CAUSE,        0)
 731__BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
 732
 733/* Bitwise operations (on saved state) */
 734__BUILD_KVM_SET_SAVED(config,     32, MIPS_CP0_CONFIG,       0)
 735__BUILD_KVM_SET_SAVED(config1,    32, MIPS_CP0_CONFIG,       1)
 736__BUILD_KVM_SET_SAVED(config2,    32, MIPS_CP0_CONFIG,       2)
 737__BUILD_KVM_SET_SAVED(config3,    32, MIPS_CP0_CONFIG,       3)
 738__BUILD_KVM_SET_SAVED(config4,    32, MIPS_CP0_CONFIG,       4)
 739__BUILD_KVM_SET_SAVED(config5,    32, MIPS_CP0_CONFIG,       5)
 740
 741/* Helpers */
 742
 743static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 744{
 745        return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
 746                vcpu->fpu_enabled;
 747}
 748
 749static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 750{
 751        return kvm_mips_guest_can_have_fpu(vcpu) &&
 752                kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 753}
 754
 755static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 756{
 757        return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 758                vcpu->msa_enabled;
 759}
 760
 761static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 762{
 763        return kvm_mips_guest_can_have_msa(vcpu) &&
 764                kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 765}
 766
 767struct kvm_mips_callbacks {
 768        int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 769        int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 770        int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 771        int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 772        int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 773        int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 774        int (*handle_syscall)(struct kvm_vcpu *vcpu);
 775        int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 776        int (*handle_break)(struct kvm_vcpu *vcpu);
 777        int (*handle_trap)(struct kvm_vcpu *vcpu);
 778        int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 779        int (*handle_fpe)(struct kvm_vcpu *vcpu);
 780        int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 781        int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
 782        int (*hardware_enable)(void);
 783        void (*hardware_disable)(void);
 784        int (*check_extension)(struct kvm *kvm, long ext);
 785        int (*vcpu_init)(struct kvm_vcpu *vcpu);
 786        void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
 787        int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 788        void (*flush_shadow_all)(struct kvm *kvm);
 789        /*
 790         * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
 791         * VZ root TLB, or T&E GVA page tables and corresponding root TLB
 792         * mappings).
 793         */
 794        void (*flush_shadow_memslot)(struct kvm *kvm,
 795                                     const struct kvm_memory_slot *slot);
 796        gpa_t (*gva_to_gpa)(gva_t gva);
 797        void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 798        void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 799        void (*queue_io_int)(struct kvm_vcpu *vcpu,
 800                             struct kvm_mips_interrupt *irq);
 801        void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 802                               struct kvm_mips_interrupt *irq);
 803        int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 804                           u32 cause);
 805        int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 806                         u32 cause);
 807        unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
 808        int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
 809        int (*get_one_reg)(struct kvm_vcpu *vcpu,
 810                           const struct kvm_one_reg *reg, s64 *v);
 811        int (*set_one_reg)(struct kvm_vcpu *vcpu,
 812                           const struct kvm_one_reg *reg, s64 v);
 813        int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
 814        int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
 815        int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 816        void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 817};
 818extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 819int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 820
 821/* Debug: dump vcpu state */
 822int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 823
 824extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
 825
 826/* Building of entry/exception code */
 827int kvm_mips_entry_setup(void);
 828void *kvm_mips_build_vcpu_run(void *addr);
 829void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
 830void *kvm_mips_build_exception(void *addr, void *handler);
 831void *kvm_mips_build_exit(void *addr);
 832
 833/* FPU/MSA context management */
 834void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 835void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 836void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 837void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 838void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 839void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 840void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 841void kvm_own_fpu(struct kvm_vcpu *vcpu);
 842void kvm_own_msa(struct kvm_vcpu *vcpu);
 843void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 844void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 845
 846/* TLB handling */
 847u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 848
 849u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
 850
 851u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 852
 853#ifdef CONFIG_KVM_MIPS_VZ
 854int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
 855                                      struct kvm_vcpu *vcpu, bool write_fault);
 856#endif
 857extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 858                                           struct kvm_vcpu *vcpu,
 859                                           bool write_fault);
 860
 861extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 862                                              struct kvm_vcpu *vcpu);
 863
 864extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 865                                                struct kvm_mips_tlb *tlb,
 866                                                unsigned long gva,
 867                                                bool write_fault);
 868
 869extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
 870                                                     u32 *opc,
 871                                                     struct kvm_run *run,
 872                                                     struct kvm_vcpu *vcpu,
 873                                                     bool write_fault);
 874
 875extern void kvm_mips_dump_host_tlbs(void);
 876extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 877extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
 878                                 bool user, bool kernel);
 879
 880extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 881                                     unsigned long entryhi);
 882
 883#ifdef CONFIG_KVM_MIPS_VZ
 884int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 885int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
 886                            unsigned long *gpa);
 887void kvm_vz_local_flush_roottlb_all_guests(void);
 888void kvm_vz_local_flush_guesttlb_all(void);
 889void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
 890                          unsigned int count);
 891void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
 892                          unsigned int count);
 893#endif
 894
 895void kvm_mips_suspend_mm(int cpu);
 896void kvm_mips_resume_mm(int cpu);
 897
 898/* MMU handling */
 899
 900/**
 901 * enum kvm_mips_flush - Types of MMU flushes.
 902 * @KMF_USER:   Flush guest user virtual memory mappings.
 903 *              Guest USeg only.
 904 * @KMF_KERN:   Flush guest kernel virtual memory mappings.
 905 *              Guest USeg and KSeg2/3.
 906 * @KMF_GPA:    Flush guest physical memory mappings.
 907 *              Also includes KSeg0 if KMF_KERN is set.
 908 */
 909enum kvm_mips_flush {
 910        KMF_USER        = 0x0,
 911        KMF_KERN        = 0x1,
 912        KMF_GPA         = 0x2,
 913};
 914void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
 915bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 916int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 917pgd_t *kvm_pgd_alloc(void);
 918void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 919void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
 920                                  bool user);
 921void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
 922void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
 923
 924enum kvm_mips_fault_result {
 925        KVM_MIPS_MAPPED = 0,
 926        KVM_MIPS_GVA,
 927        KVM_MIPS_GPA,
 928        KVM_MIPS_TLB,
 929        KVM_MIPS_TLBINV,
 930        KVM_MIPS_TLBMOD,
 931};
 932enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
 933                                                   unsigned long gva,
 934                                                   bool write);
 935
 936#define KVM_ARCH_WANT_MMU_NOTIFIER
 937int kvm_unmap_hva_range(struct kvm *kvm,
 938                        unsigned long start, unsigned long end);
 939int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 940int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 941int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 942
 943/* Emulation */
 944int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 945enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
 946int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 947int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 948
 949/**
 950 * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
 951 * @vcpu:       Virtual CPU.
 952 *
 953 * Returns:     Whether the TLBL exception was likely due to an instruction
 954 *              fetch fault rather than a data load fault.
 955 */
 956static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
 957{
 958        unsigned long badvaddr = vcpu->host_cp0_badvaddr;
 959        unsigned long epc = msk_isa16_mode(vcpu->pc);
 960        u32 cause = vcpu->host_cp0_cause;
 961
 962        if (epc == badvaddr)
 963                return true;
 964
 965        /*
 966         * Branches may be 32-bit or 16-bit instructions.
 967         * This isn't exact, but we don't really support MIPS16 or microMIPS yet
 968         * in KVM anyway.
 969         */
 970        if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
 971                return true;
 972
 973        return false;
 974}
 975
 976extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
 977                                                   u32 *opc,
 978                                                   struct kvm_run *run,
 979                                                   struct kvm_vcpu *vcpu);
 980
 981long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
 982
 983extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
 984                                                      u32 *opc,
 985                                                      struct kvm_run *run,
 986                                                      struct kvm_vcpu *vcpu);
 987
 988extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
 989                                                         u32 *opc,
 990                                                         struct kvm_run *run,
 991                                                         struct kvm_vcpu *vcpu);
 992
 993extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
 994                                                        u32 *opc,
 995                                                        struct kvm_run *run,
 996                                                        struct kvm_vcpu *vcpu);
 997
 998extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
 999                                                         u32 *opc,
1000                                                         struct kvm_run *run,

1001                                                         struct kvm_vcpu *vcpu);
1002
1003extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
1004                                                        u32 *opc,
1005                                                        struct kvm_run *run,
1006                                                        struct kvm_vcpu *vcpu);
1007
1008extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1009                                                     u32 *opc,
1010                                                     struct kvm_run *run,
1011                                                     struct kvm_vcpu *vcpu);
1012
1013extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
1014                                                      u32 *opc,
1015                                                      struct kvm_run *run,
1016                                                      struct kvm_vcpu *vcpu);
1017
1018extern enum emulation_result kvm_mips_handle_ri(u32 cause,
1019                                                u32 *opc,
1020                                                struct kvm_run *run,
1021                                                struct kvm_vcpu *vcpu);
1022
1023extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
1024                                                     u32 *opc,
1025                                                     struct kvm_run *run,
1026                                                     struct kvm_vcpu *vcpu);
1027
1028extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
1029                                                     u32 *opc,
1030                                                     struct kvm_run *run,
1031                                                     struct kvm_vcpu *vcpu);
1032
1033extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
1034                                                       u32 *opc,
1035                                                       struct kvm_run *run,
1036                                                       struct kvm_vcpu *vcpu);
1037
1038extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
1039                                                         u32 *opc,
1040                                                         struct kvm_run *run,
1041                                                         struct kvm_vcpu *vcpu);
1042
1043extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
1044                                                      u32 *opc,
1045                                                      struct kvm_run *run,
1046                                                      struct kvm_vcpu *vcpu);
1047
1048extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
1049                                                         u32 *opc,
1050                                                         struct kvm_run *run,
1051                                                         struct kvm_vcpu *vcpu);
1052
1053extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
1054                                                         struct kvm_run *run);
1055
1056u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
1057void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
1058void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
1059void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
1060int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
1061int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
1062int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
1063void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
1064void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
1065enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
1066
1067/* fairly internal functions requiring some care to use */
1068int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
1069ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
1070int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
1071                             u32 count, int min_drift);
1072
1073#ifdef CONFIG_KVM_MIPS_VZ
1074void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
1075void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
1076#else
1077static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {}
1078static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {}
1079#endif
1080
1081enum emulation_result kvm_mips_check_privilege(u32 cause,
1082                                               u32 *opc,
1083                                               struct kvm_run *run,
1084                                               struct kvm_vcpu *vcpu);
1085
1086enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
1087                                             u32 *opc,
1088                                             u32 cause,
1089                                             struct kvm_run *run,
1090                                             struct kvm_vcpu *vcpu);
1091enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
1092                                           u32 *opc,
1093                                           u32 cause,
1094                                           struct kvm_run *run,
1095                                           struct kvm_vcpu *vcpu);
1096enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1097                                             u32 cause,
1098                                             struct kvm_run *run,
1099                                             struct kvm_vcpu *vcpu);
1100enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1101                                            u32 cause,
1102                                            struct kvm_run *run,
1103                                            struct kvm_vcpu *vcpu);
1104
1105/* COP0 */
1106enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
1107
1108unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
1109unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
1110unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
1111unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
1112
1113/* Hypercalls (hypcall.c) */
1114
1115enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
1116                                            union mips_instruction inst);
1117int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
1118
1119/* Dynamic binary translation */
1120extern int kvm_mips_trans_cache_index(union mips_instruction inst,
1121                                      u32 *opc, struct kvm_vcpu *vcpu);
1122extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
1123                                   struct kvm_vcpu *vcpu);
1124extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
1125                               struct kvm_vcpu *vcpu);
1126extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
1127                               struct kvm_vcpu *vcpu);
1128
1129/* Misc */
1130extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
1131extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
1132
1133static inline void kvm_arch_hardware_unsetup(void) {}
1134static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1135static inline void kvm_arch_free_memslot(struct kvm *kvm,
1136                struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
1137static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
1138static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1139static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
1140static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
1141static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1142
1143#endif /* __MIPS_KVM_HOST_H__ */
1144