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7#ifndef __ASM_MACH_JZ4740_TIMER
8#define __ASM_MACH_JZ4740_TIMER
9
10#define JZ_REG_TIMER_STOP 0x0C
11#define JZ_REG_TIMER_STOP_SET 0x1C
12#define JZ_REG_TIMER_STOP_CLEAR 0x2C
13#define JZ_REG_TIMER_ENABLE 0x00
14#define JZ_REG_TIMER_ENABLE_SET 0x04
15#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
16#define JZ_REG_TIMER_FLAG 0x10
17#define JZ_REG_TIMER_FLAG_SET 0x14
18#define JZ_REG_TIMER_FLAG_CLEAR 0x18
19#define JZ_REG_TIMER_MASK 0x20
20#define JZ_REG_TIMER_MASK_SET 0x24
21#define JZ_REG_TIMER_MASK_CLEAR 0x28
22
23#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
24#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
25#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
26#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
27
28#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
29#define JZ_TIMER_IRQ_FULL(x) BIT(x)
30
31#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
32#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
33#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
34#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
35#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
36#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
37#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
38#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
39#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
40#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
41#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
42
43#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
44
45#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
46#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
47#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
48
49extern void __iomem *jz4740_timer_base;
50void __init jz4740_timer_init(void);
51
52void jz4740_timer_enable_watchdog(void);
53void jz4740_timer_disable_watchdog(void);
54
55static inline void jz4740_timer_stop(unsigned int timer)
56{
57 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
58}
59
60static inline void jz4740_timer_start(unsigned int timer)
61{
62 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
63}
64
65static inline bool jz4740_timer_is_enabled(unsigned int timer)
66{
67 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
68}
69
70static inline void jz4740_timer_enable(unsigned int timer)
71{
72 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
73}
74
75static inline void jz4740_timer_disable(unsigned int timer)
76{
77 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
78}
79
80static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
81{
82 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
83}
84
85static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
86{
87 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
88}
89
90static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
91{
92 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
93}
94
95static inline uint16_t jz4740_timer_get_count(unsigned int timer)
96{
97 return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
98}
99
100static inline void jz4740_timer_ack_full(unsigned int timer)
101{
102 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
103}
104
105static inline void jz4740_timer_irq_full_enable(unsigned int timer)
106{
107 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
108 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
109}
110
111static inline void jz4740_timer_irq_full_disable(unsigned int timer)
112{
113 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
114}
115
116static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
117{
118 writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
119}
120
121static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
122{
123 return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
124}
125
126#endif
127
