1/* 2 * Definitions for the DDR registers 3 * 4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com> 5 * Copyright 2008 Florian Fainelli <florian@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 */ 28 29#ifndef _ASM_RC32434_DDR_H_ 30#define _ASM_RC32434_DDR_H_ 31 32#include <asm/mach-rc32434/rb.h> 33 34/* DDR register structure */ 35struct ddr_ram { 36 u32 ddrbase; 37 u32 ddrmask; 38 u32 res1; 39 u32 res2; 40 u32 ddrc; 41 u32 ddrabase; 42 u32 ddramask; 43 u32 ddramap; 44 u32 ddrcust; 45 u32 ddrrdc; 46 u32 ddrspare; 47}; 48 49#define DDR0_PHYS_ADDR 0x18018000 50 51/* DDR banks masks */ 52#define DDR_MASK 0xffff0000 53#define DDR0_BASE_MSK DDR_MASK 54#define DDR1_BASE_MSK DDR_MASK 55 56/* DDR bank0 registers */ 57#define RC32434_DDR0_ATA_BIT 5 58#define RC32434_DDR0_ATA_MSK 0x000000E0 59#define RC32434_DDR0_DBW_BIT 8 60#define RC32434_DDR0_DBW_MSK 0x00000100 61#define RC32434_DDR0_WR_BIT 9 62#define RC32434_DDR0_WR_MSK 0x00000600 63#define RC32434_DDR0_PS_BIT 11 64#define RC32434_DDR0_PS_MSK 0x00001800 65#define RC32434_DDR0_DTYPE_BIT 13 66#define RC32434_DDR0_DTYPE_MSK 0x0000e000 67#define RC32434_DDR0_RFC_BIT 16 68#define RC32434_DDR0_RFC_MSK 0x000f0000 69#define RC32434_DDR0_RP_BIT 20 70#define RC32434_DDR0_RP_MSK 0x00300000 71#define RC32434_DDR0_AP_BIT 22 72#define RC32434_DDR0_AP_MSK 0x00400000 73#define RC32434_DDR0_RCD_BIT 23 74#define RC32434_DDR0_RCD_MSK 0x01800000 75#define RC32434_DDR0_CL_BIT 25 76#define RC32434_DDR0_CL_MSK 0x06000000 77#define RC32434_DDR0_DBM_BIT 27 78#define RC32434_DDR0_DBM_MSK 0x08000000 79#define RC32434_DDR0_SDS_BIT 28 80#define RC32434_DDR0_SDS_MSK 0x10000000 81#define RC32434_DDR0_ATP_BIT 29 82#define RC32434_DDR0_ATP_MSK 0x60000000 83#define RC32434_DDR0_RE_BIT 31 84#define RC32434_DDR0_RE_MSK 0x80000000 85 86/* DDR bank C registers */ 87#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x) 88#define RC32434_DDRC_CES_BIT 0 89#define RC32434_DDRC_ACE_BIT 1 90 91/* Custom DDR bank registers */ 92#define RC32434_DCST_MSK(x) BIT_TO_MASK(x) 93#define RC32434_DCST_CS_BIT 0 94#define RC32434_DCST_CS_MSK 0x00000003 95#define RC32434_DCST_WE_BIT 2 96#define RC32434_DCST_RAS_BIT 3 97#define RC32434_DCST_CAS_BIT 4 98#define RC32434_DSCT_CKE_BIT 5 99#define RC32434_DSCT_BA_BIT 6 100#define RC32434_DSCT_BA_MSK 0x000000c0 101 102/* DDR QSC registers */ 103#define RC32434_QSC_DM_BIT 0 104#define RC32434_QSC_DM_MSK 0x00000003 105#define RC32434_QSC_DQSBS_BIT 2 106#define RC32434_QSC_DQSBS_MSK 0x000000fc 107#define RC32434_QSC_DB_BIT 8 108#define RC32434_QSC_DB_MSK 0x00000100 109#define RC32434_QSC_DBSP_BIT 9 110#define RC32434_QSC_DBSP_MSK 0x01fffe00 111#define RC32434_QSC_BDP_BIT 25 112#define RC32434_QSC_BDP_MSK 0x7e000000 113 114/* DDR LLC registers */ 115#define RC32434_LLC_EAO_BIT 0 116#define RC32434_LLC_EAO_MSK 0x00000001 117#define RC32434_LLC_EO_BIT 1 118#define RC32434_LLC_EO_MSK 0x0000003e 119#define RC32434_LLC_FS_BIT 6 120#define RC32434_LLC_FS_MSK 0x000000c0 121#define RC32434_LLC_AS_BIT 8 122#define RC32434_LLC_AS_MSK 0x00000700 123#define RC32434_LLC_SP_BIT 11 124#define RC32434_LLC_SP_MSK 0x001ff800 125 126/* DDR LLFC registers */ 127#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x) 128#define RC32434_LLFC_MEN_BIT 0 129#define RC32434_LLFC_EAN_BIT 1 130#define RC32434_LLFC_FF_BIT 2 131 132/* DDR DLLTA registers */ 133#define RC32434_DLLTA_ADDR_BIT 2 134#define RC32434_DLLTA_ADDR_MSK 0xfffffffc 135 136/* DDR DLLED registers */ 137#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x) 138#define RC32434_DLLED_DBE_BIT 0 139#define RC32434_DLLED_DTE_BIT 1 140 141#endif /* _ASM_RC32434_DDR_H_ */ 142