LXR linux/arch/mips/pci/ops-nile4.c

   1// SPDX-License-Identifier: GPL-2.0
   2#include <linux/kernel.h>
   3#include <linux/pci.h>
   4#include <asm/bootinfo.h>
   5
   6#include <asm/lasat/lasat.h>
   7#include <asm/nile4.h>
   8
   9#define PCI_ACCESS_READ  0
  10#define PCI_ACCESS_WRITE 1
  11
  12#define LO(reg) (reg / 4)
  13#define HI(reg) (reg / 4 + 1)
  14
  15volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
  16
  17static int nile4_pcibios_config_access(unsigned char access_type,
  18        struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
  19{
  20        unsigned char busnum = bus->number;
  21        u32 adr, mask, err;
  22
  23        if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
  24                /* The addressing scheme chosen leaves room for just
  25                 * 8 devices on the first busnum (besides the PCI
  26                 * controller itself) */
  27                return PCIBIOS_DEVICE_NOT_FOUND;
  28
  29        if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
  30                /* Access controller registers directly */
  31                if (access_type == PCI_ACCESS_WRITE) {
  32                        vrc_pciregs[(0x200 + where) >> 2] = *val;
  33                } else {
  34                        *val = vrc_pciregs[(0x200 + where) >> 2];
  35                }
  36                return PCIBIOS_SUCCESSFUL;
  37        }
  38
  39        /* Temporarily map PCI Window 1 to config space */
  40        mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
  41        vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
  42
  43        /* Clear PCI Error register. This also clears the Error Type
  44         * bits in the Control register */
  45        vrc_pciregs[LO(NILE4_PCIERR)] = 0;
  46        vrc_pciregs[HI(NILE4_PCIERR)] = 0;
  47
  48        /* Setup address */
  49        if (busnum == 0)
  50                adr =
  51                    KSEG1ADDR(PCI_WINDOW1) +
  52                    ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
  53                     | (where & ~3));
  54        else
  55                adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
  56                      (where & ~3);
  57
  58        if (access_type == PCI_ACCESS_WRITE)
  59                *(u32 *) adr = *val;
  60        else
  61                *val = *(u32 *) adr;
  62
  63        /* Check for master or target abort */
  64        err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
  65
  66        /* Restore PCI Window 1 */
  67        vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
  68
  69        if (err)
  70                return PCIBIOS_DEVICE_NOT_FOUND;
  71
  72        return PCIBIOS_SUCCESSFUL;
  73}
  74
  75static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  76        int where, int size, u32 *val)
  77{
  78        u32 data = 0;
  79        int err;
  80
  81        if ((size == 2) && (where & 1))
  82                return PCIBIOS_BAD_REGISTER_NUMBER;
  83        else if ((size == 4) && (where & 3))
  84                return PCIBIOS_BAD_REGISTER_NUMBER;
  85
  86        err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
  87                                          &data);
  88        if (err)
  89                return err;
  90
  91        if (size == 1)
  92                *val = (data >> ((where & 3) << 3)) & 0xff;
  93        else if (size == 2)
  94                *val = (data >> ((where & 3) << 3)) & 0xffff;
  95        else
  96                *val = data;
  97
  98        return PCIBIOS_SUCCESSFUL;
  99}
 100
 101static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 102        int where, int size, u32 val)
 103{
 104        u32 data = 0;
 105        int err;
 106
 107        if ((size == 2) && (where & 1))
 108                return PCIBIOS_BAD_REGISTER_NUMBER;
 109        else if ((size == 4) && (where & 3))
 110                return PCIBIOS_BAD_REGISTER_NUMBER;
 111
 112        err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 113                                          &data);
 114        if (err)
 115                return err;
 116
 117        if (size == 1)
 118                data = (data & ~(0xff << ((where & 3) << 3))) |
 119                    (val << ((where & 3) << 3));
 120        else if (size == 2)
 121                data = (data & ~(0xffff << ((where & 3) << 3))) |
 122                    (val << ((where & 3) << 3));
 123        else
 124                data = val;
 125
 126        if (nile4_pcibios_config_access
 127            (PCI_ACCESS_WRITE, bus, devfn, where, &data))
 128                return -1;
 129
 130        return PCIBIOS_SUCCESSFUL;
 131}
 132
 133struct pci_ops nile4_pci_ops = {
 134        .read = nile4_pcibios_read,
 135        .write = nile4_pcibios_write,
 136};
 137