LXR linux/arch/mips/pci/pci-ar2315.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 */
   4
   5/**
   6 * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
   7 * and interrupt. PCI interface supports MMIO access method, but does not
   8 * seem to support I/O ports.
   9 *
  10 * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  11 * a memory read/write command on the PCI bus. 30 LSBs of address on
  12 * the bus are taken from memory read/write request and 2 MSBs are
  13 * determined by PCI unit configuration.
  14 *
  15 * To work with the configuration space instead of memory is necessary set
  16 * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  17 *
  18 * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  19 * controller BARs are programmend as if an external device is programmed.
  20 * Which means that during configuration, IDSEL pin of the chip should be
  21 * asserted.
  22 *
  23 * We know (and support) only one board that uses the PCI interface -
  24 * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  25 * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  26 * and IDSEL pin of AR2315 is connected to AD[16] line.
  27 */
  28
  29#include <linux/types.h>
  30#include <linux/pci.h>
  31#include <linux/platform_device.h>
  32#include <linux/kernel.h>
  33#include <linux/init.h>
  34#include <linux/mm.h>
  35#include <linux/delay.h>
  36#include <linux/bitops.h>
  37#include <linux/irq.h>
  38#include <linux/irqdomain.h>
  39#include <linux/io.h>
  40#include <asm/paccess.h>
  41
  42/*
  43 * PCI Bus Interface Registers
  44 */
  45#define AR2315_PCI_1MS_REG              0x0008
  46
  47#define AR2315_PCI_1MS_MASK             0x3FFFF /* # of AHB clk cycles in 1ms */
  48
  49#define AR2315_PCI_MISC_CONFIG          0x000c
  50
  51#define AR2315_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
  52#define AR2315_PCIMISC_CFG_SEL  0x00000002      /* Mem or Config cycles */
  53#define AR2315_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
  54#define AR2315_PCIMISC_RST_MODE 0x00000030
  55#define AR2315_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
  56#define AR2315_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
  57#define AR2315_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
  58#define AR2315_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
  59#define AR2315_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
  60#define AR2315_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
  61#define AR2315_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
  62#define AR2315_PCICACHE_DIS     0x00001000      /* PCI external access cache
  63                                                 * disable */
  64
  65#define AR2315_PCI_OUT_TSTAMP           0x0010
  66
  67#define AR2315_PCI_UNCACHE_CFG          0x0014
  68
  69#define AR2315_PCI_IN_EN                0x0100
  70
  71#define AR2315_PCI_IN_EN0       0x01    /* Enable chain 0 */
  72#define AR2315_PCI_IN_EN1       0x02    /* Enable chain 1 */
  73#define AR2315_PCI_IN_EN2       0x04    /* Enable chain 2 */
  74#define AR2315_PCI_IN_EN3       0x08    /* Enable chain 3 */
  75
  76#define AR2315_PCI_IN_DIS               0x0104
  77
  78#define AR2315_PCI_IN_DIS0      0x01    /* Disable chain 0 */
  79#define AR2315_PCI_IN_DIS1      0x02    /* Disable chain 1 */
  80#define AR2315_PCI_IN_DIS2      0x04    /* Disable chain 2 */
  81#define AR2315_PCI_IN_DIS3      0x08    /* Disable chain 3 */
  82
  83#define AR2315_PCI_IN_PTR               0x0200
  84
  85#define AR2315_PCI_OUT_EN               0x0400
  86
  87#define AR2315_PCI_OUT_EN0      0x01    /* Enable chain 0 */
  88
  89#define AR2315_PCI_OUT_DIS              0x0404
  90
  91#define AR2315_PCI_OUT_DIS0     0x01    /* Disable chain 0 */
  92
  93#define AR2315_PCI_OUT_PTR              0x0408
  94
  95/* PCI interrupt status (write one to clear) */
  96#define AR2315_PCI_ISR                  0x0500
  97
  98#define AR2315_PCI_INT_TX       0x00000001      /* Desc In Completed */
  99#define AR2315_PCI_INT_TXOK     0x00000002      /* Desc In OK */
 100#define AR2315_PCI_INT_TXERR    0x00000004      /* Desc In ERR */
 101#define AR2315_PCI_INT_TXEOL    0x00000008      /* Desc In End-of-List */
 102#define AR2315_PCI_INT_RX       0x00000010      /* Desc Out Completed */
 103#define AR2315_PCI_INT_RXOK     0x00000020      /* Desc Out OK */
 104#define AR2315_PCI_INT_RXERR    0x00000040      /* Desc Out ERR */
 105#define AR2315_PCI_INT_RXEOL    0x00000080      /* Desc Out EOL */
 106#define AR2315_PCI_INT_TXOOD    0x00000200      /* Desc In Out-of-Desc */
 107#define AR2315_PCI_INT_DESCMASK 0x0000FFFF      /* Desc Mask */
 108#define AR2315_PCI_INT_EXT      0x02000000      /* Extern PCI INTA */
 109#define AR2315_PCI_INT_ABORT    0x04000000      /* PCI bus abort event */
 110
 111/* PCI interrupt mask */
 112#define AR2315_PCI_IMR                  0x0504
 113
 114/* Global PCI interrupt enable */
 115#define AR2315_PCI_IER                  0x0508
 116
 117#define AR2315_PCI_IER_DISABLE          0x00    /* disable pci interrupts */
 118#define AR2315_PCI_IER_ENABLE           0x01    /* enable pci interrupts */
 119
 120#define AR2315_PCI_HOST_IN_EN           0x0800
 121#define AR2315_PCI_HOST_IN_DIS          0x0804
 122#define AR2315_PCI_HOST_IN_PTR          0x0810
 123#define AR2315_PCI_HOST_OUT_EN          0x0900
 124#define AR2315_PCI_HOST_OUT_DIS         0x0904
 125#define AR2315_PCI_HOST_OUT_PTR         0x0908
 126
 127/*
 128 * PCI interrupts, which share IP5
 129 * Keep ordered according to AR2315_PCI_INT_XXX bits
 130 */
 131#define AR2315_PCI_IRQ_EXT              25
 132#define AR2315_PCI_IRQ_ABORT            26
 133#define AR2315_PCI_IRQ_COUNT            27
 134
 135/* Arbitrary size of memory region to access the configuration space */
 136#define AR2315_PCI_CFG_SIZE     0x00100000
 137
 138#define AR2315_PCI_HOST_SLOT    3
 139#define AR2315_PCI_HOST_DEVID   ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
 140
 141/*
 142 * We need some arbitrary non-zero value to be programmed to the BAR1 register
 143 * of PCI host controller to enable DMA. The same value should be used as the
 144 * offset to calculate the physical address of DMA buffer for PCI devices.
 145 */
 146#define AR2315_PCI_HOST_SDRAM_BASEADDR  0x20000000
 147
 148/* ??? access BAR */
 149#define AR2315_PCI_HOST_MBAR0           0x10000000
 150/* RAM access BAR */
 151#define AR2315_PCI_HOST_MBAR1           AR2315_PCI_HOST_SDRAM_BASEADDR
 152/* ??? access BAR */
 153#define AR2315_PCI_HOST_MBAR2           0x30000000
 154
 155struct ar2315_pci_ctrl {
 156        void __iomem *cfg_mem;
 157        void __iomem *mmr_mem;
 158        unsigned irq;
 159        unsigned irq_ext;
 160        struct irq_domain *domain;
 161        struct pci_controller pci_ctrl;
 162        struct resource mem_res;
 163        struct resource io_res;
 164};
 165
 166static inline dma_addr_t ar2315_dev_offset(struct device *dev)
 167{
 168        if (dev && dev_is_pci(dev))
 169                return AR2315_PCI_HOST_SDRAM_BASEADDR;
 170        return 0;
 171}
 172
 173dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 174{
 175        return paddr + ar2315_dev_offset(dev);
 176}
 177
 178phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
 179{
 180        return dma_addr - ar2315_dev_offset(dev);
 181}
 182
 183static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
 184{
 185        struct pci_controller *hose = bus->sysdata;
 186
 187        return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
 188}
 189
 190static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
 191{
 192        return __raw_readl(apc->mmr_mem + reg);
 193}
 194
 195static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
 196                                        u32 val)
 197{
 198        __raw_writel(val, apc->mmr_mem + reg);
 199}
 200
 201static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
 202                                       u32 mask, u32 val)
 203{
 204        u32 ret = ar2315_pci_reg_read(apc, reg);
 205
 206        ret &= ~mask;
 207        ret |= val;
 208        ar2315_pci_reg_write(apc, reg, ret);
 209}
 210
 211static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
 212                                 int where, int size, u32 *ptr, bool write)
 213{
 214        int func = PCI_FUNC(devfn);
 215        int dev = PCI_SLOT(devfn);
 216        u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
 217        u32 mask = 0xffffffff >> 8 * (4 - size);
 218        u32 sh = (where & 3) * 8;
 219        u32 value, isr;
 220
 221        /* Prevent access past the remapped area */
 222        if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
 223                return PCIBIOS_DEVICE_NOT_FOUND;
 224
 225        /* Clear pending errors */
 226        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 227        /* Select Configuration access */
 228        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
 229                            AR2315_PCIMISC_CFG_SEL);
 230
 231        mb();   /* PCI must see space change before we begin */
 232
 233        value = __raw_readl(apc->cfg_mem + addr);
 234
 235        isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 236
 237        if (isr & AR2315_PCI_INT_ABORT)
 238                goto exit_err;
 239
 240        if (write) {
 241                value = (value & ~(mask << sh)) | *ptr << sh;
 242                __raw_writel(value, apc->cfg_mem + addr);
 243                isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 244                if (isr & AR2315_PCI_INT_ABORT)
 245                        goto exit_err;
 246        } else {
 247                *ptr = (value >> sh) & mask;
 248        }
 249
 250        goto exit;
 251
 252exit_err:
 253        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 254        if (!write)
 255                *ptr = 0xffffffff;
 256
 257exit:
 258        /* Select Memory access */
 259        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
 260                            0);
 261
 262        return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 263                                            PCIBIOS_SUCCESSFUL;
 264}
 265
 266static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
 267                                          unsigned devfn, int where, u32 *val)
 268{
 269        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
 270                                     false);
 271}
 272
 273static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
 274                                          unsigned devfn, int where, u32 val)
 275{
 276        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
 277                                     true);
 278}
 279
 280static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
 281                               int size, u32 *value)
 282{
 283        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 284
 285        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 286                return PCIBIOS_DEVICE_NOT_FOUND;
 287
 288        return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
 289}
 290
 291static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
 292                                int size, u32 value)
 293{
 294        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 295
 296        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 297                return PCIBIOS_DEVICE_NOT_FOUND;
 298
 299        return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
 300}
 301
 302static struct pci_ops ar2315_pci_ops = {
 303        .read   = ar2315_pci_cfg_read,
 304        .write  = ar2315_pci_cfg_write,
 305};
 306
 307static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
 308{
 309        unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 310        int res;
 311        u32 id;
 312
 313        res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
 314        if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 315                return -ENODEV;
 316
 317        /* Program MBARs */
 318        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
 319                                AR2315_PCI_HOST_MBAR0);
 320        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
 321                                AR2315_PCI_HOST_MBAR1);
 322        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
 323                                AR2315_PCI_HOST_MBAR2);
 324
 325        /* Run */
 326        ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 327                                PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 328                                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 329                                PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 330
 331        return 0;
 332}
 333
 334static void ar2315_pci_irq_handler(struct irq_desc *desc)
 335{
 336        struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
 337        u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
 338                      ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
 339        unsigned pci_irq = 0;
 340
 341        if (pending)
 342                pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
 343
 344        if (pci_irq)
 345                generic_handle_irq(pci_irq);
 346        else
 347                spurious_interrupt();
 348}
 349
 350static void ar2315_pci_irq_mask(struct irq_data *d)
 351{
 352        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 353
 354        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
 355}
 356
 357static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 358{
 359        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 360        u32 m = BIT(d->hwirq);
 361
 362        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
 363        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
 364}
 365
 366static void ar2315_pci_irq_unmask(struct irq_data *d)
 367{
 368        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 369
 370        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
 371}
 372
 373static struct irq_chip ar2315_pci_irq_chip = {
 374        .name = "AR2315-PCI",
 375        .irq_mask = ar2315_pci_irq_mask,
 376        .irq_mask_ack = ar2315_pci_irq_mask_ack,
 377        .irq_unmask = ar2315_pci_irq_unmask,
 378};
 379
 380static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
 381                              irq_hw_number_t hw)
 382{
 383        irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
 384        irq_set_chip_data(irq, d->host_data);
 385        return 0;
 386}
 387
 388static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
 389        .map = ar2315_pci_irq_map,
 390};
 391
 392static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
 393{
 394        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 395        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 396                            AR2315_PCI_INT_EXT), 0);
 397
 398        apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
 399
 400        irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
 401                                         apc);
 402
 403        /* Clear any pending Abort or external Interrupts
 404         * and enable interrupt processing */
 405        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
 406                                                  AR2315_PCI_INT_EXT);
 407        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 408}
 409
 410static int ar2315_pci_probe(struct platform_device *pdev)
 411{
 412        struct ar2315_pci_ctrl *apc;
 413        struct device *dev = &pdev->dev;
 414        struct resource *res;
 415        int irq, err;
 416
 417        apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
 418        if (!apc)
 419                return -ENOMEM;
 420
 421        irq = platform_get_irq(pdev, 0);
 422        if (irq < 0)
 423                return -EINVAL;
 424        apc->irq = irq;
 425
 426        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 427                                           "ar2315-pci-ctrl");
 428        apc->mmr_mem = devm_ioremap_resource(dev, res);
 429        if (IS_ERR(apc->mmr_mem))
 430                return PTR_ERR(apc->mmr_mem);
 431
 432        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 433                                           "ar2315-pci-ext");
 434        if (!res)
 435                return -EINVAL;
 436
 437        apc->mem_res.name = "AR2315 PCI mem space";
 438        apc->mem_res.parent = res;
 439        apc->mem_res.start = res->start;
 440        apc->mem_res.end = res->end;
 441        apc->mem_res.flags = IORESOURCE_MEM;
 442
 443        /* Remap PCI config space */
 444        apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
 445                                            AR2315_PCI_CFG_SIZE);
 446        if (!apc->cfg_mem) {
 447                dev_err(dev, "failed to remap PCI config space\n");
 448                return -ENOMEM;
 449        }
 450
 451        /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 452        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 453                            AR2315_PCIMISC_RST_MODE,
 454                            AR2315_PCIRST_LOW);
 455        msleep(100);
 456
 457        /* Bring the PCI out of reset */
 458        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 459                            AR2315_PCIMISC_RST_MODE,
 460                            AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 461
 462        ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
 463                             0x1E | /* 1GB uncached */
 464                             (1 << 5) | /* Enable uncached */
 465                             (0x2 << 30) /* Base: 0x80000000 */);
 466        ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
 467
 468        msleep(500);
 469
 470        err = ar2315_pci_host_setup(apc);
 471        if (err)
 472                return err;
 473
 474        apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
 475                                            &ar2315_pci_irq_domain_ops, apc);
 476        if (!apc->domain) {
 477                dev_err(dev, "failed to add IRQ domain\n");
 478                return -ENOMEM;
 479        }
 480
 481        ar2315_pci_irq_init(apc);
 482
 483        /* PCI controller does not support I/O ports */
 484        apc->io_res.name = "AR2315 IO space";
 485        apc->io_res.start = 0;
 486        apc->io_res.end = 0;
 487        apc->io_res.flags = IORESOURCE_IO,
 488
 489        apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
 490        apc->pci_ctrl.mem_resource = &apc->mem_res,
 491        apc->pci_ctrl.io_resource = &apc->io_res,
 492
 493        register_pci_controller(&apc->pci_ctrl);
 494
 495        dev_info(dev, "register PCI controller\n");
 496
 497        return 0;
 498}
 499
 500static struct platform_driver ar2315_pci_driver = {
 501        .probe = ar2315_pci_probe,
 502        .driver = {
 503                .name = "ar2315-pci",
 504        },
 505};
 506
 507static int __init ar2315_pci_init(void)
 508{
 509        return platform_driver_register(&ar2315_pci_driver);
 510}
 511arch_initcall(ar2315_pci_init);
 512
 513int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 514{
 515        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
 516
 517        return slot ? 0 : apc->irq_ext;
 518}
 519
 520int pcibios_plat_dev_init(struct pci_dev *dev)
 521{
 522        return 0;
 523}
 524