LXR linux/arch/powerpc/include/asm/book3s/64/mmu-hash.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
   3#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
   4/*
   5 * PowerPC64 memory management structures
   6 *
   7 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   8 *   PPC64 rework.
   9 */
  10
  11#include <asm/page.h>
  12#include <asm/bug.h>
  13#include <asm/asm-const.h>
  14
  15/*
  16 * This is necessary to get the definition of PGTABLE_RANGE which we
  17 * need for various slices related matters. Note that this isn't the
  18 * complete pgtable.h but only a portion of it.
  19 */
  20#include <asm/book3s/64/pgtable.h>
  21#include <asm/bug.h>
  22#include <asm/task_size_64.h>
  23#include <asm/cpu_has_feature.h>
  24
  25/*
  26 * SLB
  27 */
  28
  29#define SLB_NUM_BOLTED          2
  30#define SLB_CACHE_ENTRIES       8
  31#define SLB_MIN_SIZE            32
  32
  33/* Bits in the SLB ESID word */
  34#define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  35
  36/* Bits in the SLB VSID word */
  37#define SLB_VSID_SHIFT          12
  38#define SLB_VSID_SHIFT_256M     SLB_VSID_SHIFT
  39#define SLB_VSID_SHIFT_1T       24
  40#define SLB_VSID_SSIZE_SHIFT    62
  41#define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  42#define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  43#define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  44#define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  45#define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  46#define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  47#define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  48#define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  49#define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  50#define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  51#define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  52#define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  53#define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  54#define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  55
  56#define SLB_VSID_KERNEL         (SLB_VSID_KP)
  57#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  58
  59#define SLBIE_C                 (0x08000000)
  60#define SLBIE_SSIZE_SHIFT       25
  61
  62/*
  63 * Hash table
  64 */
  65
  66#define HPTES_PER_GROUP 8
  67
  68#define HPTE_V_SSIZE_SHIFT      62
  69#define HPTE_V_AVPN_SHIFT       7
  70#define HPTE_V_COMMON_BITS      ASM_CONST(0x000fffffffffffff)
  71#define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  72#define HPTE_V_AVPN_3_0         ASM_CONST(0x000fffffffffff80)
  73#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  74#define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  75#define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  76#define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  77#define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  78#define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  79#define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  80
  81/*
  82 * ISA 3.0 has a different HPTE format.
  83 */
  84#define HPTE_R_3_0_SSIZE_SHIFT  58
  85#define HPTE_R_3_0_SSIZE_MASK   (3ull << HPTE_R_3_0_SSIZE_SHIFT)
  86#define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
  87#define HPTE_R_TS               ASM_CONST(0x4000000000000000)
  88#define HPTE_R_KEY_HI           ASM_CONST(0x3000000000000000)
  89#define HPTE_R_KEY_BIT0         ASM_CONST(0x2000000000000000)
  90#define HPTE_R_KEY_BIT1         ASM_CONST(0x1000000000000000)
  91#define HPTE_R_RPN_SHIFT        12
  92#define HPTE_R_RPN              ASM_CONST(0x0ffffffffffff000)
  93#define HPTE_R_RPN_3_0          ASM_CONST(0x01fffffffffff000)
  94#define HPTE_R_PP               ASM_CONST(0x0000000000000003)
  95#define HPTE_R_PPP              ASM_CONST(0x8000000000000003)
  96#define HPTE_R_N                ASM_CONST(0x0000000000000004)
  97#define HPTE_R_G                ASM_CONST(0x0000000000000008)
  98#define HPTE_R_M                ASM_CONST(0x0000000000000010)
  99#define HPTE_R_I                ASM_CONST(0x0000000000000020)
 100#define HPTE_R_W                ASM_CONST(0x0000000000000040)
 101#define HPTE_R_WIMG             ASM_CONST(0x0000000000000078)
 102#define HPTE_R_C                ASM_CONST(0x0000000000000080)
 103#define HPTE_R_R                ASM_CONST(0x0000000000000100)
 104#define HPTE_R_KEY_LO           ASM_CONST(0x0000000000000e00)
 105#define HPTE_R_KEY_BIT2         ASM_CONST(0x0000000000000800)
 106#define HPTE_R_KEY_BIT3         ASM_CONST(0x0000000000000400)
 107#define HPTE_R_KEY_BIT4         ASM_CONST(0x0000000000000200)
 108#define HPTE_R_KEY              (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
 109
 110#define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
 111#define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
 112
 113/* Values for PP (assumes Ks=0, Kp=1) */
 114#define PP_RWXX 0       /* Supervisor read/write, User none */
 115#define PP_RWRX 1       /* Supervisor read/write, User read */
 116#define PP_RWRW 2       /* Supervisor read/write, User read/write */
 117#define PP_RXRX 3       /* Supervisor read,       User read */
 118#define PP_RXXX (HPTE_R_PP0 | 2)        /* Supervisor read, user none */
 119
 120/* Fields for tlbiel instruction in architecture 2.06 */
 121#define TLBIEL_INVAL_SEL_MASK   0xc00   /* invalidation selector */
 122#define  TLBIEL_INVAL_PAGE      0x000   /* invalidate a single page */
 123#define  TLBIEL_INVAL_SET_LPID  0x800   /* invalidate a set for current LPID */
 124#define  TLBIEL_INVAL_SET       0xc00   /* invalidate a set for all LPIDs */
 125#define TLBIEL_INVAL_SET_MASK   0xfff000        /* set number to inval. */
 126#define TLBIEL_INVAL_SET_SHIFT  12
 127
 128#define POWER7_TLB_SETS         128     /* # sets in POWER7 TLB */
 129#define POWER8_TLB_SETS         512     /* # sets in POWER8 TLB */
 130#define POWER9_TLB_SETS_HASH    256     /* # sets in POWER9 TLB Hash mode */
 131#define POWER9_TLB_SETS_RADIX   128     /* # sets in POWER9 TLB Radix mode */
 132
 133#ifndef __ASSEMBLY__
 134
 135struct mmu_hash_ops {
 136        void            (*hpte_invalidate)(unsigned long slot,
 137                                           unsigned long vpn,
 138                                           int bpsize, int apsize,
 139                                           int ssize, int local);
 140        long            (*hpte_updatepp)(unsigned long slot,
 141                                         unsigned long newpp,
 142                                         unsigned long vpn,
 143                                         int bpsize, int apsize,
 144                                         int ssize, unsigned long flags);
 145        void            (*hpte_updateboltedpp)(unsigned long newpp,
 146                                               unsigned long ea,
 147                                               int psize, int ssize);
 148        long            (*hpte_insert)(unsigned long hpte_group,
 149                                       unsigned long vpn,
 150                                       unsigned long prpn,
 151                                       unsigned long rflags,
 152                                       unsigned long vflags,
 153                                       int psize, int apsize,
 154                                       int ssize);
 155        long            (*hpte_remove)(unsigned long hpte_group);
 156        int             (*hpte_removebolted)(unsigned long ea,
 157                                             int psize, int ssize);
 158        void            (*flush_hash_range)(unsigned long number, int local);
 159        void            (*hugepage_invalidate)(unsigned long vsid,
 160                                               unsigned long addr,
 161                                               unsigned char *hpte_slot_array,
 162                                               int psize, int ssize, int local);
 163        int             (*resize_hpt)(unsigned long shift);
 164        /*
 165         * Special for kexec.
 166         * To be called in real mode with interrupts disabled. No locks are
 167         * taken as such, concurrent access on pre POWER5 hardware could result
 168         * in a deadlock.
 169         * The linear mapping is destroyed as well.
 170         */
 171        void            (*hpte_clear_all)(void);
 172};
 173extern struct mmu_hash_ops mmu_hash_ops;
 174
 175struct hash_pte {
 176        __be64 v;
 177        __be64 r;
 178};
 179
 180extern struct hash_pte *htab_address;
 181extern unsigned long htab_size_bytes;
 182extern unsigned long htab_hash_mask;
 183
 184
 185static inline int shift_to_mmu_psize(unsigned int shift)
 186{
 187        int psize;
 188
 189        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
 190                if (mmu_psize_defs[psize].shift == shift)
 191                        return psize;
 192        return -1;
 193}
 194
 195static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 196{
 197        if (mmu_psize_defs[mmu_psize].shift)
 198                return mmu_psize_defs[mmu_psize].shift;
 199        BUG();
 200}
 201
 202static inline unsigned int ap_to_shift(unsigned long ap)
 203{
 204        int psize;
 205
 206        for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
 207                if (mmu_psize_defs[psize].ap == ap)
 208                        return mmu_psize_defs[psize].shift;
 209        }
 210
 211        return -1;
 212}
 213
 214static inline unsigned long get_sllp_encoding(int psize)
 215{
 216        unsigned long sllp;
 217
 218        sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) |
 219                ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
 220        return sllp;
 221}
 222
 223#endif /* __ASSEMBLY__ */
 224
 225/*
 226 * Segment sizes.
 227 * These are the values used by hardware in the B field of
 228 * SLB entries and the first dword of MMU hashtable entries.
 229 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 230 */
 231#define MMU_SEGSIZE_256M        0
 232#define MMU_SEGSIZE_1T          1
 233
 234/*
 235 * encode page number shift.
 236 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
 237 * 12 bits. This enable us to address upto 76 bit va.
 238 * For hpt hash from a va we can ignore the page size bits of va and for
 239 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
 240 * we work in all cases including 4k page size.
 241 */
 242#define VPN_SHIFT       12
 243
 244/*
 245 * HPTE Large Page (LP) details
 246 */
 247#define LP_SHIFT        12
 248#define LP_BITS         8
 249#define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
 250
 251#ifndef __ASSEMBLY__
 252
 253static inline int slb_vsid_shift(int ssize)
 254{
 255        if (ssize == MMU_SEGSIZE_256M)
 256                return SLB_VSID_SHIFT;
 257        return SLB_VSID_SHIFT_1T;
 258}
 259
 260static inline int segment_shift(int ssize)
 261{
 262        if (ssize == MMU_SEGSIZE_256M)
 263                return SID_SHIFT;
 264        return SID_SHIFT_1T;
 265}
 266
 267/*
 268 * This array is indexed by the LP field of the HPTE second dword.
 269 * Since this field may contain some RPN bits, some entries are
 270 * replicated so that we get the same value irrespective of RPN.
 271 * The top 4 bits are the page size index (MMU_PAGE_*) for the
 272 * actual page size, the bottom 4 bits are the base page size.
 273 */
 274extern u8 hpte_page_sizes[1 << LP_BITS];
 275
 276static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
 277                                             bool is_base_size)
 278{
 279        unsigned int i, lp;
 280
 281        if (!(h & HPTE_V_LARGE))
 282                return 1ul << 12;
 283
 284        /* Look at the 8 bit LP value */
 285        lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
 286        i = hpte_page_sizes[lp];
 287        if (!i)
 288                return 0;
 289        if (!is_base_size)
 290                i >>= 4;
 291        return 1ul << mmu_psize_defs[i & 0xf].shift;
 292}
 293
 294static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
 295{
 296        return __hpte_page_size(h, l, 0);
 297}
 298
 299static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
 300{
 301        return __hpte_page_size(h, l, 1);
 302}
 303
 304/*
 305 * The current system page and segment sizes
 306 */
 307extern int mmu_kernel_ssize;
 308extern int mmu_highuser_ssize;
 309extern u16 mmu_slb_size;
 310extern unsigned long tce_alloc_start, tce_alloc_end;
 311
 312/*
 313 * If the processor supports 64k normal pages but not 64k cache
 314 * inhibited pages, we have to be prepared to switch processes
 315 * to use 4k pages when they create cache-inhibited mappings.
 316 * If this is the case, mmu_ci_restrictions will be set to 1.
 317 */
 318extern int mmu_ci_restrictions;
 319
 320/*
 321 * This computes the AVPN and B fields of the first dword of a HPTE,
 322 * for use when we want to match an existing PTE.  The bottom 7 bits
 323 * of the returned value are zero.
 324 */
 325static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
 326                                             int ssize)
 327{
 328        unsigned long v;
 329        /*
 330         * The AVA field omits the low-order 23 bits of the 78 bits VA.
 331         * These bits are not needed in the PTE, because the
 332         * low-order b of these bits are part of the byte offset
 333         * into the virtual page and, if b < 23, the high-order
 334         * 23-b of these bits are always used in selecting the
 335         * PTEGs to be searched
 336         */
 337        v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
 338        v <<= HPTE_V_AVPN_SHIFT;
 339        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
 340        return v;
 341}
 342
 343/*
 344 * ISA v3.0 defines a new HPTE format, which differs from the old
 345 * format in having smaller AVPN and ARPN fields, and the B field
 346 * in the second dword instead of the first.
 347 */
 348static inline unsigned long hpte_old_to_new_v(unsigned long v)
 349{
 350        /* trim AVPN, drop B */
 351        return v & HPTE_V_COMMON_BITS;
 352}
 353
 354static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
 355{
 356        /* move B field from 1st to 2nd dword, trim ARPN */
 357        return (r & ~HPTE_R_3_0_SSIZE_MASK) |
 358                (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
 359}
 360
 361static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
 362{
 363        /* insert B field */
 364        return (v & HPTE_V_COMMON_BITS) |
 365                ((r & HPTE_R_3_0_SSIZE_MASK) <<
 366                 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
 367}
 368
 369static inline unsigned long hpte_new_to_old_r(unsigned long r)
 370{
 371        /* clear out B field */
 372        return r & ~HPTE_R_3_0_SSIZE_MASK;
 373}
 374
 375static inline unsigned long hpte_get_old_v(struct hash_pte *hptep)
 376{
 377        unsigned long hpte_v;
 378
 379        hpte_v = be64_to_cpu(hptep->v);
 380        if (cpu_has_feature(CPU_FTR_ARCH_300))
 381                hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
 382        return hpte_v;
 383}
 384
 385/*
 386 * This function sets the AVPN and L fields of the HPTE  appropriately
 387 * using the base page size and actual page size.
 388 */
 389static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
 390                                          int actual_psize, int ssize)
 391{
 392        unsigned long v;
 393        v = hpte_encode_avpn(vpn, base_psize, ssize);
 394        if (actual_psize != MMU_PAGE_4K)
 395                v |= HPTE_V_LARGE;
 396        return v;
 397}
 398
 399/*
 400 * This function sets the ARPN, and LP fields of the HPTE appropriately
 401 * for the page size. We assume the pa is already "clean" that is properly
 402 * aligned for the requested page size
 403 */
 404static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
 405                                          int actual_psize)
 406{
 407        /* A 4K page needs no special encoding */
 408        if (actual_psize == MMU_PAGE_4K)
 409                return pa & HPTE_R_RPN;
 410        else {
 411                unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
 412                unsigned int shift = mmu_psize_defs[actual_psize].shift;
 413                return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
 414        }
 415}
 416
 417/*
 418 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
 419 */
 420static inline unsigned long hpt_vpn(unsigned long ea,
 421                                    unsigned long vsid, int ssize)
 422{
 423        unsigned long mask;
 424        int s_shift = segment_shift(ssize);
 425
 426        mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
 427        return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
 428}
 429
 430/*
 431 * This hashes a virtual address
 432 */
 433static inline unsigned long hpt_hash(unsigned long vpn,
 434                                     unsigned int shift, int ssize)
 435{
 436        unsigned long mask;
 437        unsigned long hash, vsid;
 438
 439        /* VPN_SHIFT can be atmost 12 */
 440        if (ssize == MMU_SEGSIZE_256M) {
 441                mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
 442                hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
 443                        ((vpn & mask) >> (shift - VPN_SHIFT));
 444        } else {
 445                mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
 446                vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
 447                hash = vsid ^ (vsid << 25) ^
 448                        ((vpn & mask) >> (shift - VPN_SHIFT)) ;
 449        }
 450        return hash & 0x7fffffffffUL;
 451}
 452
 453#define HPTE_LOCAL_UPDATE       0x1
 454#define HPTE_NOHPTE_UPDATE      0x2
 455
 456extern int __hash_page_4K(unsigned long ea, unsigned long access,
 457                          unsigned long vsid, pte_t *ptep, unsigned long trap,
 458                          unsigned long flags, int ssize, int subpage_prot);
 459extern int __hash_page_64K(unsigned long ea, unsigned long access,
 460                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 461                           unsigned long flags, int ssize);
 462struct mm_struct;
 463unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
 464extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
 465                        unsigned long access, unsigned long trap,
 466                        unsigned long flags);
 467extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
 468                     unsigned long dsisr);
 469int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 470                     pte_t *ptep, unsigned long trap, unsigned long flags,
 471                     int ssize, unsigned int shift, unsigned int mmu_psize);
 472#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 473extern int __hash_page_thp(unsigned long ea, unsigned long access,
 474                           unsigned long vsid, pmd_t *pmdp, unsigned long trap,
 475                           unsigned long flags, int ssize, unsigned int psize);
 476#else
 477static inline int __hash_page_thp(unsigned long ea, unsigned long access,
 478                                  unsigned long vsid, pmd_t *pmdp,
 479                                  unsigned long trap, unsigned long flags,
 480                                  int ssize, unsigned int psize)
 481{
 482        BUG();
 483        return -1;
 484}
 485#endif
 486extern void hash_failure_debug(unsigned long ea, unsigned long access,
 487                               unsigned long vsid, unsigned long trap,
 488                               int ssize, int psize, int lpsize,
 489                               unsigned long pte);
 490extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 491                             unsigned long pstart, unsigned long prot,
 492                             int psize, int ssize);
 493int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 494                        int psize, int ssize);
 495extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
 496extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 497
 498extern void hash__setup_new_exec(void);
 499
 500#ifdef CONFIG_PPC_PSERIES
 501void hpte_init_pseries(void);
 502#else
 503static inline void hpte_init_pseries(void) { }
 504#endif
 505
 506extern void hpte_init_native(void);
 507
 508struct slb_entry {
 509        u64     esid;
 510        u64     vsid;
 511};
 512
 513extern void slb_initialize(void);
 514void slb_flush_and_restore_bolted(void);
 515void slb_flush_all_realmode(void);
 516void __slb_restore_bolted_realmode(void);
 517void slb_restore_bolted_realmode(void);
 518void slb_save_contents(struct slb_entry *slb_ptr);
 519void slb_dump_contents(struct slb_entry *slb_ptr);
 520
 521extern void slb_vmalloc_update(void);
 522extern void slb_set_size(u16 size);
 523#endif /* __ASSEMBLY__ */
 524
 525/*
 526 * VSID allocation (256MB segment)
 527 *
 528 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
 529 * from mmu context id and effective segment id of the address.
 530 *
 531 * For user processes max context id is limited to MAX_USER_CONTEXT.
 532 * more details in get_user_context
 533 *
 534 * For kernel space get_kernel_context
 535 *
 536 * The proto-VSIDs are then scrambled into real VSIDs with the
 537 * multiplicative hash:
 538 *
 539 *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 540 *
 541 * VSID_MULTIPLIER is prime, so in particular it is
 542 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 543 * Because the modulus is 2^n-1 we can compute it efficiently without
 544 * a divide or extra multiply (see below). The scramble function gives
 545 * robust scattering in the hash table (at least based on some initial
 546 * results).
 547 *
 548 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id
 549 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which
 550 * will produce a VSID of 0.
 551 *
 552 * We also need to avoid the last segment of the last context, because that
 553 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
 554 * because of the modulo operation in vsid scramble.
 555 */
 556
 557/*
 558 * Max Va bits we support as of now is 68 bits. We want 19 bit
 559 * context ID.
 560 * Restrictions:
 561 * GPU has restrictions of not able to access beyond 128TB
 562 * (47 bit effective address). We also cannot do more than 20bit PID.
 563 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS
 564 * to 16 bits (ie, we can only have 2^16 pids at the same time).
 565 */
 566#define VA_BITS                 68
 567#define CONTEXT_BITS            19
 568#define ESID_BITS               (VA_BITS - (SID_SHIFT + CONTEXT_BITS))
 569#define ESID_BITS_1T            (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
 570
 571#define ESID_BITS_MASK          ((1 << ESID_BITS) - 1)
 572#define ESID_BITS_1T_MASK       ((1 << ESID_BITS_1T) - 1)
 573
 574/*
 575 * Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need
 576 * to use more than one context for linear mapping the kernel.
 577 * For vmalloc and memmap, we use just one context with 512TB. With 64 byte
 578 * struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)).
 579 */
 580#if (MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT)
 581#define MAX_KERNEL_CTX_CNT      (1UL << (MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT))
 582#else
 583#define MAX_KERNEL_CTX_CNT      1
 584#endif
 585
 586#define MAX_VMALLOC_CTX_CNT     1
 587#define MAX_IO_CTX_CNT          1
 588#define MAX_VMEMMAP_CTX_CNT     1
 589
 590/*
 591 * 256MB segment
 592 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
 593 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts
 594 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each
 595 * context maps 2^49 bytes (512TB).
 596 *
 597 * We also need to avoid the last segment of the last context, because that
 598 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
 599 * because of the modulo operation in vsid scramble.
 600 *
 601 */
 602#define MAX_USER_CONTEXT        ((ASM_CONST(1) << CONTEXT_BITS) - 2)
 603#define MIN_USER_CONTEXT        (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
 604                                 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT)
 605/*
 606 * For platforms that support on 65bit VA we limit the context bits
 607 */
 608#define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
 609
 610/*
 611 * This should be computed such that protovosid * vsid_mulitplier
 612 * doesn't overflow 64 bits. The vsid_mutliplier should also be
 613 * co-prime to vsid_modulus. We also need to make sure that number
 614 * of bits in multiplied result (dividend) is less than twice the number of
 615 * protovsid bits for our modulus optmization to work.
 616 *
 617 * The below table shows the current values used.
 618 * |-------+------------+----------------------+------------+-------------------|
 619 * |       | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS |
 620 * |-------+------------+----------------------+------------+-------------------|
 621 * | 1T    |         24 |                   25 |         49 |                50 |
 622 * |-------+------------+----------------------+------------+-------------------|
 623 * | 256MB |         24 |                   37 |         61 |                74 |
 624 * |-------+------------+----------------------+------------+-------------------|
 625 *
 626 * |-------+------------+----------------------+------------+--------------------|
 627 * |       | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS |
 628 * |-------+------------+----------------------+------------+--------------------|
 629 * | 1T    |         24 |                   28 |         52 |                 56 |
 630 * |-------+------------+----------------------+------------+--------------------|
 631 * | 256MB |         24 |                   40 |         64 |                 80 |
 632 * |-------+------------+----------------------+------------+--------------------|
 633 *
 634 */
 635#define VSID_MULTIPLIER_256M    ASM_CONST(12538073)     /* 24-bit prime */
 636#define VSID_BITS_256M          (VA_BITS - SID_SHIFT)
 637#define VSID_BITS_65_256M       (65 - SID_SHIFT)
 638/*
 639 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
 640 */
 641#define VSID_MULINV_256M        ASM_CONST(665548017062)
 642
 643#define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
 644#define VSID_BITS_1T            (VA_BITS - SID_SHIFT_1T)
 645#define VSID_BITS_65_1T         (65 - SID_SHIFT_1T)
 646#define VSID_MULINV_1T          ASM_CONST(209034062)
 647
 648/* 1TB VSID reserved for VRMA */
 649#define VRMA_VSID       0x1ffffffUL
 650#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
 651
 652/* 4 bits per slice and we have one slice per 1TB */
 653#define SLICE_ARRAY_SIZE        (H_PGTABLE_RANGE >> 41)
 654#define LOW_SLICE_ARRAY_SZ      (BITS_PER_LONG / BITS_PER_BYTE)
 655#define TASK_SLICE_ARRAY_SZ(x)  ((x)->hash_context->slb_addr_limit >> 41)
 656#ifndef __ASSEMBLY__
 657
 658#ifdef CONFIG_PPC_SUBPAGE_PROT
 659/*
 660 * For the sub-page protection option, we extend the PGD with one of
 661 * these.  Basically we have a 3-level tree, with the top level being
 662 * the protptrs array.  To optimize speed and memory consumption when
 663 * only addresses < 4GB are being protected, pointers to the first
 664 * four pages of sub-page protection words are stored in the low_prot
 665 * array.
 666 * Each page of sub-page protection words protects 1GB (4 bytes
 667 * protects 64k).  For the 3-level tree, each page of pointers then
 668 * protects 8TB.
 669 */
 670struct subpage_prot_table {
 671        unsigned long maxaddr;  /* only addresses < this are protected */
 672        unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
 673        unsigned int *low_prot[4];
 674};
 675
 676#define SBP_L1_BITS             (PAGE_SHIFT - 2)
 677#define SBP_L2_BITS             (PAGE_SHIFT - 3)
 678#define SBP_L1_COUNT            (1 << SBP_L1_BITS)
 679#define SBP_L2_COUNT            (1 << SBP_L2_BITS)
 680#define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
 681#define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
 682
 683extern void subpage_prot_free(struct mm_struct *mm);
 684#else
 685static inline void subpage_prot_free(struct mm_struct *mm) {}
 686#endif /* CONFIG_PPC_SUBPAGE_PROT */
 687
 688/*
 689 * One bit per slice. We have lower slices which cover 256MB segments
 690 * upto 4G range. That gets us 16 low slices. For the rest we track slices
 691 * in 1TB size.
 692 */
 693struct slice_mask {
 694        u64 low_slices;
 695        DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
 696};
 697
 698struct hash_mm_context {
 699        u16 user_psize; /* page size index */
 700
 701        /* SLB page size encodings*/
 702        unsigned char low_slices_psize[LOW_SLICE_ARRAY_SZ];
 703        unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
 704        unsigned long slb_addr_limit;
 705#ifdef CONFIG_PPC_64K_PAGES
 706        struct slice_mask mask_64k;
 707#endif
 708        struct slice_mask mask_4k;
 709#ifdef CONFIG_HUGETLB_PAGE
 710        struct slice_mask mask_16m;
 711        struct slice_mask mask_16g;
 712#endif
 713
 714#ifdef CONFIG_PPC_SUBPAGE_PROT
 715        struct subpage_prot_table *spt;
 716#endif /* CONFIG_PPC_SUBPAGE_PROT */
 717};
 718
 719#if 0
 720/*
 721 * The code below is equivalent to this function for arguments
 722 * < 2^VSID_BITS, which is all this should ever be called
 723 * with.  However gcc is not clever enough to compute the
 724 * modulus (2^n-1) without a second multiply.
 725 */
 726#define vsid_scramble(protovsid, size) \
 727        ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
 728
 729/* simplified form avoiding mod operation */
 730#define vsid_scramble(protovsid, size) \
 731        ({                                                               \
 732                unsigned long x;                                         \
 733                x = (protovsid) * VSID_MULTIPLIER_##size;                \
 734                x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
 735                (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
 736        })
 737
 738#else /* 1 */
 739static inline unsigned long vsid_scramble(unsigned long protovsid,
 740                                  unsigned long vsid_multiplier, int vsid_bits)
 741{
 742        unsigned long vsid;
 743        unsigned long vsid_modulus = ((1UL << vsid_bits) - 1);
 744        /*
 745         * We have same multipler for both 256 and 1T segements now
 746         */
 747        vsid = protovsid * vsid_multiplier;
 748        vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus);
 749        return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
 750}
 751
 752#endif /* 1 */
 753
 754/* Returns the segment size indicator for a user address */
 755static inline int user_segment_size(unsigned long addr)
 756{
 757        /* Use 1T segments if possible for addresses >= 1T */
 758        if (addr >= (1UL << SID_SHIFT_1T))
 759                return mmu_highuser_ssize;
 760        return MMU_SEGSIZE_256M;
 761}
 762
 763static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
 764                                     int ssize)
 765{
 766        unsigned long va_bits = VA_BITS;
 767        unsigned long vsid_bits;
 768        unsigned long protovsid;
 769
 770        /*
 771         * Bad address. We return VSID 0 for that
 772         */
 773        if ((ea & EA_MASK)  >= H_PGTABLE_RANGE)
 774                return 0;
 775
 776        if (!mmu_has_feature(MMU_FTR_68_BIT_VA))
 777                va_bits = 65;
 778
 779        if (ssize == MMU_SEGSIZE_256M) {
 780                vsid_bits = va_bits - SID_SHIFT;
 781                protovsid = (context << ESID_BITS) |
 782                        ((ea >> SID_SHIFT) & ESID_BITS_MASK);
 783                return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits);
 784        }
 785        /* 1T segment */
 786        vsid_bits = va_bits - SID_SHIFT_1T;
 787        protovsid = (context << ESID_BITS_1T) |
 788                ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK);
 789        return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits);
 790}
 791
 792/*
 793 * For kernel space, we use context ids as below
 794 * below. Range is 512TB per context.
 795 *
 796 * 0x00001 -  [ 0xc000000000000000 - 0xc001ffffffffffff]
 797 * 0x00002 -  [ 0xc002000000000000 - 0xc003ffffffffffff]
 798 * 0x00003 -  [ 0xc004000000000000 - 0xc005ffffffffffff]
 799 * 0x00004 -  [ 0xc006000000000000 - 0xc007ffffffffffff]
 800 *
 801 * vmap, IO, vmemap
 802 *
 803 * 0x00005 -  [ 0xc008000000000000 - 0xc009ffffffffffff]
 804 * 0x00006 -  [ 0xc00a000000000000 - 0xc00bffffffffffff]
 805 * 0x00007 -  [ 0xc00c000000000000 - 0xc00dffffffffffff]
 806 *
 807 */
 808static inline unsigned long get_kernel_context(unsigned long ea)
 809{
 810        unsigned long region_id = get_region_id(ea);
 811        unsigned long ctx;
 812        /*
 813         * Depending on Kernel config, kernel region can have one context
 814         * or more.
 815         */
 816        if (region_id == LINEAR_MAP_REGION_ID) {
 817                /*
 818                 * We already verified ea to be not beyond the addr limit.
 819                 */
 820                ctx =  1 + ((ea & EA_MASK) >> MAX_EA_BITS_PER_CONTEXT);
 821        } else
 822                ctx = region_id + MAX_KERNEL_CTX_CNT - 1;
 823        return ctx;
 824}
 825
 826/*
 827 * This is only valid for addresses >= PAGE_OFFSET
 828 */
 829static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 830{
 831        unsigned long context;
 832
 833        if (!is_kernel_addr(ea))
 834                return 0;
 835
 836        context = get_kernel_context(ea);
 837        return get_vsid(context, ea, ssize);
 838}
 839
 840unsigned htab_shift_for_mem_size(unsigned long mem_size);
 841
 842#endif /* __ASSEMBLY__ */
 843
 844#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
 845