LXR linux/arch/powerpc/include/asm/eeh.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   4 * Copyright 2001-2012 IBM Corporation.
   5 */
   6
   7#ifndef _POWERPC_EEH_H
   8#define _POWERPC_EEH_H
   9#ifdef __KERNEL__
  10
  11#include <linux/init.h>
  12#include <linux/list.h>
  13#include <linux/string.h>
  14#include <linux/time.h>
  15#include <linux/atomic.h>
  16
  17#include <uapi/asm/eeh.h>
  18
  19struct pci_dev;
  20struct pci_bus;
  21struct pci_dn;
  22
  23#ifdef CONFIG_EEH
  24
  25/* EEH subsystem flags */
  26#define EEH_ENABLED             0x01    /* EEH enabled                       */
  27#define EEH_FORCE_DISABLED      0x02    /* EEH disabled                      */
  28#define EEH_PROBE_MODE_DEV      0x04    /* From PCI device                   */
  29#define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree                  */
  30#define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid                     */
  31#define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log                 */
  32#define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately              */
  33
  34/*
  35 * Delay for PE reset, all in ms
  36 *
  37 * PCI specification has reset hold time of 100 milliseconds.
  38 * We have 250 milliseconds here. The PCI bus settlement time
  39 * is specified as 1.5 seconds and we have 1.8 seconds.
  40 */
  41#define EEH_PE_RST_HOLD_TIME            250
  42#define EEH_PE_RST_SETTLE_TIME          1800
  43
  44/*
  45 * The struct is used to trace PE related EEH functionality.
  46 * In theory, there will have one instance of the struct to
  47 * be created against particular PE. In nature, PEs correlate
  48 * to each other. the struct has to reflect that hierarchy in
  49 * order to easily pick up those affected PEs when one particular
  50 * PE has EEH errors.
  51 *
  52 * Also, one particular PE might be composed of PCI device, PCI
  53 * bus and its subordinate components. The struct also need ship
  54 * the information. Further more, one particular PE is only meaingful
  55 * in the corresponding PHB. Therefore, the root PEs should be created
  56 * against existing PHBs in on-to-one fashion.
  57 */
  58#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  59#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  60#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  61#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  62#define EEH_PE_VF       (1 << 4)        /* VF PE     */
  63
  64#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  65#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  66#define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
  67#define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
  68
  69#define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  70#define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
  71#define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
  72#define EEH_PE_PRI_BUS          (1 << 11)       /* Cached primary bus   */
  73
  74struct eeh_pe {
  75        int type;                       /* PE type: PHB/Bus/Device      */
  76        int state;                      /* PE EEH dependent mode        */
  77        int config_addr;                /* Traditional PCI address      */
  78        int addr;                       /* PE configuration address     */
  79        struct pci_controller *phb;     /* Associated PHB               */
  80        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  81        int check_count;                /* Times of ignored error       */
  82        int freeze_count;               /* Times of froze up            */
  83        time64_t tstamp;                /* Time on first-time freeze    */
  84        int false_positives;            /* Times of reported #ff's      */
  85        atomic_t pass_dev_cnt;          /* Count of passed through devs */
  86        struct eeh_pe *parent;          /* Parent PE                    */
  87        void *data;                     /* PE auxillary data            */
  88        struct list_head child_list;    /* List of PEs below this PE    */
  89        struct list_head child;         /* Memb. child_list/eeh_phb_pe  */
  90        struct list_head edevs;         /* List of eeh_dev in this PE   */
  91};
  92
  93#define eeh_pe_for_each_dev(pe, edev, tmp) \
  94                list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
  95
  96#define eeh_for_each_pe(root, pe) \
  97        for (pe = root; pe; pe = eeh_pe_next(pe, root))
  98
  99static inline bool eeh_pe_passed(struct eeh_pe *pe)
 100{
 101        return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 102}
 103
 104/*
 105 * The struct is used to trace EEH state for the associated
 106 * PCI device node or PCI device. In future, it might
 107 * represent PE as well so that the EEH device to form
 108 * another tree except the currently existing tree of PCI
 109 * buses and PCI devices
 110 */
 111#define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 112#define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 113#define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 114#define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 115#define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 116
 117#define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 118#define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 119#define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 120
 121struct eeh_dev {
 122        int mode;                       /* EEH mode                     */
 123        int class_code;                 /* Class code of the device     */
 124        int pe_config_addr;             /* PE config address            */
 125        u32 config_space[16];           /* Saved PCI config space       */
 126        int pcix_cap;                   /* Saved PCIx capability        */
 127        int pcie_cap;                   /* Saved PCIe capability        */
 128        int aer_cap;                    /* Saved AER capability         */
 129        int af_cap;                     /* Saved AF capability          */
 130        struct eeh_pe *pe;              /* Associated PE                */
 131        struct list_head entry;         /* Membership in eeh_pe.edevs   */
 132        struct list_head rmv_entry;     /* Membership in rmv_list       */
 133        struct pci_dn *pdn;             /* Associated PCI device node   */
 134        struct pci_dev *pdev;           /* Associated PCI device        */
 135        bool in_error;                  /* Error flag for edev          */
 136        struct pci_dev *physfn;         /* Associated SRIOV PF          */
 137};
 138
 139static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
 140{
 141        return edev ? edev->pdn : NULL;
 142}
 143
 144static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 145{
 146        return edev ? edev->pdev : NULL;
 147}
 148
 149static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
 150{
 151        return edev ? edev->pe : NULL;
 152}
 153
 154/* Return values from eeh_ops::next_error */
 155enum {
 156        EEH_NEXT_ERR_NONE = 0,
 157        EEH_NEXT_ERR_INF,
 158        EEH_NEXT_ERR_FROZEN_PE,
 159        EEH_NEXT_ERR_FENCED_PHB,
 160        EEH_NEXT_ERR_DEAD_PHB,
 161        EEH_NEXT_ERR_DEAD_IOC
 162};
 163
 164/*
 165 * The struct is used to trace the registered EEH operation
 166 * callback functions. Actually, those operation callback
 167 * functions are heavily platform dependent. That means the
 168 * platform should register its own EEH operation callback
 169 * functions before any EEH further operations.
 170 */
 171#define EEH_OPT_DISABLE         0       /* EEH disable  */
 172#define EEH_OPT_ENABLE          1       /* EEH enable   */
 173#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 174#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 175#define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
 176#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 177#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 178#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 179#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 180#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 181#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 182#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 183#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 184#define EEH_RESET_HOT           1       /* Hot reset                    */
 185#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 186#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 187#define EEH_LOG_PERM            2       /* EEH permanent error log      */
 188
 189struct eeh_ops {
 190        char *name;
 191        int (*init)(void);
 192        void* (*probe)(struct pci_dn *pdn, void *data);
 193        int (*set_option)(struct eeh_pe *pe, int option);
 194        int (*get_pe_addr)(struct eeh_pe *pe);
 195        int (*get_state)(struct eeh_pe *pe, int *delay);
 196        int (*reset)(struct eeh_pe *pe, int option);
 197        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 198        int (*configure_bridge)(struct eeh_pe *pe);
 199        int (*err_inject)(struct eeh_pe *pe, int type, int func,
 200                          unsigned long addr, unsigned long mask);
 201        int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
 202        int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
 203        int (*next_error)(struct eeh_pe **pe);
 204        int (*restore_config)(struct pci_dn *pdn);
 205        int (*notify_resume)(struct pci_dn *pdn);
 206};
 207
 208extern int eeh_subsystem_flags;
 209extern u32 eeh_max_freezes;
 210extern bool eeh_debugfs_no_recover;
 211extern struct eeh_ops *eeh_ops;
 212extern raw_spinlock_t confirm_error_lock;
 213
 214static inline void eeh_add_flag(int flag)
 215{
 216        eeh_subsystem_flags |= flag;
 217}
 218
 219static inline void eeh_clear_flag(int flag)
 220{
 221        eeh_subsystem_flags &= ~flag;
 222}
 223
 224static inline bool eeh_has_flag(int flag)
 225{
 226        return !!(eeh_subsystem_flags & flag);
 227}
 228
 229static inline bool eeh_enabled(void)
 230{
 231        return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
 232}
 233
 234static inline void eeh_serialize_lock(unsigned long *flags)
 235{
 236        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 237}
 238
 239static inline void eeh_serialize_unlock(unsigned long flags)
 240{
 241        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 242}
 243
 244static inline bool eeh_state_active(int state)
 245{
 246        return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
 247        == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
 248}
 249
 250typedef void *(*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
 251typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
 252void eeh_set_pe_aux_size(int size);
 253int eeh_phb_pe_create(struct pci_controller *phb);
 254int eeh_wait_state(struct eeh_pe *pe, int max_wait);
 255struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 256struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
 257struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
 258                          int pe_no, int config_addr);
 259int eeh_add_to_parent_pe(struct eeh_dev *edev);
 260int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 261void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 262void *eeh_pe_traverse(struct eeh_pe *root,
 263                      eeh_pe_traverse_func fn, void *flag);
 264void *eeh_pe_dev_traverse(struct eeh_pe *root,
 265                          eeh_edev_traverse_func fn, void *flag);
 266void eeh_pe_restore_bars(struct eeh_pe *pe);
 267const char *eeh_pe_loc_get(struct eeh_pe *pe);
 268struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 269
 270struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
 271void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 272void eeh_probe_devices(void);
 273int __init eeh_ops_register(struct eeh_ops *ops);
 274int __exit eeh_ops_unregister(const char *name);
 275int eeh_check_failure(const volatile void __iomem *token);
 276int eeh_dev_check_failure(struct eeh_dev *edev);
 277void eeh_addr_cache_build(void);
 278void eeh_add_device_early(struct pci_dn *);
 279void eeh_add_device_tree_early(struct pci_dn *);
 280void eeh_add_device_late(struct pci_dev *);
 281void eeh_add_device_tree_late(struct pci_bus *);
 282void eeh_add_sysfs_files(struct pci_bus *);
 283void eeh_remove_device(struct pci_dev *);
 284int eeh_unfreeze_pe(struct eeh_pe *pe);
 285int eeh_pe_reset_and_recover(struct eeh_pe *pe);
 286int eeh_dev_open(struct pci_dev *pdev);
 287void eeh_dev_release(struct pci_dev *pdev);
 288struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 289int eeh_pe_set_option(struct eeh_pe *pe, int option);
 290int eeh_pe_get_state(struct eeh_pe *pe);
 291int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
 292int eeh_pe_configure(struct eeh_pe *pe);
 293int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
 294                      unsigned long addr, unsigned long mask);
 295int eeh_restore_vf_config(struct pci_dn *pdn);
 296
 297/**
 298 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 299 *
 300 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 301 * which does further tests out of line.
 302 */
 303#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 304
 305/*
 306 * Reads from a device which has been isolated by EEH will return
 307 * all 1s.  This macro gives an all-1s value of the given size (in
 308 * bytes: 1, 2, or 4) for comparing with the result of a read.
 309 */
 310#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 311
 312#else /* !CONFIG_EEH */
 313
 314static inline bool eeh_enabled(void)
 315{
 316        return false;
 317}
 318
 319static inline void eeh_probe_devices(void) { }
 320
 321static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
 322{
 323        return NULL;
 324}
 325
 326static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 327
 328static inline int eeh_check_failure(const volatile void __iomem *token)
 329{
 330        return 0;
 331}
 332
 333#define eeh_dev_check_failure(x) (0)
 334
 335static inline void eeh_addr_cache_build(void) { }
 336
 337static inline void eeh_add_device_early(struct pci_dn *pdn) { }
 338
 339static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
 340
 341static inline void eeh_add_device_late(struct pci_dev *dev) { }
 342
 343static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 344
 345static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 346
 347static inline void eeh_remove_device(struct pci_dev *dev) { }
 348
 349#define EEH_POSSIBLE_ERROR(val, type) (0)
 350#define EEH_IO_ERROR_VALUE(size) (-1UL)
 351#endif /* CONFIG_EEH */
 352
 353#ifdef CONFIG_PPC64
 354/*
 355 * MMIO read/write operations with EEH support.
 356 */
 357static inline u8 eeh_readb(const volatile void __iomem *addr)
 358{
 359        u8 val = in_8(addr);
 360        if (EEH_POSSIBLE_ERROR(val, u8))
 361                eeh_check_failure(addr);
 362        return val;
 363}
 364
 365static inline u16 eeh_readw(const volatile void __iomem *addr)
 366{
 367        u16 val = in_le16(addr);
 368        if (EEH_POSSIBLE_ERROR(val, u16))
 369                eeh_check_failure(addr);
 370        return val;
 371}
 372
 373static inline u32 eeh_readl(const volatile void __iomem *addr)
 374{
 375        u32 val = in_le32(addr);
 376        if (EEH_POSSIBLE_ERROR(val, u32))
 377                eeh_check_failure(addr);
 378        return val;
 379}
 380
 381static inline u64 eeh_readq(const volatile void __iomem *addr)
 382{
 383        u64 val = in_le64(addr);
 384        if (EEH_POSSIBLE_ERROR(val, u64))
 385                eeh_check_failure(addr);
 386        return val;
 387}
 388
 389static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 390{
 391        u16 val = in_be16(addr);
 392        if (EEH_POSSIBLE_ERROR(val, u16))
 393                eeh_check_failure(addr);
 394        return val;
 395}
 396
 397static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 398{
 399        u32 val = in_be32(addr);
 400        if (EEH_POSSIBLE_ERROR(val, u32))
 401                eeh_check_failure(addr);
 402        return val;
 403}
 404
 405static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 406{
 407        u64 val = in_be64(addr);
 408        if (EEH_POSSIBLE_ERROR(val, u64))
 409                eeh_check_failure(addr);
 410        return val;
 411}
 412
 413static inline void eeh_memcpy_fromio(void *dest, const
 414                                     volatile void __iomem *src,
 415                                     unsigned long n)
 416{
 417        _memcpy_fromio(dest, src, n);
 418
 419        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 420         * were copied. Check all four bytes.
 421         */
 422        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 423                eeh_check_failure(src);
 424}
 425
 426/* in-string eeh macros */
 427static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 428                              int ns)
 429{
 430        _insb(addr, buf, ns);
 431        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 432                eeh_check_failure(addr);
 433}
 434
 435static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 436                              int ns)
 437{
 438        _insw(addr, buf, ns);
 439        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 440                eeh_check_failure(addr);
 441}
 442
 443static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 444                              int nl)
 445{
 446        _insl(addr, buf, nl);
 447        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 448                eeh_check_failure(addr);
 449}
 450
 451
 452void eeh_cache_debugfs_init(void);
 453
 454#endif /* CONFIG_PPC64 */
 455#endif /* __KERNEL__ */
 456#endif /* _POWERPC_EEH_H */
 457