1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_MMU_BOOK3E_H_ 3#define _ASM_POWERPC_MMU_BOOK3E_H_ 4/* 5 * Freescale Book-E/Book-3e (ISA 2.06+) MMU support 6 */ 7 8/* Book-3e defined page sizes */ 9#define BOOK3E_PAGESZ_1K 0 10#define BOOK3E_PAGESZ_2K 1 11#define BOOK3E_PAGESZ_4K 2 12#define BOOK3E_PAGESZ_8K 3 13#define BOOK3E_PAGESZ_16K 4 14#define BOOK3E_PAGESZ_32K 5 15#define BOOK3E_PAGESZ_64K 6 16#define BOOK3E_PAGESZ_128K 7 17#define BOOK3E_PAGESZ_256K 8 18#define BOOK3E_PAGESZ_512K 9 19#define BOOK3E_PAGESZ_1M 10 20#define BOOK3E_PAGESZ_2M 11 21#define BOOK3E_PAGESZ_4M 12 22#define BOOK3E_PAGESZ_8M 13 23#define BOOK3E_PAGESZ_16M 14 24#define BOOK3E_PAGESZ_32M 15 25#define BOOK3E_PAGESZ_64M 16 26#define BOOK3E_PAGESZ_128M 17 27#define BOOK3E_PAGESZ_256M 18 28#define BOOK3E_PAGESZ_512M 19 29#define BOOK3E_PAGESZ_1GB 20 30#define BOOK3E_PAGESZ_2GB 21 31#define BOOK3E_PAGESZ_4GB 22 32#define BOOK3E_PAGESZ_8GB 23 33#define BOOK3E_PAGESZ_16GB 24 34#define BOOK3E_PAGESZ_32GB 25 35#define BOOK3E_PAGESZ_64GB 26 36#define BOOK3E_PAGESZ_128GB 27 37#define BOOK3E_PAGESZ_256GB 28 38#define BOOK3E_PAGESZ_512GB 29 39#define BOOK3E_PAGESZ_1TB 30 40#define BOOK3E_PAGESZ_2TB 31 41 42/* MAS registers bit definitions */ 43 44#define MAS0_TLBSEL_MASK 0x30000000 45#define MAS0_TLBSEL_SHIFT 28 46#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) 47#define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> \ 48 MAS0_TLBSEL_SHIFT) 49#define MAS0_ESEL_MASK 0x0FFF0000 50#define MAS0_ESEL_SHIFT 16 51#define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) 52#define MAS0_NV(x) ((x) & 0x00000FFF) 53#define MAS0_HES 0x00004000 54#define MAS0_WQ_ALLWAYS 0x00000000 55#define MAS0_WQ_COND 0x00001000 56#define MAS0_WQ_CLR_RSRV 0x00002000 57 58#define MAS1_VALID 0x80000000 59#define MAS1_IPROT 0x40000000 60#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) 61#define MAS1_IND 0x00002000 62#define MAS1_TS 0x00001000 63#define MAS1_TSIZE_MASK 0x00000f80 64#define MAS1_TSIZE_SHIFT 7 65#define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) 66#define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT) 67 68#define MAS2_EPN (~0xFFFUL) 69#define MAS2_X0 0x00000040 70#define MAS2_X1 0x00000020 71#define MAS2_W 0x00000010 72#define MAS2_I 0x00000008 73#define MAS2_M 0x00000004 74#define MAS2_G 0x00000002 75#define MAS2_E 0x00000001 76#define MAS2_WIMGE_MASK 0x0000001f 77#define MAS2_EPN_MASK(size) (~0 << (size + 10)) 78#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) 79 80#define MAS3_RPN 0xFFFFF000 81#define MAS3_U0 0x00000200 82#define MAS3_U1 0x00000100 83#define MAS3_U2 0x00000080 84#define MAS3_U3 0x00000040 85#define MAS3_UX 0x00000020 86#define MAS3_SX 0x00000010 87#define MAS3_UW 0x00000008 88#define MAS3_SW 0x00000004 89#define MAS3_UR 0x00000002 90#define MAS3_SR 0x00000001 91#define MAS3_BAP_MASK 0x0000003f 92#define MAS3_SPSIZE 0x0000003e 93#define MAS3_SPSIZE_SHIFT 1 94 95#define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK 96#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 97#define MAS4_INDD 0x00008000 /* Default IND */ 98#define MAS4_TSIZED(x) MAS1_TSIZE(x) 99#define MAS4_X0D 0x00000040 100#define MAS4_X1D 0x00000020 101#define MAS4_WD 0x00000010 102#define MAS4_ID 0x00000008 103#define MAS4_MD 0x00000004 104#define MAS4_GD 0x00000002 105#define MAS4_ED 0x00000001 106#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 107#define MAS4_WIMGED_SHIFT 0 108#define MAS4_VLED MAS4_X1D /* Default VLE */ 109#define MAS4_ACMD 0x000000c0 /* Default ACM */ 110#define MAS4_ACMD_SHIFT 6 111#define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */ 112#define MAS4_TSIZED_SHIFT 7 113 114#define MAS5_SGS 0x80000000 115 116#define MAS6_SPID0 0x3FFF0000 117#define MAS6_SPID1 0x00007FFE 118#define MAS6_ISIZE(x) MAS1_TSIZE(x) 119#define MAS6_SAS 0x00000001 120#define MAS6_SPID MAS6_SPID0 121#define MAS6_SIND 0x00000002 /* Indirect page */ 122#define MAS6_SIND_SHIFT 1 123#define MAS6_SPID_MASK 0x3fff0000 124#define MAS6_SPID_SHIFT 16 125#define MAS6_ISIZE_MASK 0x00000f80 126#define MAS6_ISIZE_SHIFT 7 127 128#define MAS7_RPN 0xFFFFFFFF 129 130#define MAS8_TGS 0x80000000 /* Guest space */ 131#define MAS8_VF 0x40000000 /* Virtualization Fault */ 132#define MAS8_TLPID 0x000000ff 133 134/* Bit definitions for MMUCFG */ 135#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 136#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 137#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 138#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 139#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 140#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 141#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 142#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 143#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 144 145/* Bit definitions for MMUCSR0 */ 146#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 147#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 148#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 149#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 150#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 151 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 152#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 153#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 154#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 155#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 156 157/* MMUCFG bits */ 158#define MMUCFG_MAVN_NASK 0x00000003 159#define MMUCFG_MAVN_V1_0 0x00000000 160#define MMUCFG_MAVN_V2_0 0x00000001 161#define MMUCFG_NTLB_MASK 0x0000000c 162#define MMUCFG_NTLB_SHIFT 2 163#define MMUCFG_PIDSIZE_MASK 0x000007c0 164#define MMUCFG_PIDSIZE_SHIFT 6 165#define MMUCFG_TWC 0x00008000 166#define MMUCFG_LRAT 0x00010000 167#define MMUCFG_RASIZE_MASK 0x00fe0000 168#define MMUCFG_RASIZE_SHIFT 17 169#define MMUCFG_LPIDSIZE_MASK 0x0f000000 170#define MMUCFG_LPIDSIZE_SHIFT 24 171 172/* TLBnCFG encoding */ 173#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 174#define TLBnCFG_HES 0x00002000 /* HW select supported */ 175#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 176#define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 177#define TLBnCFG_IND 0x00020000 /* IND entries supported */ 178#define TLBnCFG_PT 0x00040000 /* Can load from page table */ 179#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 180#define TLBnCFG_MINSIZE_SHIFT 20 181#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 182#define TLBnCFG_MAXSIZE_SHIFT 16 183#define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 184#define TLBnCFG_ASSOC_SHIFT 24 185 186/* TLBnPS encoding */ 187#define TLBnPS_4K 0x00000004 188#define TLBnPS_8K 0x00000008 189#define TLBnPS_16K 0x00000010 190#define TLBnPS_32K 0x00000020 191#define TLBnPS_64K 0x00000040 192#define TLBnPS_128K 0x00000080 193#define TLBnPS_256K 0x00000100 194#define TLBnPS_512K 0x00000200 195#define TLBnPS_1M 0x00000400 196#define TLBnPS_2M 0x00000800 197#define TLBnPS_4M 0x00001000 198#define TLBnPS_8M 0x00002000 199#define TLBnPS_16M 0x00004000 200#define TLBnPS_32M 0x00008000 201#define TLBnPS_64M 0x00010000 202#define TLBnPS_128M 0x00020000 203#define TLBnPS_256M 0x00040000 204#define TLBnPS_512M 0x00080000 205#define TLBnPS_1G 0x00100000 206#define TLBnPS_2G 0x00200000 207#define TLBnPS_4G 0x00400000 208#define TLBnPS_8G 0x00800000 209#define TLBnPS_16G 0x01000000 210#define TLBnPS_32G 0x02000000 211#define TLBnPS_64G 0x04000000 212#define TLBnPS_128G 0x08000000 213#define TLBnPS_256G 0x10000000 214 215/* tlbilx action encoding */ 216#define TLBILX_T_ALL 0 217#define TLBILX_T_TID 1 218#define TLBILX_T_FULLMATCH 3 219#define TLBILX_T_CLASS0 4 220#define TLBILX_T_CLASS1 5 221#define TLBILX_T_CLASS2 6 222#define TLBILX_T_CLASS3 7 223 224#ifndef __ASSEMBLY__ 225#include <asm/bug.h> 226 227extern unsigned int tlbcam_index; 228 229typedef struct { 230 unsigned int id; 231 unsigned int active; 232 unsigned long vdso_base; 233} mm_context_t; 234 235/* Page size definitions, common between 32 and 64-bit 236 * 237 * shift : is the "PAGE_SHIFT" value for that page size 238 * penc : is the pte encoding mask 239 * 240 */ 241struct mmu_psize_def 242{ 243 unsigned int shift; /* number of bits */ 244 unsigned int enc; /* PTE encoding */ 245 unsigned int ind; /* Corresponding indirect page size shift */ 246 unsigned int flags; 247#define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ 248#define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ 249}; 250extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 251 252static inline int shift_to_mmu_psize(unsigned int shift) 253{ 254 int psize; 255 256 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) 257 if (mmu_psize_defs[psize].shift == shift) 258 return psize; 259 return -1; 260} 261 262static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 263{ 264 if (mmu_psize_defs[mmu_psize].shift) 265 return mmu_psize_defs[mmu_psize].shift; 266 BUG(); 267} 268 269/* The page sizes use the same names as 64-bit hash but are 270 * constants 271 */ 272#if defined(CONFIG_PPC_4K_PAGES) 273#define mmu_virtual_psize MMU_PAGE_4K 274#else 275#error Unsupported page size 276#endif 277 278extern int mmu_linear_psize; 279extern int mmu_vmemmap_psize; 280 281struct tlb_core_data { 282 /* 283 * Per-core spinlock for e6500 TLB handlers (no tlbsrx.) 284 * Must be the first struct element. 285 */ 286 u8 lock; 287 288 /* For software way selection, as on Freescale TLB1 */ 289 u8 esel_next, esel_max, esel_first; 290}; 291 292#ifdef CONFIG_PPC64 293extern unsigned long linear_map_top; 294extern int book3e_htw_mode; 295 296#define PPC_HTW_NONE 0 297#define PPC_HTW_IBM 1 298#define PPC_HTW_E6500 2 299 300/* 301 * 64-bit booke platforms don't load the tlb in the tlb miss handler code. 302 * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to 303 * return 1, indicating that the tlb requires preloading. 304 */ 305#define HUGETLB_NEED_PRELOAD 306 307#define mmu_cleanup_all NULL 308 309#define MAX_PHYSMEM_BITS 44 310 311#endif 312 313#endif /* !__ASSEMBLY__ */ 314 315#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ 316