LXR linux/arch/powerpc/include/asm/ppc

   1/*
   2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3 */
   4#ifndef _ASM_POWERPC_PPC_ASM_H
   5#define _ASM_POWERPC_PPC_ASM_H
   6
   7#include <linux/stringify.h>
   8#include <asm/asm-compat.h>
   9#include <asm/processor.h>
  10#include <asm/ppc-opcode.h>
  11#include <asm/firmware.h>
  12#include <asm/feature-fixups.h>
  13
  14#ifdef __ASSEMBLY__
  15
  16#define SZL                     (BITS_PER_LONG/8)
  17
  18/*
  19 * Stuff for accurate CPU time accounting.
  20 * These macros handle transitions between user and system state
  21 * in exception entry and exit and accumulate time to the
  22 * user_time and system_time fields in the paca.
  23 */
  24
  25#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  26#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
  27#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
  28#define ACCOUNT_STOLEN_TIME
  29#else
  30#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)                             \
  31        MFTB(ra);                       /* get timebase */              \
  32        PPC_LL  rb, ACCOUNT_STARTTIME_USER(ptr);                        \
  33        PPC_STL ra, ACCOUNT_STARTTIME(ptr);                             \
  34        subf    rb,rb,ra;               /* subtract start value */      \
  35        PPC_LL  ra, ACCOUNT_USER_TIME(ptr);                             \
  36        add     ra,ra,rb;               /* add on to user time */       \
  37        PPC_STL ra, ACCOUNT_USER_TIME(ptr);                             \
  38
  39#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)                              \
  40        MFTB(ra);                       /* get timebase */              \
  41        PPC_LL  rb, ACCOUNT_STARTTIME(ptr);                             \
  42        PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr);                        \
  43        subf    rb,rb,ra;               /* subtract start value */      \
  44        PPC_LL  ra, ACCOUNT_SYSTEM_TIME(ptr);                           \
  45        add     ra,ra,rb;               /* add on to system time */     \
  46        PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
  47
  48#ifdef CONFIG_PPC_SPLPAR
  49#define ACCOUNT_STOLEN_TIME                                             \
  50BEGIN_FW_FTR_SECTION;                                                   \
  51        beq     33f;                                                    \
  52        /* from user - see if there are any DTL entries to process */   \
  53        ld      r10,PACALPPACAPTR(r13); /* get ptr to VPA */            \
  54        ld      r11,PACA_DTL_RIDX(r13); /* get log read index */        \
  55        addi    r10,r10,LPPACA_DTLIDX;                                  \
  56        LDX_BE  r10,0,r10;              /* get log write index */       \
  57        cmpd    cr1,r11,r10;                                            \
  58        beq+    cr1,33f;                                                \
  59        bl      accumulate_stolen_time;                         \
  60        ld      r12,_MSR(r1);                                           \
  61        andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
  6233:                                                                     \
  63END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
  64
  65#else  /* CONFIG_PPC_SPLPAR */
  66#define ACCOUNT_STOLEN_TIME
  67
  68#endif /* CONFIG_PPC_SPLPAR */
  69
  70#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
  71
  72/*
  73 * Macros for storing registers into and loading registers from
  74 * exception frames.
  75 */
  76#ifdef __powerpc64__
  77#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  78#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  79#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  80#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  81#else
  82#define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  83#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  84#define SAVE_NVGPRS(base)       stmw    13, GPR0+4*13(base)
  85#define REST_NVGPRS(base)       lmw     13, GPR0+4*13(base)
  86#endif
  87
  88#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  89#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  90#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  91#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  92#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  93#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  94#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  95#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  96
  97#define SAVE_FPR(n, base)       stfd    n,8*TS_FPRWIDTH*(n)(base)
  98#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  99#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
 100#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
 101#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
 102#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
 103#define REST_FPR(n, base)       lfd     n,8*TS_FPRWIDTH*(n)(base)
 104#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
 105#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
 106#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
 107#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
 108#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 109
 110#define SAVE_VR(n,b,base)       li b,16*(n);  stvx n,base,b
 111#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 112#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 113#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 114#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 115#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 116#define REST_VR(n,b,base)       li b,16*(n); lvx n,base,b
 117#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
 118#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 119#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
 120#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
 121#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 122
 123#ifdef __BIG_ENDIAN__
 124#define STXVD2X_ROT(n,b,base)           STXVD2X(n,b,base)
 125#define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base)
 126#else
 127#define STXVD2X_ROT(n,b,base)           XXSWAPD(n,n);           \
 128                                        STXVD2X(n,b,base);      \
 129                                        XXSWAPD(n,n)
 130
 131#define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base);       \
 132                                        XXSWAPD(n,n)
 133#endif
 134/* Save the lower 32 VSRs in the thread VSR region */
 135#define SAVE_VSR(n,b,base)      li b,16*(n);  STXVD2X_ROT(n,R##base,R##b)
 136#define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 137#define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 138#define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 139#define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 140#define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
 141#define REST_VSR(n,b,base)      li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
 142#define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 143#define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 144#define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 145#define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 146#define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 147
 148/*
 149 * b = base register for addressing, o = base offset from register of 1st EVR
 150 * n = first EVR, s = scratch
 151 */
 152#define SAVE_EVR(n,s,b,o)       evmergehi s,s,n; stw s,o+4*(n)(b)
 153#define SAVE_2EVRS(n,s,b,o)     SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
 154#define SAVE_4EVRS(n,s,b,o)     SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
 155#define SAVE_8EVRS(n,s,b,o)     SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
 156#define SAVE_16EVRS(n,s,b,o)    SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
 157#define SAVE_32EVRS(n,s,b,o)    SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
 158#define REST_EVR(n,s,b,o)       lwz s,o+4*(n)(b); evmergelo n,s,n
 159#define REST_2EVRS(n,s,b,o)     REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
 160#define REST_4EVRS(n,s,b,o)     REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
 161#define REST_8EVRS(n,s,b,o)     REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
 162#define REST_16EVRS(n,s,b,o)    REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
 163#define REST_32EVRS(n,s,b,o)    REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
 164
 165/* Macros to adjust thread priority for hardware multithreading */
 166#define HMT_VERY_LOW    or      31,31,31        # very low priority
 167#define HMT_LOW         or      1,1,1
 168#define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
 169#define HMT_MEDIUM      or      2,2,2
 170#define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 171#define HMT_HIGH        or      3,3,3
 172#define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 173
 174#ifdef CONFIG_PPC64
 175#define ULONG_SIZE      8
 176#else
 177#define ULONG_SIZE      4
 178#endif
 179#define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
 180#define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
 181
 182#ifdef __KERNEL__
 183#ifdef CONFIG_PPC64
 184
 185#define STACKFRAMESIZE 256
 186#define __STK_REG(i)   (112 + ((i)-14)*8)
 187#define STK_REG(i)     __STK_REG(__REG_##i)
 188
 189#ifdef PPC64_ELF_ABI_v2
 190#define STK_GOT         24
 191#define __STK_PARAM(i)  (32 + ((i)-3)*8)
 192#else
 193#define STK_GOT         40
 194#define __STK_PARAM(i)  (48 + ((i)-3)*8)
 195#endif
 196#define STK_PARAM(i)    __STK_PARAM(__REG_##i)
 197
 198#ifdef PPC64_ELF_ABI_v2
 199
 200#define _GLOBAL(name) \
 201        .align 2 ; \
 202        .type name,@function; \
 203        .globl name; \
 204name:
 205
 206#define _GLOBAL_TOC(name) \
 207        .align 2 ; \
 208        .type name,@function; \
 209        .globl name; \
 210name: \
 2110:      addis r2,r12,(.TOC.-0b)@ha; \
 212        addi r2,r2,(.TOC.-0b)@l; \
 213        .localentry name,.-name
 214
 215#define DOTSYM(a)       a
 216
 217#else
 218
 219#define XGLUE(a,b) a##b
 220#define GLUE(a,b) XGLUE(a,b)
 221
 222#define _GLOBAL(name) \
 223        .align 2 ; \
 224        .globl name; \
 225        .globl GLUE(.,name); \
 226        .pushsection ".opd","aw"; \
 227name: \
 228        .quad GLUE(.,name); \
 229        .quad .TOC.@tocbase; \
 230        .quad 0; \
 231        .popsection; \
 232        .type GLUE(.,name),@function; \
 233GLUE(.,name):
 234
 235#define _GLOBAL_TOC(name) _GLOBAL(name)
 236
 237#define DOTSYM(a)       GLUE(.,a)
 238
 239#endif
 240
 241#else /* 32-bit */
 242
 243#define _ENTRY(n)       \
 244        .globl n;       \
 245n:
 246
 247#define _GLOBAL(n)      \
 248        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 249        .globl n;       \
 250n:
 251
 252#define _GLOBAL_TOC(name) _GLOBAL(name)
 253
 254#endif
 255
 256/*
 257 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
 258 * section, which gets emitted at the end of regular text.
 259 *
 260 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
 261 * a blacklist. The former is for core kprobe functions/data, the
 262 * latter is for those that incdentially must be excluded from probing
 263 * and allows them to be linked at more optimal location within text.
 264 */
 265#ifdef CONFIG_KPROBES
 266#define _ASM_NOKPROBE_SYMBOL(entry)                     \
 267        .pushsection "_kprobe_blacklist","aw";          \
 268        PPC_LONG (entry) ;                              \
 269        .popsection
 270#else
 271#define _ASM_NOKPROBE_SYMBOL(entry)
 272#endif
 273
 274#define FUNC_START(name)        _GLOBAL(name)
 275#define FUNC_END(name)
 276
 277/* 
 278 * LOAD_REG_IMMEDIATE(rn, expr)
 279 *   Loads the value of the constant expression 'expr' into register 'rn'
 280 *   using immediate instructions only.  Use this when it's important not
 281 *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 282 *   valid) and when 'expr' is a constant or absolute address.
 283 *
 284 * LOAD_REG_ADDR(rn, name)
 285 *   Loads the address of label 'name' into register 'rn'.  Use this when
 286 *   you don't particularly need immediate instructions only, but you need
 287 *   the whole address in one register (e.g. it's a structure address and
 288 *   you want to access various offsets within it).  On ppc32 this is
 289 *   identical to LOAD_REG_IMMEDIATE.
 290 *
 291 * LOAD_REG_ADDR_PIC(rn, name)
 292 *   Loads the address of label 'name' into register 'run'. Use this when
 293 *   the kernel doesn't run at the linked or relocated address. Please
 294 *   note that this macro will clobber the lr register.
 295 *
 296 * LOAD_REG_ADDRBASE(rn, name)
 297 * ADDROFF(name)
 298 *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 299 *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 300 *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 301 *   in size, so is suitable for use directly as an offset in load and store
 302 *   instructions.  Use this when loading/storing a single word or less as:
 303 *      LOAD_REG_ADDRBASE(rX, name)
 304 *      ld      rY,ADDROFF(name)(rX)
 305 */
 306
 307/* Be careful, this will clobber the lr register. */
 308#define LOAD_REG_ADDR_PIC(reg, name)            \
 309        bl      0f;                             \
 3100:      mflr    reg;                            \
 311        addis   reg,reg,(name - 0b)@ha;         \
 312        addi    reg,reg,(name - 0b)@l;
 313
 314#ifdef __powerpc64__
 315#ifdef HAVE_AS_ATHIGH
 316#define __AS_ATHIGH high
 317#else
 318#define __AS_ATHIGH h
 319#endif
 320#define LOAD_REG_IMMEDIATE(reg,expr)            \
 321        lis     reg,(expr)@highest;             \
 322        ori     reg,reg,(expr)@higher;  \
 323        rldicr  reg,reg,32,31;          \
 324        oris    reg,reg,(expr)@__AS_ATHIGH;     \
 325        ori     reg,reg,(expr)@l;
 326
 327#define LOAD_REG_ADDR(reg,name)                 \
 328        ld      reg,name@got(r2)
 329
 330#define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 331#define ADDROFF(name)                   0
 332
 333/* offsets for stack frame layout */
 334#define LRSAVE  16
 335
 336#else /* 32-bit */
 337
 338#define LOAD_REG_IMMEDIATE(reg,expr)            \
 339        lis     reg,(expr)@ha;          \
 340        addi    reg,reg,(expr)@l;
 341
 342#define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
 343
 344#define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
 345#define ADDROFF(name)                   name@l
 346
 347/* offsets for stack frame layout */
 348#define LRSAVE  4
 349
 350#endif
 351
 352/* various errata or part fixups */
 353#ifdef CONFIG_PPC601_SYNC_FIX
 354#define SYNC                            \
 355BEGIN_FTR_SECTION                       \
 356        sync;                           \
 357        isync;                          \
 358END_FTR_SECTION_IFSET(CPU_FTR_601)
 359#define SYNC_601                        \
 360BEGIN_FTR_SECTION                       \
 361        sync;                           \
 362END_FTR_SECTION_IFSET(CPU_FTR_601)
 363#define ISYNC_601                       \
 364BEGIN_FTR_SECTION                       \
 365        isync;                          \
 366END_FTR_SECTION_IFSET(CPU_FTR_601)
 367#else
 368#define SYNC
 369#define SYNC_601
 370#define ISYNC_601
 371#endif
 372
 373#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 374#define MFTB(dest)                      \
 37590:     mfspr dest, SPRN_TBRL;          \
 376BEGIN_FTR_SECTION_NESTED(96);           \
 377        cmpwi dest,0;                   \
 378        beq-  90b;                      \
 379END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 380#else
 381#define MFTB(dest)                      MFTBL(dest)
 382#endif
 383
 384#ifdef CONFIG_PPC_8xx
 385#define MFTBL(dest)                     mftb dest
 386#define MFTBU(dest)                     mftbu dest
 387#else
 388#define MFTBL(dest)                     mfspr dest, SPRN_TBRL
 389#define MFTBU(dest)                     mfspr dest, SPRN_TBRU
 390#endif
 391
 392#ifndef CONFIG_SMP
 393#define TLBSYNC
 394#else /* CONFIG_SMP */
 395/* tlbsync is not implemented on 601 */
 396#define TLBSYNC                         \
 397BEGIN_FTR_SECTION                       \
 398        tlbsync;                        \
 399        sync;                           \
 400END_FTR_SECTION_IFCLR(CPU_FTR_601)
 401#endif
 402
 403#ifdef CONFIG_PPC64
 404#define MTOCRF(FXM, RS)                 \
 405        BEGIN_FTR_SECTION_NESTED(848);  \
 406        mtcrf   (FXM), RS;              \
 407        FTR_SECTION_ELSE_NESTED(848);   \
 408        mtocrf (FXM), RS;               \
 409        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 410#endif
 411
 412/*
 413 * This instruction is not implemented on the PPC 603 or 601; however, on
 414 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 415 * All of these instructions exist in the 8xx, they have magical powers,
 416 * and they must be used.
 417 */
 418
 419#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
 420#define tlbia                                   \
 421        li      r4,1024;                        \
 422        mtctr   r4;                             \
 423        lis     r4,KERNELBASE@h;                \
 424        .machine push;                          \
 425        .machine "power4";                      \
 4260:      tlbie   r4;                             \
 427        .machine pop;                           \
 428        addi    r4,r4,0x1000;                   \
 429        bdnz    0b
 430#endif
 431
 432
 433#ifdef CONFIG_IBM440EP_ERR42
 434#define PPC440EP_ERR42 isync
 435#else
 436#define PPC440EP_ERR42
 437#endif
 438
 439/* The following stops all load and store data streams associated with stream
 440 * ID (ie. streams created explicitly).  The embedded and server mnemonics for
 441 * dcbt are different so this must only be used for server.
 442 */
 443#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch)        \
 444       lis     scratch,0x60000000@h;                    \
 445       dcbt    0,scratch,0b01010
 446
 447/*
 448 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
 449 * keep the address intact to be compatible with code shared with
 450 * 32-bit classic.
 451 *
 452 * On the other hand, I find it useful to have them behave as expected
 453 * by their name (ie always do the addition) on 64-bit BookE
 454 */
 455#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 456#define toreal(rd)
 457#define fromreal(rd)
 458
 459/*
 460 * We use addis to ensure compatibility with the "classic" ppc versions of
 461 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
 462 * converting the address in r0, and so this version has to do that too
 463 * (i.e. set register rd to 0 when rs == 0).
 464 */
 465#define tophys(rd,rs)                           \
 466        addis   rd,rs,0
 467
 468#define tovirt(rd,rs)                           \
 469        addis   rd,rs,0
 470
 471#elif defined(CONFIG_PPC64)
 472#define toreal(rd)              /* we can access c000... in real mode */
 473#define fromreal(rd)
 474
 475#define tophys(rd,rs)                           \
 476        clrldi  rd,rs,2
 477
 478#define tovirt(rd,rs)                           \
 479        rotldi  rd,rs,16;                       \
 480        ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 481        rotldi  rd,rd,48
 482#else
 483#define toreal(rd)      tophys(rd,rd)
 484#define fromreal(rd)    tovirt(rd,rd)
 485
 486#define tophys(rd, rs)  addis   rd, rs, -PAGE_OFFSET@h
 487#define tovirt(rd, rs)  addis   rd, rs, PAGE_OFFSET@h
 488#endif
 489
 490#ifdef CONFIG_PPC_BOOK3S_64
 491#define RFI             rfid
 492#define MTMSRD(r)       mtmsrd  r
 493#define MTMSR_EERI(reg) mtmsrd  reg,1
 494#else
 495#ifndef CONFIG_40x
 496#define RFI             rfi
 497#else
 498#define RFI             rfi; b .        /* Prevent prefetch past rfi */
 499#endif
 500#define MTMSRD(r)       mtmsr   r
 501#define MTMSR_EERI(reg) mtmsr   reg
 502#endif
 503
 504#endif /* __KERNEL__ */
 505
 506/* The boring bits... */
 507
 508/* Condition Register Bit Fields */
 509
 510#define cr0     0
 511#define cr1     1
 512#define cr2     2
 513#define cr3     3
 514#define cr4     4
 515#define cr5     5
 516#define cr6     6
 517#define cr7     7
 518
 519
 520/*
 521 * General Purpose Registers (GPRs)
 522 *
 523 * The lower case r0-r31 should be used in preference to the upper
 524 * case R0-R31 as they provide more error checking in the assembler.
 525 * Use R0-31 only when really nessesary.
 526 */
 527
 528#define r0      %r0
 529#define r1      %r1
 530#define r2      %r2
 531#define r3      %r3
 532#define r4      %r4
 533#define r5      %r5
 534#define r6      %r6
 535#define r7      %r7
 536#define r8      %r8
 537#define r9      %r9
 538#define r10     %r10
 539#define r11     %r11
 540#define r12     %r12
 541#define r13     %r13
 542#define r14     %r14
 543#define r15     %r15
 544#define r16     %r16
 545#define r17     %r17
 546#define r18     %r18
 547#define r19     %r19
 548#define r20     %r20
 549#define r21     %r21
 550#define r22     %r22
 551#define r23     %r23
 552#define r24     %r24
 553#define r25     %r25
 554#define r26     %r26
 555#define r27     %r27
 556#define r28     %r28
 557#define r29     %r29
 558#define r30     %r30
 559#define r31     %r31
 560
 561
 562/* Floating Point Registers (FPRs) */
 563
 564#define fr0     0
 565#define fr1     1
 566#define fr2     2
 567#define fr3     3
 568#define fr4     4
 569#define fr5     5
 570#define fr6     6
 571#define fr7     7
 572#define fr8     8
 573#define fr9     9
 574#define fr10    10
 575#define fr11    11
 576#define fr12    12
 577#define fr13    13
 578#define fr14    14
 579#define fr15    15
 580#define fr16    16
 581#define fr17    17
 582#define fr18    18
 583#define fr19    19
 584#define fr20    20
 585#define fr21    21
 586#define fr22    22
 587#define fr23    23
 588#define fr24    24
 589#define fr25    25
 590#define fr26    26
 591#define fr27    27
 592#define fr28    28
 593#define fr29    29
 594#define fr30    30
 595#define fr31    31
 596
 597/* AltiVec Registers (VPRs) */
 598
 599#define v0      0
 600#define v1      1
 601#define v2      2
 602#define v3      3
 603#define v4      4
 604#define v5      5
 605#define v6      6
 606#define v7      7
 607#define v8      8
 608#define v9      9
 609#define v10     10
 610#define v11     11
 611#define v12     12
 612#define v13     13
 613#define v14     14
 614#define v15     15
 615#define v16     16
 616#define v17     17
 617#define v18     18
 618#define v19     19
 619#define v20     20
 620#define v21     21
 621#define v22     22
 622#define v23     23
 623#define v24     24
 624#define v25     25
 625#define v26     26
 626#define v27     27
 627#define v28     28
 628#define v29     29
 629#define v30     30
 630#define v31     31
 631
 632/* VSX Registers (VSRs) */
 633
 634#define vs0     0
 635#define vs1     1
 636#define vs2     2
 637#define vs3     3
 638#define vs4     4
 639#define vs5     5
 640#define vs6     6
 641#define vs7     7
 642#define vs8     8
 643#define vs9     9
 644#define vs10    10
 645#define vs11    11
 646#define vs12    12
 647#define vs13    13
 648#define vs14    14
 649#define vs15    15
 650#define vs16    16
 651#define vs17    17
 652#define vs18    18
 653#define vs19    19
 654#define vs20    20
 655#define vs21    21
 656#define vs22    22
 657#define vs23    23
 658#define vs24    24
 659#define vs25    25
 660#define vs26    26
 661#define vs27    27
 662#define vs28    28
 663#define vs29    29
 664#define vs30    30
 665#define vs31    31
 666#define vs32    32
 667#define vs33    33
 668#define vs34    34
 669#define vs35    35
 670#define vs36    36
 671#define vs37    37
 672#define vs38    38
 673#define vs39    39
 674#define vs40    40
 675#define vs41    41
 676#define vs42    42
 677#define vs43    43
 678#define vs44    44
 679#define vs45    45
 680#define vs46    46
 681#define vs47    47
 682#define vs48    48
 683#define vs49    49
 684#define vs50    50
 685#define vs51    51
 686#define vs52    52
 687#define vs53    53
 688#define vs54    54
 689#define vs55    55
 690#define vs56    56
 691#define vs57    57
 692#define vs58    58
 693#define vs59    59
 694#define vs60    60
 695#define vs61    61
 696#define vs62    62
 697#define vs63    63
 698
 699/* SPE Registers (EVPRs) */
 700
 701#define evr0    0
 702#define evr1    1
 703#define evr2    2
 704#define evr3    3
 705#define evr4    4
 706#define evr5    5
 707#define evr6    6
 708#define evr7    7
 709#define evr8    8
 710#define evr9    9
 711#define evr10   10
 712#define evr11   11
 713#define evr12   12
 714#define evr13   13
 715#define evr14   14
 716#define evr15   15
 717#define evr16   16
 718#define evr17   17
 719#define evr18   18
 720#define evr19   19
 721#define evr20   20
 722#define evr21   21
 723#define evr22   22
 724#define evr23   23
 725#define evr24   24
 726#define evr25   25
 727#define evr26   26
 728#define evr27   27
 729#define evr28   28
 730#define evr29   29
 731#define evr30   30
 732#define evr31   31
 733
 734/* some stab codes */
 735#define N_FUN   36
 736#define N_RSYM  64
 737#define N_SLINE 68
 738#define N_SO    100
 739
 740/*
 741 * Create an endian fixup trampoline
 742 *
 743 * This starts with a "tdi 0,0,0x48" instruction which is
 744 * essentially a "trap never", and thus akin to a nop.
 745 *
 746 * The opcode for this instruction read with the wrong endian
 747 * however results in a b . + 8
 748 *
 749 * So essentially we use that trick to execute the following
 750 * trampoline in "reverse endian" if we are running with the
 751 * MSR_LE bit set the "wrong" way for whatever endianness the
 752 * kernel is built for.
 753 */
 754
 755#ifdef CONFIG_PPC_BOOK3E
 756#define FIXUP_ENDIAN
 757#else
 758/*
 759 * This version may be used in in HV or non-HV context.
 760 * MSR[EE] must be disabled.
 761 */
 762#define FIXUP_ENDIAN                                               \
 763        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 764        b     191f;       /* Skip trampoline if endian is good  */ \
 765        .long 0xa600607d; /* mfmsr r11                          */ \
 766        .long 0x01006b69; /* xori r11,r11,1                     */ \
 767        .long 0x00004039; /* li r10,0                           */ \
 768        .long 0x6401417d; /* mtmsrd r10,1                       */ \
 769        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 770        .long 0xa602487d; /* mflr r10                           */ \
 771        .long 0x14004a39; /* addi r10,r10,20                    */ \
 772        .long 0xa6035a7d; /* mtsrr0 r10                         */ \
 773        .long 0xa6037b7d; /* mtsrr1 r11                         */ \
 774        .long 0x2400004c; /* rfid                               */ \
 775191:
 776
 777/*
 778 * This version that may only be used with MSR[HV]=1
 779 * - Does not clear MSR[RI], so more robust.
 780 * - Slightly smaller and faster.
 781 */
 782#define FIXUP_ENDIAN_HV                                            \
 783        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 784        b     191f;       /* Skip trampoline if endian is good  */ \
 785        .long 0xa600607d; /* mfmsr r11                          */ \
 786        .long 0x01006b69; /* xori r11,r11,1                     */ \
 787        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 788        .long 0xa602487d; /* mflr r10                           */ \
 789        .long 0x14004a39; /* addi r10,r10,20                    */ \
 790        .long 0xa64b5a7d; /* mthsrr0 r10                        */ \
 791        .long 0xa64b7b7d; /* mthsrr1 r11                        */ \
 792        .long 0x2402004c; /* hrfid                              */ \
 793191:
 794
 795#endif /* !CONFIG_PPC_BOOK3E */
 796
 797#endif /*  __ASSEMBLY__ */
 798
 799/*
 800 * Helper macro for exception table entries
 801 */
 802#define EX_TABLE(_fault, _target)               \
 803        stringify_in_c(.section __ex_table,"a";)\
 804        stringify_in_c(.balign 4;)              \
 805        stringify_in_c(.long (_fault) - . ;)    \
 806        stringify_in_c(.long (_target) - . ;)   \
 807        stringify_in_c(.previous)
 808
 809#ifdef CONFIG_PPC_FSL_BOOK3E
 810#define BTB_FLUSH(reg)                  \
 811        lis reg,BUCSR_INIT@h;           \
 812        ori reg,reg,BUCSR_INIT@l;       \
 813        mtspr SPRN_BUCSR,reg;           \
 814        isync;
 815#else
 816#define BTB_FLUSH(reg)
 817#endif /* CONFIG_PPC_FSL_BOOK3E */
 818
 819#endif /* _ASM_POWERPC_PPC_ASM_H */
 820