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12#include <linux/delay.h>
13#include <linux/export.h>
14#include <linux/gfp.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18
19#include <asm/pci-bridge.h>
20#include <asm/ppc-pci.h>
21
22static int eeh_pe_aux_size = 0;
23static LIST_HEAD(eeh_phb_pe);
24
25
26
27
28
29
30
31void eeh_set_pe_aux_size(int size)
32{
33 if (size < 0)
34 return;
35
36 eeh_pe_aux_size = size;
37}
38
39
40
41
42
43
44
45
46static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
47{
48 struct eeh_pe *pe;
49 size_t alloc_size;
50
51 alloc_size = sizeof(struct eeh_pe);
52 if (eeh_pe_aux_size) {
53 alloc_size = ALIGN(alloc_size, cache_line_size());
54 alloc_size += eeh_pe_aux_size;
55 }
56
57
58 pe = kzalloc(alloc_size, GFP_KERNEL);
59 if (!pe) return NULL;
60
61
62 pe->type = type;
63 pe->phb = phb;
64 INIT_LIST_HEAD(&pe->child_list);
65 INIT_LIST_HEAD(&pe->edevs);
66
67 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
68 cache_line_size());
69 return pe;
70}
71
72
73
74
75
76
77
78
79int eeh_phb_pe_create(struct pci_controller *phb)
80{
81 struct eeh_pe *pe;
82
83
84 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
85 if (!pe) {
86 pr_err("%s: out of memory!\n", __func__);
87 return -ENOMEM;
88 }
89
90
91 list_add_tail(&pe->child, &eeh_phb_pe);
92
93 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
94
95 return 0;
96}
97
98
99
100
101
102
103
104
105
106int eeh_wait_state(struct eeh_pe *pe, int max_wait)
107{
108 int ret;
109 int mwait;
110
111
112
113
114
115
116
117
118
119#define EEH_STATE_MIN_WAIT_TIME (1000)
120#define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
121
122 while (1) {
123 ret = eeh_ops->get_state(pe, &mwait);
124
125 if (ret != EEH_STATE_UNAVAILABLE)
126 return ret;
127
128 if (max_wait <= 0) {
129 pr_warn("%s: Timeout when getting PE's state (%d)\n",
130 __func__, max_wait);
131 return EEH_STATE_NOT_SUPPORT;
132 }
133
134 if (mwait < EEH_STATE_MIN_WAIT_TIME) {
135 pr_warn("%s: Firmware returned bad wait value %d\n",
136 __func__, mwait);
137 mwait = EEH_STATE_MIN_WAIT_TIME;
138 } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
139 pr_warn("%s: Firmware returned too long wait value %d\n",
140 __func__, mwait);
141 mwait = EEH_STATE_MAX_WAIT_TIME;
142 }
143
144 msleep(min(mwait, max_wait));
145 max_wait -= mwait;
146 }
147}
148
149
150
151
152
153
154
155
156
157struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
158{
159 struct eeh_pe *pe;
160
161 list_for_each_entry(pe, &eeh_phb_pe, child) {
162
163
164
165
166
167 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
168 return pe;
169 }
170
171 return NULL;
172}
173
174
175
176
177
178
179
180
181
182struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
183{
184 struct list_head *next = pe->child_list.next;
185
186 if (next == &pe->child_list) {
187 while (1) {
188 if (pe == root)
189 return NULL;
190 next = pe->child.next;
191 if (next != &pe->parent->child_list)
192 break;
193 pe = pe->parent;
194 }
195 }
196
197 return list_entry(next, struct eeh_pe, child);
198}
199
200
201
202
203
204
205
206
207
208
209
210
211void *eeh_pe_traverse(struct eeh_pe *root,
212 eeh_pe_traverse_func fn, void *flag)
213{
214 struct eeh_pe *pe;
215 void *ret;
216
217 eeh_for_each_pe(root, pe) {
218 ret = fn(pe, flag);
219 if (ret) return ret;
220 }
221
222 return NULL;
223}
224
225
226
227
228
229
230
231
232
233
234void *eeh_pe_dev_traverse(struct eeh_pe *root,
235 eeh_edev_traverse_func fn, void *flag)
236{
237 struct eeh_pe *pe;
238 struct eeh_dev *edev, *tmp;
239 void *ret;
240
241 if (!root) {
242 pr_warn("%s: Invalid PE %p\n",
243 __func__, root);
244 return NULL;
245 }
246
247
248 eeh_for_each_pe(root, pe) {
249 eeh_pe_for_each_dev(pe, edev, tmp) {
250 ret = fn(edev, flag);
251 if (ret)
252 return ret;
253 }
254 }
255
256 return NULL;
257}
258
259
260
261
262
263
264
265
266
267
268
269struct eeh_pe_get_flag {
270 int pe_no;
271 int config_addr;
272};
273
274static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
275{
276 struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
277
278
279 if (pe->type & EEH_PE_PHB)
280 return NULL;
281
282
283
284
285
286 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
287 if (tmp->pe_no == pe->addr)
288 return pe;
289 } else {
290 if (tmp->pe_no &&
291 (tmp->pe_no == pe->addr))
292 return pe;
293 }
294
295
296 if (tmp->config_addr &&
297 (tmp->config_addr == pe->config_addr))
298 return pe;
299
300 return NULL;
301}
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
317 int pe_no, int config_addr)
318{
319 struct eeh_pe *root = eeh_phb_pe_get(phb);
320 struct eeh_pe_get_flag tmp = { pe_no, config_addr };
321 struct eeh_pe *pe;
322
323 pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
324
325 return pe;
326}
327
328
329
330
331
332
333
334
335
336static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
337{
338 struct eeh_dev *parent;
339 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
340
341
342
343
344
345
346 if (edev->physfn)
347 pdn = pci_get_pdn(edev->physfn);
348 else
349 pdn = pdn ? pdn->parent : NULL;
350 while (pdn) {
351
352 parent = pdn_to_eeh_dev(pdn);
353 if (!parent)
354 return NULL;
355
356 if (parent->pe)
357 return parent->pe;
358
359 pdn = pdn->parent;
360 }
361
362 return NULL;
363}
364
365
366
367
368
369
370
371
372
373
374int eeh_add_to_parent_pe(struct eeh_dev *edev)
375{
376 struct eeh_pe *pe, *parent;
377 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
378 int config_addr = (pdn->busno << 8) | (pdn->devfn);
379
380
381 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
382 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
383 __func__, config_addr, pdn->phb->global_number);
384 return -EINVAL;
385 }
386
387
388
389
390
391
392
393 pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
394 if (pe && !(pe->type & EEH_PE_INVALID)) {
395
396 pe->type = EEH_PE_BUS;
397 edev->pe = pe;
398
399
400 list_add_tail(&edev->entry, &pe->edevs);
401 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
402 pdn->phb->global_number,
403 pdn->busno,
404 PCI_SLOT(pdn->devfn),
405 PCI_FUNC(pdn->devfn),
406 pe->addr);
407 return 0;
408 } else if (pe && (pe->type & EEH_PE_INVALID)) {
409 list_add_tail(&edev->entry, &pe->edevs);
410 edev->pe = pe;
411
412
413
414
415 parent = pe;
416 while (parent) {
417 if (!(parent->type & EEH_PE_INVALID))
418 break;
419 parent->type &= ~EEH_PE_INVALID;
420 parent = parent->parent;
421 }
422
423 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
424 "PE#%x, Parent PE#%x\n",
425 pdn->phb->global_number,
426 pdn->busno,
427 PCI_SLOT(pdn->devfn),
428 PCI_FUNC(pdn->devfn),
429 pe->addr, pe->parent->addr);
430 return 0;
431 }
432
433
434 if (edev->physfn)
435 pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
436 else
437 pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
438 if (!pe) {
439 pr_err("%s: out of memory!\n", __func__);
440 return -ENOMEM;
441 }
442 pe->addr = edev->pe_config_addr;
443 pe->config_addr = config_addr;
444
445
446
447
448
449
450
451 parent = eeh_pe_get_parent(edev);
452 if (!parent) {
453 parent = eeh_phb_pe_get(pdn->phb);
454 if (!parent) {
455 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
456 __func__, pdn->phb->global_number);
457 edev->pe = NULL;
458 kfree(pe);
459 return -EEXIST;
460 }
461 }
462 pe->parent = parent;
463
464
465
466
467
468 list_add_tail(&pe->child, &parent->child_list);
469 list_add_tail(&edev->entry, &pe->edevs);
470 edev->pe = pe;
471 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
472 "Device PE#%x, Parent PE#%x\n",
473 pdn->phb->global_number,
474 pdn->busno,
475 PCI_SLOT(pdn->devfn),
476 PCI_FUNC(pdn->devfn),
477 pe->addr, pe->parent->addr);
478
479 return 0;
480}
481
482
483
484
485
486
487
488
489
490
491int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
492{
493 struct eeh_pe *pe, *parent, *child;
494 int cnt;
495 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
496
497 pe = eeh_dev_to_pe(edev);
498 if (!pe) {
499 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
500 __func__, pdn->phb->global_number,
501 pdn->busno,
502 PCI_SLOT(pdn->devfn),
503 PCI_FUNC(pdn->devfn));
504 return -EEXIST;
505 }
506
507
508 edev->pe = NULL;
509 list_del(&edev->entry);
510
511
512
513
514
515
516
517 while (1) {
518 parent = pe->parent;
519 if (pe->type & EEH_PE_PHB)
520 break;
521
522 if (!(pe->state & EEH_PE_KEEP)) {
523 if (list_empty(&pe->edevs) &&
524 list_empty(&pe->child_list)) {
525 list_del(&pe->child);
526 kfree(pe);
527 } else {
528 break;
529 }
530 } else {
531 if (list_empty(&pe->edevs)) {
532 cnt = 0;
533 list_for_each_entry(child, &pe->child_list, child) {
534 if (!(child->type & EEH_PE_INVALID)) {
535 cnt++;
536 break;
537 }
538 }
539
540 if (!cnt)
541 pe->type |= EEH_PE_INVALID;
542 else
543 break;
544 }
545 }
546
547 pe = parent;
548 }
549
550 return 0;
551}
552
553
554
555
556
557
558
559
560
561
562void eeh_pe_update_time_stamp(struct eeh_pe *pe)
563{
564 time64_t tstamp;
565
566 if (!pe) return;
567
568 if (pe->freeze_count <= 0) {
569 pe->freeze_count = 0;
570 pe->tstamp = ktime_get_seconds();
571 } else {
572 tstamp = ktime_get_seconds();
573 if (tstamp - pe->tstamp > 3600) {
574 pe->tstamp = tstamp;
575 pe->freeze_count = 0;
576 }
577 }
578}
579
580
581
582
583
584
585
586
587
588void eeh_pe_state_mark(struct eeh_pe *root, int state)
589{
590 struct eeh_pe *pe;
591
592 eeh_for_each_pe(root, pe)
593 if (!(pe->state & EEH_PE_REMOVED))
594 pe->state |= state;
595}
596EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
597
598
599
600
601
602
603
604
605
606void eeh_pe_mark_isolated(struct eeh_pe *root)
607{
608 struct eeh_pe *pe;
609 struct eeh_dev *edev;
610 struct pci_dev *pdev;
611
612 eeh_pe_state_mark(root, EEH_PE_ISOLATED);
613 eeh_for_each_pe(root, pe) {
614 list_for_each_entry(edev, &pe->edevs, entry) {
615 pdev = eeh_dev_to_pci_dev(edev);
616 if (pdev)
617 pdev->error_state = pci_channel_io_frozen;
618 }
619
620 if (pe->state & EEH_PE_CFG_RESTRICTED)
621 pe->state |= EEH_PE_CFG_BLOCKED;
622 }
623}
624EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated);
625
626static void *__eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag)
627{
628 int mode = *((int *)flag);
629
630 edev->mode |= mode;
631
632 return NULL;
633}
634
635
636
637
638
639
640
641void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
642{
643 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
644}
645
646
647
648
649
650
651
652
653
654
655
656void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed)
657{
658 struct eeh_pe *pe;
659 struct eeh_dev *edev, *tmp;
660 struct pci_dev *pdev;
661
662 eeh_for_each_pe(root, pe) {
663
664 if (pe->state & EEH_PE_REMOVED)
665 continue;
666
667 if (!include_passed && eeh_pe_passed(pe))
668 continue;
669
670 pe->state &= ~state;
671
672
673
674
675
676
677 if (!(state & EEH_PE_ISOLATED))
678 continue;
679
680 pe->check_count = 0;
681 eeh_pe_for_each_dev(pe, edev, tmp) {
682 pdev = eeh_dev_to_pci_dev(edev);
683 if (!pdev)
684 continue;
685
686 pdev->error_state = pci_channel_io_normal;
687 }
688
689
690 if (pe->state & EEH_PE_CFG_RESTRICTED)
691 pe->state &= ~EEH_PE_CFG_BLOCKED;
692 }
693}
694
695
696
697
698
699
700
701
702
703
704
705
706static void eeh_bridge_check_link(struct eeh_dev *edev)
707{
708 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
709 int cap;
710 uint32_t val;
711 int timeout = 0;
712
713
714
715
716
717 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
718 return;
719
720 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
721 __func__, pdn->phb->global_number,
722 pdn->busno,
723 PCI_SLOT(pdn->devfn),
724 PCI_FUNC(pdn->devfn));
725
726
727 cap = edev->pcie_cap;
728 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
729 if (!(val & PCI_EXP_SLTSTA_PDS)) {
730 pr_debug(" No card in the slot (0x%04x) !\n", val);
731 return;
732 }
733
734
735 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
736 if (val & PCI_EXP_SLTCAP_PCP) {
737 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
738 if (val & PCI_EXP_SLTCTL_PCC) {
739 pr_debug(" In power-off state, power it on ...\n");
740 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
741 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
742 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
743 msleep(2 * 1000);
744 }
745 }
746
747
748 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
749 val &= ~PCI_EXP_LNKCTL_LD;
750 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
751
752
753 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
754 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
755 pr_debug(" No link reporting capability (0x%08x) \n", val);
756 msleep(1000);
757 return;
758 }
759
760
761 timeout = 0;
762 while (timeout < 5000) {
763 msleep(20);
764 timeout += 20;
765
766 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
767 if (val & PCI_EXP_LNKSTA_DLLLA)
768 break;
769 }
770
771 if (val & PCI_EXP_LNKSTA_DLLLA)
772 pr_debug(" Link up (%s)\n",
773 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
774 else
775 pr_debug(" Link not ready (0x%04x)\n", val);
776}
777
778#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
779#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
780
781static void eeh_restore_bridge_bars(struct eeh_dev *edev)
782{
783 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
784 int i;
785
786
787
788
789
790 for (i = 4; i < 13; i++)
791 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
792
793 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
794
795
796 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
797 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
798 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
799 SAVED_BYTE(PCI_LATENCY_TIMER));
800
801 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
802
803
804 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
805 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
806
807
808 eeh_bridge_check_link(edev);
809}
810
811static void eeh_restore_device_bars(struct eeh_dev *edev)
812{
813 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
814 int i;
815 u32 cmd;
816
817 for (i = 4; i < 10; i++)
818 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
819
820 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
821
822 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
823 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
824 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
825 SAVED_BYTE(PCI_LATENCY_TIMER));
826
827
828 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
829
830
831
832
833
834 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
835 if (edev->config_space[1] & PCI_COMMAND_PARITY)
836 cmd |= PCI_COMMAND_PARITY;
837 else
838 cmd &= ~PCI_COMMAND_PARITY;
839 if (edev->config_space[1] & PCI_COMMAND_SERR)
840 cmd |= PCI_COMMAND_SERR;
841 else
842 cmd &= ~PCI_COMMAND_SERR;
843 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
844}
845
846
847
848
849
850
851
852
853
854
855static void *eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag)
856{
857 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
858
859
860 if (edev->mode & EEH_DEV_BRIDGE)
861 eeh_restore_bridge_bars(edev);
862 else
863 eeh_restore_device_bars(edev);
864
865 if (eeh_ops->restore_config && pdn)
866 eeh_ops->restore_config(pdn);
867
868 return NULL;
869}
870
871
872
873
874
875
876
877
878void eeh_pe_restore_bars(struct eeh_pe *pe)
879{
880
881
882
883
884 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
885}
886
887
888
889
890
891
892
893
894
895
896const char *eeh_pe_loc_get(struct eeh_pe *pe)
897{
898 struct pci_bus *bus = eeh_pe_bus_get(pe);
899 struct device_node *dn;
900 const char *loc = NULL;
901
902 while (bus) {
903 dn = pci_bus_to_OF_node(bus);
904 if (!dn) {
905 bus = bus->parent;
906 continue;
907 }
908
909 if (pci_is_root_bus(bus))
910 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
911 else
912 loc = of_get_property(dn, "ibm,slot-location-code",
913 NULL);
914
915 if (loc)
916 return loc;
917
918 bus = bus->parent;
919 }
920
921 return "N/A";
922}
923
924
925
926
927
928
929
930
931
932
933
934struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
935{
936 struct eeh_dev *edev;
937 struct pci_dev *pdev;
938
939 if (pe->type & EEH_PE_PHB)
940 return pe->phb->bus;
941
942
943 if (pe->state & EEH_PE_PRI_BUS)
944 return pe->bus;
945
946
947 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
948 pdev = eeh_dev_to_pci_dev(edev);
949 if (pdev)
950 return pdev->bus;
951
952 return NULL;
953}
954