LXR linux/arch/powerpc/kernel/exceptions-64e.S

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 *  Boot code and exception vectors for Book3E processors
   4 *
   5 *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
   6 */
   7
   8#include <linux/threads.h>
   9#include <asm/reg.h>
  10#include <asm/page.h>
  11#include <asm/ppc_asm.h>
  12#include <asm/asm-offsets.h>
  13#include <asm/cputable.h>
  14#include <asm/setup.h>
  15#include <asm/thread_info.h>
  16#include <asm/reg_a2.h>
  17#include <asm/exception-64e.h>
  18#include <asm/bug.h>
  19#include <asm/irqflags.h>
  20#include <asm/ptrace.h>
  21#include <asm/ppc-opcode.h>
  22#include <asm/mmu.h>
  23#include <asm/hw_irq.h>
  24#include <asm/kvm_asm.h>
  25#include <asm/kvm_booke_hv_asm.h>
  26#include <asm/feature-fixups.h>
  27
  28/* XXX This will ultimately add space for a special exception save
  29 *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
  30 *     when taking special interrupts. For now we don't support that,
  31 *     special interrupts from within a non-standard level will probably
  32 *     blow you up
  33 */
  34#define SPECIAL_EXC_SRR0        0
  35#define SPECIAL_EXC_SRR1        1
  36#define SPECIAL_EXC_SPRG_GEN    2
  37#define SPECIAL_EXC_SPRG_TLB    3
  38#define SPECIAL_EXC_MAS0        4
  39#define SPECIAL_EXC_MAS1        5
  40#define SPECIAL_EXC_MAS2        6
  41#define SPECIAL_EXC_MAS3        7
  42#define SPECIAL_EXC_MAS6        8
  43#define SPECIAL_EXC_MAS7        9
  44#define SPECIAL_EXC_MAS5        10      /* E.HV only */
  45#define SPECIAL_EXC_MAS8        11      /* E.HV only */
  46#define SPECIAL_EXC_IRQHAPPENED 12
  47#define SPECIAL_EXC_DEAR        13
  48#define SPECIAL_EXC_ESR         14
  49#define SPECIAL_EXC_SOFTE       15
  50#define SPECIAL_EXC_CSRR0       16
  51#define SPECIAL_EXC_CSRR1       17
  52/* must be even to keep 16-byte stack alignment */
  53#define SPECIAL_EXC_END         18
  54
  55#define SPECIAL_EXC_FRAME_SIZE  (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
  56#define SPECIAL_EXC_FRAME_OFFS  (INT_FRAME_SIZE - 288)
  57
  58#define SPECIAL_EXC_STORE(reg, name) \
  59        std     reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  60
  61#define SPECIAL_EXC_LOAD(reg, name) \
  62        ld      reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  63
  64special_reg_save:
  65        lbz     r9,PACAIRQHAPPENED(r13)
  66        RECONCILE_IRQ_STATE(r3,r4)
  67
  68        /*
  69         * We only need (or have stack space) to save this stuff if
  70         * we interrupted the kernel.
  71         */
  72        ld      r3,_MSR(r1)
  73        andi.   r3,r3,MSR_PR
  74        bnelr
  75
  76        /*
  77         * Advance to the next TLB exception frame for handler
  78         * types that don't do it automatically.
  79         */
  80        LOAD_REG_ADDR(r11,extlb_level_exc)
  81        lwz     r12,0(r11)
  82        mfspr   r10,SPRN_SPRG_TLB_EXFRAME
  83        add     r10,r10,r12
  84        mtspr   SPRN_SPRG_TLB_EXFRAME,r10
  85
  86        /*
  87         * Save registers needed to allow nesting of certain exceptions
  88         * (such as TLB misses) inside special exception levels
  89         */
  90        mfspr   r10,SPRN_SRR0
  91        SPECIAL_EXC_STORE(r10,SRR0)
  92        mfspr   r10,SPRN_SRR1
  93        SPECIAL_EXC_STORE(r10,SRR1)
  94        mfspr   r10,SPRN_SPRG_GEN_SCRATCH
  95        SPECIAL_EXC_STORE(r10,SPRG_GEN)
  96        mfspr   r10,SPRN_SPRG_TLB_SCRATCH
  97        SPECIAL_EXC_STORE(r10,SPRG_TLB)
  98        mfspr   r10,SPRN_MAS0
  99        SPECIAL_EXC_STORE(r10,MAS0)
 100        mfspr   r10,SPRN_MAS1
 101        SPECIAL_EXC_STORE(r10,MAS1)
 102        mfspr   r10,SPRN_MAS2
 103        SPECIAL_EXC_STORE(r10,MAS2)
 104        mfspr   r10,SPRN_MAS3
 105        SPECIAL_EXC_STORE(r10,MAS3)
 106        mfspr   r10,SPRN_MAS6
 107        SPECIAL_EXC_STORE(r10,MAS6)
 108        mfspr   r10,SPRN_MAS7
 109        SPECIAL_EXC_STORE(r10,MAS7)
 110BEGIN_FTR_SECTION
 111        mfspr   r10,SPRN_MAS5
 112        SPECIAL_EXC_STORE(r10,MAS5)
 113        mfspr   r10,SPRN_MAS8
 114        SPECIAL_EXC_STORE(r10,MAS8)
 115
 116        /* MAS5/8 could have inappropriate values if we interrupted KVM code */
 117        li      r10,0
 118        mtspr   SPRN_MAS5,r10
 119        mtspr   SPRN_MAS8,r10
 120END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 121        SPECIAL_EXC_STORE(r9,IRQHAPPENED)
 122
 123        mfspr   r10,SPRN_DEAR
 124        SPECIAL_EXC_STORE(r10,DEAR)
 125        mfspr   r10,SPRN_ESR
 126        SPECIAL_EXC_STORE(r10,ESR)
 127
 128        lbz     r10,PACAIRQSOFTMASK(r13)
 129        SPECIAL_EXC_STORE(r10,SOFTE)
 130        ld      r10,_NIP(r1)
 131        SPECIAL_EXC_STORE(r10,CSRR0)
 132        ld      r10,_MSR(r1)
 133        SPECIAL_EXC_STORE(r10,CSRR1)
 134
 135        blr
 136
 137ret_from_level_except:
 138        ld      r3,_MSR(r1)
 139        andi.   r3,r3,MSR_PR
 140        beq     1f
 141        b       ret_from_except
 1421:
 143
 144        LOAD_REG_ADDR(r11,extlb_level_exc)
 145        lwz     r12,0(r11)
 146        mfspr   r10,SPRN_SPRG_TLB_EXFRAME
 147        sub     r10,r10,r12
 148        mtspr   SPRN_SPRG_TLB_EXFRAME,r10
 149
 150        /*
 151         * It's possible that the special level exception interrupted a
 152         * TLB miss handler, and inserted the same entry that the
 153         * interrupted handler was about to insert.  On CPUs without TLB
 154         * write conditional, this can result in a duplicate TLB entry.
 155         * Wipe all non-bolted entries to be safe.
 156         *
 157         * Note that this doesn't protect against any TLB misses
 158         * we may take accessing the stack from here to the end of
 159         * the special level exception.  It's not clear how we can
 160         * reasonably protect against that, but only CPUs with
 161         * neither TLB write conditional nor bolted kernel memory
 162         * are affected.  Do any such CPUs even exist?
 163         */
 164        PPC_TLBILX_ALL(0,R0)
 165
 166        REST_NVGPRS(r1)
 167
 168        SPECIAL_EXC_LOAD(r10,SRR0)
 169        mtspr   SPRN_SRR0,r10
 170        SPECIAL_EXC_LOAD(r10,SRR1)
 171        mtspr   SPRN_SRR1,r10
 172        SPECIAL_EXC_LOAD(r10,SPRG_GEN)
 173        mtspr   SPRN_SPRG_GEN_SCRATCH,r10
 174        SPECIAL_EXC_LOAD(r10,SPRG_TLB)
 175        mtspr   SPRN_SPRG_TLB_SCRATCH,r10
 176        SPECIAL_EXC_LOAD(r10,MAS0)
 177        mtspr   SPRN_MAS0,r10
 178        SPECIAL_EXC_LOAD(r10,MAS1)
 179        mtspr   SPRN_MAS1,r10
 180        SPECIAL_EXC_LOAD(r10,MAS2)
 181        mtspr   SPRN_MAS2,r10
 182        SPECIAL_EXC_LOAD(r10,MAS3)
 183        mtspr   SPRN_MAS3,r10
 184        SPECIAL_EXC_LOAD(r10,MAS6)
 185        mtspr   SPRN_MAS6,r10
 186        SPECIAL_EXC_LOAD(r10,MAS7)
 187        mtspr   SPRN_MAS7,r10
 188BEGIN_FTR_SECTION
 189        SPECIAL_EXC_LOAD(r10,MAS5)
 190        mtspr   SPRN_MAS5,r10
 191        SPECIAL_EXC_LOAD(r10,MAS8)
 192        mtspr   SPRN_MAS8,r10
 193END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 194
 195        lbz     r6,PACAIRQSOFTMASK(r13)
 196        ld      r5,SOFTE(r1)
 197
 198        /* Interrupts had better not already be enabled... */
 199        tweqi   r6,IRQS_ENABLED
 200
 201        andi.   r6,r5,IRQS_DISABLED
 202        bne     1f
 203
 204        TRACE_ENABLE_INTS
 205        stb     r5,PACAIRQSOFTMASK(r13)
 2061:
 207        /*
 208         * Restore PACAIRQHAPPENED rather than setting it based on
 209         * the return MSR[EE], since we could have interrupted
 210         * __check_irq_replay() or other inconsistent transitory
 211         * states that must remain that way.
 212         */
 213        SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
 214        stb     r10,PACAIRQHAPPENED(r13)
 215
 216        SPECIAL_EXC_LOAD(r10,DEAR)
 217        mtspr   SPRN_DEAR,r10
 218        SPECIAL_EXC_LOAD(r10,ESR)
 219        mtspr   SPRN_ESR,r10
 220
 221        stdcx.  r0,0,r1         /* to clear the reservation */
 222
 223        REST_4GPRS(2, r1)
 224        REST_4GPRS(6, r1)
 225
 226        ld      r10,_CTR(r1)
 227        ld      r11,_XER(r1)
 228        mtctr   r10
 229        mtxer   r11
 230
 231        blr
 232
 233.macro ret_from_level srr0 srr1 paca_ex scratch
 234        bl      ret_from_level_except
 235
 236        ld      r10,_LINK(r1)
 237        ld      r11,_CCR(r1)
 238        ld      r0,GPR13(r1)
 239        mtlr    r10
 240        mtcr    r11
 241
 242        ld      r10,GPR10(r1)
 243        ld      r11,GPR11(r1)
 244        ld      r12,GPR12(r1)
 245        mtspr   \scratch,r0
 246
 247        std     r10,\paca_ex+EX_R10(r13);
 248        std     r11,\paca_ex+EX_R11(r13);
 249        ld      r10,_NIP(r1)
 250        ld      r11,_MSR(r1)
 251        ld      r0,GPR0(r1)
 252        ld      r1,GPR1(r1)
 253        mtspr   \srr0,r10
 254        mtspr   \srr1,r11
 255        ld      r10,\paca_ex+EX_R10(r13)
 256        ld      r11,\paca_ex+EX_R11(r13)
 257        mfspr   r13,\scratch
 258.endm
 259
 260ret_from_crit_except:
 261        ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
 262        rfci
 263
 264ret_from_mc_except:
 265        ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
 266        rfmci
 267
 268/* Exception prolog code for all exceptions */
 269#define EXCEPTION_PROLOG(n, intnum, type, addition)                         \
 270        mtspr   SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */   \
 271        mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
 272        std     r10,PACA_EX##type+EX_R10(r13);                              \
 273        std     r11,PACA_EX##type+EX_R11(r13);                              \
 274        mfcr    r10;                    /* save CR */                       \
 275        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
 276        DO_KVM  intnum,SPRN_##type##_SRR1;    /* KVM hook */                \
 277        stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 278        addition;                       /* additional code for that exc. */ \
 279        std     r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 280        type##_SET_KSTACK;              /* get special stack if necessary */\
 281        andi.   r10,r11,MSR_PR;         /* save stack pointer */            \
 282        beq     1f;                     /* branch around if supervisor */   \
 283        ld      r1,PACAKSAVE(r13);      /* get kernel stack coming from usr */\
 2841:      type##_BTB_FLUSH                \
 285        cmpdi   cr1,r1,0;               /* check if SP makes sense */       \
 286        bge-    cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
 287        mfspr   r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
 288
 289/* Exception type-specific macros */
 290#define GEN_SET_KSTACK                                                      \
 291        subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack */
 292#define SPRN_GEN_SRR0   SPRN_SRR0
 293#define SPRN_GEN_SRR1   SPRN_SRR1
 294
 295#define GDBELL_SET_KSTACK       GEN_SET_KSTACK
 296#define SPRN_GDBELL_SRR0        SPRN_GSRR0
 297#define SPRN_GDBELL_SRR1        SPRN_GSRR1
 298
 299#define CRIT_SET_KSTACK                                                     \
 300        ld      r1,PACA_CRIT_STACK(r13);                                    \
 301        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 302#define SPRN_CRIT_SRR0  SPRN_CSRR0
 303#define SPRN_CRIT_SRR1  SPRN_CSRR1
 304
 305#define DBG_SET_KSTACK                                                      \
 306        ld      r1,PACA_DBG_STACK(r13);                                     \
 307        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 308#define SPRN_DBG_SRR0   SPRN_DSRR0
 309#define SPRN_DBG_SRR1   SPRN_DSRR1
 310
 311#define MC_SET_KSTACK                                                       \
 312        ld      r1,PACA_MC_STACK(r13);                                      \
 313        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 314#define SPRN_MC_SRR0    SPRN_MCSRR0
 315#define SPRN_MC_SRR1    SPRN_MCSRR1
 316
 317#ifdef CONFIG_PPC_FSL_BOOK3E
 318#define GEN_BTB_FLUSH                   \
 319        START_BTB_FLUSH_SECTION         \
 320                beq 1f;                 \
 321                BTB_FLUSH(r10)                  \
 322                1:              \
 323        END_BTB_FLUSH_SECTION
 324
 325#define CRIT_BTB_FLUSH                  \
 326        START_BTB_FLUSH_SECTION         \
 327                BTB_FLUSH(r10)          \
 328        END_BTB_FLUSH_SECTION
 329
 330#define DBG_BTB_FLUSH CRIT_BTB_FLUSH
 331#define MC_BTB_FLUSH CRIT_BTB_FLUSH
 332#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
 333#else
 334#define GEN_BTB_FLUSH
 335#define CRIT_BTB_FLUSH
 336#define DBG_BTB_FLUSH
 337#define MC_BTB_FLUSH
 338#define GDBELL_BTB_FLUSH
 339#endif
 340
 341#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)                        \
 342        EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
 343
 344#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)                          \
 345        EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
 346
 347#define DBG_EXCEPTION_PROLOG(n, intnum, addition)                           \
 348        EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
 349
 350#define MC_EXCEPTION_PROLOG(n, intnum, addition)                            \
 351        EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
 352
 353#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)                        \
 354        EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 355
 356/* Variants of the "addition" argument for the prolog
 357 */
 358#define PROLOG_ADDITION_NONE_GEN(n)
 359#define PROLOG_ADDITION_NONE_GDBELL(n)
 360#define PROLOG_ADDITION_NONE_CRIT(n)
 361#define PROLOG_ADDITION_NONE_DBG(n)
 362#define PROLOG_ADDITION_NONE_MC(n)
 363
 364#define PROLOG_ADDITION_MASKABLE_GEN(n)                                     \
 365        lbz     r10,PACAIRQSOFTMASK(r13);       /* are irqs soft-masked? */ \
 366        andi.   r10,r10,IRQS_DISABLED;  /* yes -> go out of line */ \
 367        bne     masked_interrupt_book3e_##n
 368
 369#define PROLOG_ADDITION_2REGS_GEN(n)                                        \
 370        std     r14,PACA_EXGEN+EX_R14(r13);                                 \
 371        std     r15,PACA_EXGEN+EX_R15(r13)
 372
 373#define PROLOG_ADDITION_1REG_GEN(n)                                         \
 374        std     r14,PACA_EXGEN+EX_R14(r13);
 375
 376#define PROLOG_ADDITION_2REGS_CRIT(n)                                       \
 377        std     r14,PACA_EXCRIT+EX_R14(r13);                                \
 378        std     r15,PACA_EXCRIT+EX_R15(r13)
 379
 380#define PROLOG_ADDITION_2REGS_DBG(n)                                        \
 381        std     r14,PACA_EXDBG+EX_R14(r13);                                 \
 382        std     r15,PACA_EXDBG+EX_R15(r13)
 383
 384#define PROLOG_ADDITION_2REGS_MC(n)                                         \
 385        std     r14,PACA_EXMC+EX_R14(r13);                                  \
 386        std     r15,PACA_EXMC+EX_R15(r13)
 387
 388
 389/* Core exception code for all exceptions except TLB misses. */
 390#define EXCEPTION_COMMON_LVL(n, scratch, excf)                              \
 391exc_##n##_common:                                                           \
 392        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
 393        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
 394        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
 395        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
 396        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
 397        std     r10,_NIP(r1);           /* save SRR0 to stackframe */       \
 398        std     r11,_MSR(r1);           /* save SRR1 to stackframe */       \
 399        beq     2f;                     /* if from kernel mode */           \
 400        ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */  \
 4012:      ld      r3,excf+EX_R10(r13);    /* get back r10 */                  \
 402        ld      r4,excf+EX_R11(r13);    /* get back r11 */                  \
 403        mfspr   r5,scratch;             /* get back r13 */                  \
 404        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
 405        ld      r2,PACATOC(r13);        /* get kernel TOC into r2 */        \
 406        mflr    r6;                     /* save LR in stackframe */         \
 407        mfctr   r7;                     /* save CTR in stackframe */        \
 408        mfspr   r8,SPRN_XER;            /* save XER in stackframe */        \
 409        ld      r9,excf+EX_R1(r13);     /* load orig r1 back from PACA */   \
 410        lwz     r10,excf+EX_CR(r13);    /* load orig CR back from PACA  */  \
 411        lbz     r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */       \
 412        ld      r12,exception_marker@toc(r2);                               \
 413        li      r0,0;                                                       \
 414        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
 415        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
 416        std     r5,GPR13(r1);           /* save it to stackframe */         \
 417        std     r6,_LINK(r1);                                               \
 418        std     r7,_CTR(r1);                                                \
 419        std     r8,_XER(r1);                                                \
 420        li      r3,(n)+1;               /* indicate partial regs in trap */ \
 421        std     r9,0(r1);               /* store stack frame back link */   \
 422        std     r10,_CCR(r1);           /* store orig CR in stackframe */   \
 423        std     r9,GPR1(r1);            /* store stack frame back link */   \
 424        std     r11,SOFTE(r1);          /* and save it to stackframe */     \
 425        std     r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */       \
 426        std     r3,_TRAP(r1);           /* set trap number              */  \
 427        std     r0,RESULT(r1);          /* clear regs->result */
 428
 429#define EXCEPTION_COMMON(n) \
 430        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
 431#define EXCEPTION_COMMON_CRIT(n) \
 432        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
 433#define EXCEPTION_COMMON_MC(n) \
 434        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
 435#define EXCEPTION_COMMON_DBG(n) \
 436        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
 437
 438/*
 439 * This is meant for exceptions that don't immediately hard-enable.  We
 440 * set a bit in paca->irq_happened to ensure that a subsequent call to
 441 * arch_local_irq_restore() will properly hard-enable and avoid the
 442 * fast-path, and then reconcile irq state.
 443 */
 444#define INTS_DISABLE    RECONCILE_IRQ_STATE(r3,r4)
 445
 446/*
 447 * This is called by exceptions that don't use INTS_DISABLE (that did not
 448 * touch irq indicators in the PACA).  This will restore MSR:EE to it's
 449 * previous value
 450 *
 451 * XXX In the long run, we may want to open-code it in order to separate the
 452 *     load from the wrtee, thus limiting the latency caused by the dependency
 453 *     but at this point, I'll favor code clarity until we have a near to final
 454 *     implementation
 455 */
 456#define INTS_RESTORE_HARD                                                   \
 457        ld      r11,_MSR(r1);                                               \
 458        wrtee   r11;
 459
 460/* XXX FIXME: Restore r14/r15 when necessary */
 461#define BAD_STACK_TRAMPOLINE(n)                                             \
 462exc_##n##_bad_stack:                                                        \
 463        li      r1,(n);                 /* get exception number */          \
 464        sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
 465        b       bad_stack_book3e;       /* bad stack error */
 466
 467/* WARNING: If you change the layout of this stub, make sure you check
 468        *   the debug exception handler which handles single stepping
 469        *   into exceptions from userspace, and the MM code in
 470        *   arch/powerpc/mm/tlb_nohash.c which patches the branch here
 471        *   and would need to be updated if that branch is moved
 472        */
 473#define EXCEPTION_STUB(loc, label)                                      \
 474        . = interrupt_base_book3e + loc;                                \
 475        nop;    /* To make debug interrupts happy */                    \
 476        b       exc_##label##_book3e;
 477
 478#define ACK_NONE(r)
 479#define ACK_DEC(r)                                                      \
 480        lis     r,TSR_DIS@h;                                            \
 481        mtspr   SPRN_TSR,r
 482#define ACK_FIT(r)                                                      \
 483        lis     r,TSR_FIS@h;                                            \
 484        mtspr   SPRN_TSR,r
 485
 486/* Used by asynchronous interrupt that may happen in the idle loop.
 487 *
 488 * This check if the thread was in the idle loop, and if yes, returns
 489 * to the caller rather than the PC. This is to avoid a race if
 490 * interrupts happen before the wait instruction.
 491 */
 492#define CHECK_NAPPING()                                                 \
 493        ld      r11, PACA_THREAD_INFO(r13);                             \
 494        ld      r10,TI_LOCAL_FLAGS(r11);                                \
 495        andi.   r9,r10,_TLF_NAPPING;                                    \
 496        beq+    1f;                                                     \
 497        ld      r8,_LINK(r1);                                           \
 498        rlwinm  r7,r10,0,~_TLF_NAPPING;                                 \
 499        std     r8,_NIP(r1);                                            \
 500        std     r7,TI_LOCAL_FLAGS(r11);                                 \
 5011:
 502
 503
 504#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)           \
 505        START_EXCEPTION(label);                                         \
 506        NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
 507        EXCEPTION_COMMON(trapnum)                                       \
 508        INTS_DISABLE;                                                   \
 509        ack(r8);                                                        \
 510        CHECK_NAPPING();                                                \
 511        addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
 512        bl      hdlr;                                                   \
 513        b       ret_from_except_lite;
 514
 515/* This value is used to mark exception frames on the stack. */
 516        .section        ".toc","aw"
 517exception_marker:
 518        .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
 519
 520
 521/*
 522 * And here we have the exception vectors !
 523 */
 524
 525        .text
 526        .balign 0x1000
 527        .globl interrupt_base_book3e
 528interrupt_base_book3e:                                  /* fake trap */
 529        EXCEPTION_STUB(0x000, machine_check)
 530        EXCEPTION_STUB(0x020, critical_input)           /* 0x0100 */
 531        EXCEPTION_STUB(0x040, debug_crit)               /* 0x0d00 */
 532        EXCEPTION_STUB(0x060, data_storage)             /* 0x0300 */
 533        EXCEPTION_STUB(0x080, instruction_storage)      /* 0x0400 */
 534        EXCEPTION_STUB(0x0a0, external_input)           /* 0x0500 */
 535        EXCEPTION_STUB(0x0c0, alignment)                /* 0x0600 */
 536        EXCEPTION_STUB(0x0e0, program)                  /* 0x0700 */
 537        EXCEPTION_STUB(0x100, fp_unavailable)           /* 0x0800 */
 538        EXCEPTION_STUB(0x120, system_call)              /* 0x0c00 */
 539        EXCEPTION_STUB(0x140, ap_unavailable)           /* 0x0f20 */
 540        EXCEPTION_STUB(0x160, decrementer)              /* 0x0900 */
 541        EXCEPTION_STUB(0x180, fixed_interval)           /* 0x0980 */
 542        EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
 543        EXCEPTION_STUB(0x1c0, data_tlb_miss)
 544        EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
 545        EXCEPTION_STUB(0x200, altivec_unavailable)
 546        EXCEPTION_STUB(0x220, altivec_assist)
 547        EXCEPTION_STUB(0x260, perfmon)
 548        EXCEPTION_STUB(0x280, doorbell)
 549        EXCEPTION_STUB(0x2a0, doorbell_crit)
 550        EXCEPTION_STUB(0x2c0, guest_doorbell)
 551        EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
 552        EXCEPTION_STUB(0x300, hypercall)
 553        EXCEPTION_STUB(0x320, ehpriv)
 554        EXCEPTION_STUB(0x340, lrat_error)
 555
 556        .globl __end_interrupts
 557__end_interrupts:
 558
 559/* Critical Input Interrupt */
 560        START_EXCEPTION(critical_input);
 561        CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
 562                              PROLOG_ADDITION_NONE)
 563        EXCEPTION_COMMON_CRIT(0x100)
 564        bl      save_nvgprs
 565        bl      special_reg_save
 566        CHECK_NAPPING();
 567        addi    r3,r1,STACK_FRAME_OVERHEAD
 568        bl      unknown_exception
 569        b       ret_from_crit_except
 570
 571/* Machine Check Interrupt */
 572        START_EXCEPTION(machine_check);
 573        MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
 574                            PROLOG_ADDITION_NONE)
 575        EXCEPTION_COMMON_MC(0x000)
 576        bl      save_nvgprs
 577        bl      special_reg_save
 578        CHECK_NAPPING();
 579        addi    r3,r1,STACK_FRAME_OVERHEAD
 580        bl      machine_check_exception
 581        b       ret_from_mc_except
 582
 583/* Data Storage Interrupt */
 584        START_EXCEPTION(data_storage)
 585        NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
 586                                PROLOG_ADDITION_2REGS)
 587        mfspr   r14,SPRN_DEAR
 588        mfspr   r15,SPRN_ESR
 589        EXCEPTION_COMMON(0x300)
 590        INTS_DISABLE
 591        b       storage_fault_common
 592
 593/* Instruction Storage Interrupt */
 594        START_EXCEPTION(instruction_storage);
 595        NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
 596                                PROLOG_ADDITION_2REGS)
 597        li      r15,0
 598        mr      r14,r10
 599        EXCEPTION_COMMON(0x400)
 600        INTS_DISABLE
 601        b       storage_fault_common
 602
 603/* External Input Interrupt */
 604        MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
 605                           external_input, do_IRQ, ACK_NONE)
 606
 607/* Alignment */
 608        START_EXCEPTION(alignment);
 609        NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
 610                                PROLOG_ADDITION_2REGS)
 611        mfspr   r14,SPRN_DEAR
 612        mfspr   r15,SPRN_ESR
 613        EXCEPTION_COMMON(0x600)
 614        b       alignment_more  /* no room, go out of line */
 615
 616/* Program Interrupt */
 617        START_EXCEPTION(program);
 618        NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
 619                                PROLOG_ADDITION_1REG)
 620        mfspr   r14,SPRN_ESR
 621        EXCEPTION_COMMON(0x700)
 622        INTS_DISABLE
 623        std     r14,_DSISR(r1)
 624        addi    r3,r1,STACK_FRAME_OVERHEAD
 625        ld      r14,PACA_EXGEN+EX_R14(r13)
 626        bl      save_nvgprs
 627        bl      program_check_exception
 628        b       ret_from_except
 629
 630/* Floating Point Unavailable Interrupt */
 631        START_EXCEPTION(fp_unavailable);
 632        NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
 633                                PROLOG_ADDITION_NONE)
 634        /* we can probably do a shorter exception entry for that one... */
 635        EXCEPTION_COMMON(0x800)
 636        ld      r12,_MSR(r1)
 637        andi.   r0,r12,MSR_PR;
 638        beq-    1f
 639        bl      load_up_fpu
 640        b       fast_exception_return
 6411:      INTS_DISABLE
 642        bl      save_nvgprs
 643        addi    r3,r1,STACK_FRAME_OVERHEAD
 644        bl      kernel_fp_unavailable_exception
 645        b       ret_from_except
 646
 647/* Altivec Unavailable Interrupt */
 648        START_EXCEPTION(altivec_unavailable);
 649        NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
 650                                PROLOG_ADDITION_NONE)
 651        /* we can probably do a shorter exception entry for that one... */
 652        EXCEPTION_COMMON(0x200)
 653#ifdef CONFIG_ALTIVEC
 654BEGIN_FTR_SECTION
 655        ld      r12,_MSR(r1)
 656        andi.   r0,r12,MSR_PR;
 657        beq-    1f
 658        bl      load_up_altivec
 659        b       fast_exception_return
 6601:
 661END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 662#endif
 663        INTS_DISABLE
 664        bl      save_nvgprs
 665        addi    r3,r1,STACK_FRAME_OVERHEAD
 666        bl      altivec_unavailable_exception
 667        b       ret_from_except
 668
 669/* AltiVec Assist */
 670        START_EXCEPTION(altivec_assist);
 671        NORMAL_EXCEPTION_PROLOG(0x220,
 672                                BOOKE_INTERRUPT_ALTIVEC_ASSIST,
 673                                PROLOG_ADDITION_NONE)
 674        EXCEPTION_COMMON(0x220)
 675        INTS_DISABLE
 676        bl      save_nvgprs
 677        addi    r3,r1,STACK_FRAME_OVERHEAD
 678#ifdef CONFIG_ALTIVEC
 679BEGIN_FTR_SECTION
 680        bl      altivec_assist_exception
 681END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 682#else
 683        bl      unknown_exception
 684#endif
 685        b       ret_from_except
 686
 687
 688/* Decrementer Interrupt */
 689        MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
 690                           decrementer, timer_interrupt, ACK_DEC)
 691
 692/* Fixed Interval Timer Interrupt */
 693        MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
 694                           fixed_interval, unknown_exception, ACK_FIT)
 695
 696/* Watchdog Timer Interrupt */
 697        START_EXCEPTION(watchdog);
 698        CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
 699                              PROLOG_ADDITION_NONE)
 700        EXCEPTION_COMMON_CRIT(0x9f0)
 701        bl      save_nvgprs
 702        bl      special_reg_save
 703        CHECK_NAPPING();
 704        addi    r3,r1,STACK_FRAME_OVERHEAD
 705#ifdef CONFIG_BOOKE_WDT
 706        bl      WatchdogException
 707#else
 708        bl      unknown_exception
 709#endif
 710        b       ret_from_crit_except
 711
 712/* System Call Interrupt */
 713        START_EXCEPTION(system_call)
 714        mr      r9,r13                  /* keep a copy of userland r13 */
 715        mfspr   r11,SPRN_SRR0           /* get return address */
 716        mfspr   r12,SPRN_SRR1           /* get previous MSR */
 717        mfspr   r13,SPRN_SPRG_PACA      /* get our PACA */
 718        b       system_call_common
 719
 720/* Auxiliary Processor Unavailable Interrupt */
 721        START_EXCEPTION(ap_unavailable);
 722        NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
 723                                PROLOG_ADDITION_NONE)
 724        EXCEPTION_COMMON(0xf20)
 725        INTS_DISABLE
 726        bl      save_nvgprs
 727        addi    r3,r1,STACK_FRAME_OVERHEAD
 728        bl      unknown_exception
 729        b       ret_from_except
 730
 731/* Debug exception as a critical interrupt*/
 732        START_EXCEPTION(debug_crit);
 733        CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 734                              PROLOG_ADDITION_2REGS)
 735
 736        /*
 737         * If there is a single step or branch-taken exception in an
 738         * exception entry sequence, it was probably meant to apply to
 739         * the code where the exception occurred (since exception entry
 740         * doesn't turn off DE automatically).  We simulate the effect
 741         * of turning off DE on entry to an exception handler by turning
 742         * off DE in the CSRR1 value and clearing the debug status.
 743         */
 744
 745        mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
 746        andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
 747        beq+    1f
 748
 749#ifdef CONFIG_RELOCATABLE
 750        ld      r15,PACATOC(r13)
 751        ld      r14,interrupt_base_book3e@got(r15)
 752        ld      r15,__end_interrupts@got(r15)
 753#else
 754        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
 755        LOAD_REG_IMMEDIATE(r15,__end_interrupts)
 756#endif
 757        cmpld   cr0,r10,r14
 758        cmpld   cr1,r10,r15
 759        blt+    cr0,1f
 760        bge+    cr1,1f
 761
 762        /* here it looks like we got an inappropriate debug exception. */
 763        lis     r14,(DBSR_IC|DBSR_BT)@h         /* clear the event */
 764        rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the CSRR1 value */
 765        mtspr   SPRN_DBSR,r14
 766        mtspr   SPRN_CSRR1,r11
 767        lwz     r10,PACA_EXCRIT+EX_CR(r13)      /* restore registers */
 768        ld      r1,PACA_EXCRIT+EX_R1(r13)
 769        ld      r14,PACA_EXCRIT+EX_R14(r13)
 770        ld      r15,PACA_EXCRIT+EX_R15(r13)
 771        mtcr    r10
 772        ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
 773        ld      r11,PACA_EXCRIT+EX_R11(r13)
 774        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
 775        rfci
 776
 777        /* Normal debug exception */
 778        /* XXX We only handle coming from userspace for now since we can't
 779         *     quite save properly an interrupted kernel state yet
 780         */
 7811:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
 782        beq     kernel_dbg_exc;         /* if from kernel mode */
 783
 784        /* Now we mash up things to make it look like we are coming on a
 785         * normal exception
 786         */
 787        mfspr   r14,SPRN_DBSR
 788        EXCEPTION_COMMON_CRIT(0xd00)
 789        std     r14,_DSISR(r1)
 790        addi    r3,r1,STACK_FRAME_OVERHEAD
 791        mr      r4,r14
 792        ld      r14,PACA_EXCRIT+EX_R14(r13)
 793        ld      r15,PACA_EXCRIT+EX_R15(r13)
 794        bl      save_nvgprs
 795        bl      DebugException
 796        b       ret_from_except
 797
 798kernel_dbg_exc:
 799        b       .       /* NYI */
 800
 801/* Debug exception as a debug interrupt*/
 802        START_EXCEPTION(debug_debug);
 803        DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 804                                                 PROLOG_ADDITION_2REGS)
 805
 806        /*
 807         * If there is a single step or branch-taken exception in an
 808         * exception entry sequence, it was probably meant to apply to
 809         * the code where the exception occurred (since exception entry
 810         * doesn't turn off DE automatically).  We simulate the effect
 811         * of turning off DE on entry to an exception handler by turning
 812         * off DE in the DSRR1 value and clearing the debug status.
 813         */
 814
 815        mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
 816        andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
 817        beq+    1f
 818
 819#ifdef CONFIG_RELOCATABLE
 820        ld      r15,PACATOC(r13)
 821        ld      r14,interrupt_base_book3e@got(r15)
 822        ld      r15,__end_interrupts@got(r15)
 823#else
 824        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
 825        LOAD_REG_IMMEDIATE(r15,__end_interrupts)
 826#endif
 827        cmpld   cr0,r10,r14
 828        cmpld   cr1,r10,r15
 829        blt+    cr0,1f
 830        bge+    cr1,1f
 831
 832        /* here it looks like we got an inappropriate debug exception. */
 833        lis     r14,(DBSR_IC|DBSR_BT)@h         /* clear the event */
 834        rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the DSRR1 value */
 835        mtspr   SPRN_DBSR,r14
 836        mtspr   SPRN_DSRR1,r11
 837        lwz     r10,PACA_EXDBG+EX_CR(r13)       /* restore registers */
 838        ld      r1,PACA_EXDBG+EX_R1(r13)
 839        ld      r14,PACA_EXDBG+EX_R14(r13)
 840        ld      r15,PACA_EXDBG+EX_R15(r13)
 841        mtcr    r10
 842        ld      r10,PACA_EXDBG+EX_R10(r13)      /* restore registers */
 843        ld      r11,PACA_EXDBG+EX_R11(r13)
 844        mfspr   r13,SPRN_SPRG_DBG_SCRATCH
 845        rfdi
 846
 847        /* Normal debug exception */
 848        /* XXX We only handle coming from userspace for now since we can't
 849         *     quite save properly an interrupted kernel state yet
 850         */
 8511:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
 852        beq     kernel_dbg_exc;         /* if from kernel mode */
 853
 854        /* Now we mash up things to make it look like we are coming on a
 855         * normal exception
 856         */
 857        mfspr   r14,SPRN_DBSR
 858        EXCEPTION_COMMON_DBG(0xd08)
 859        INTS_DISABLE
 860        std     r14,_DSISR(r1)
 861        addi    r3,r1,STACK_FRAME_OVERHEAD
 862        mr      r4,r14
 863        ld      r14,PACA_EXDBG+EX_R14(r13)
 864        ld      r15,PACA_EXDBG+EX_R15(r13)
 865        bl      save_nvgprs
 866        bl      DebugException
 867        b       ret_from_except
 868
 869        START_EXCEPTION(perfmon);
 870        NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
 871                                PROLOG_ADDITION_NONE)
 872        EXCEPTION_COMMON(0x260)
 873        INTS_DISABLE
 874        CHECK_NAPPING()
 875        addi    r3,r1,STACK_FRAME_OVERHEAD
 876        bl      performance_monitor_exception
 877        b       ret_from_except_lite
 878
 879/* Doorbell interrupt */
 880        MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
 881                           doorbell, doorbell_exception, ACK_NONE)
 882
 883/* Doorbell critical Interrupt */
 884        START_EXCEPTION(doorbell_crit);
 885        CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
 886                              PROLOG_ADDITION_NONE)
 887        EXCEPTION_COMMON_CRIT(0x2a0)
 888        bl      save_nvgprs
 889        bl      special_reg_save
 890        CHECK_NAPPING();
 891        addi    r3,r1,STACK_FRAME_OVERHEAD
 892        bl      unknown_exception
 893        b       ret_from_crit_except
 894
 895/*
 896 *      Guest doorbell interrupt
 897 *      This general exception use GSRRx save/restore registers
 898 */
 899        START_EXCEPTION(guest_doorbell);
 900        GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
 901                                PROLOG_ADDITION_NONE)
 902        EXCEPTION_COMMON(0x2c0)
 903        addi    r3,r1,STACK_FRAME_OVERHEAD
 904        bl      save_nvgprs
 905        INTS_RESTORE_HARD
 906        bl      unknown_exception
 907        b       ret_from_except
 908
 909/* Guest Doorbell critical Interrupt */
 910        START_EXCEPTION(guest_doorbell_crit);
 911        CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
 912                              PROLOG_ADDITION_NONE)
 913        EXCEPTION_COMMON_CRIT(0x2e0)
 914        bl      save_nvgprs
 915        bl      special_reg_save
 916        CHECK_NAPPING();
 917        addi    r3,r1,STACK_FRAME_OVERHEAD
 918        bl      unknown_exception
 919        b       ret_from_crit_except
 920
 921/* Hypervisor call */
 922        START_EXCEPTION(hypercall);
 923        NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
 924                                PROLOG_ADDITION_NONE)
 925        EXCEPTION_COMMON(0x310)
 926        addi    r3,r1,STACK_FRAME_OVERHEAD
 927        bl      save_nvgprs
 928        INTS_RESTORE_HARD
 929        bl      unknown_exception
 930        b       ret_from_except
 931
 932/* Embedded Hypervisor priviledged  */
 933        START_EXCEPTION(ehpriv);
 934        NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
 935                                PROLOG_ADDITION_NONE)
 936        EXCEPTION_COMMON(0x320)
 937        addi    r3,r1,STACK_FRAME_OVERHEAD
 938        bl      save_nvgprs
 939        INTS_RESTORE_HARD
 940        bl      unknown_exception
 941        b       ret_from_except
 942
 943/* LRAT Error interrupt */
 944        START_EXCEPTION(lrat_error);
 945        NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
 946                                PROLOG_ADDITION_NONE)
 947        EXCEPTION_COMMON(0x340)
 948        addi    r3,r1,STACK_FRAME_OVERHEAD
 949        bl      save_nvgprs
 950        INTS_RESTORE_HARD
 951        bl      unknown_exception
 952        b       ret_from_except
 953
 954/*
 955 * An interrupt came in while soft-disabled; We mark paca->irq_happened
 956 * accordingly and if the interrupt is level sensitive, we hard disable
 957 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
 958 * keep these in synch.
 959 */
 960
 961.macro masked_interrupt_book3e paca_irq full_mask
 962        lbz     r10,PACAIRQHAPPENED(r13)
 963        .if \full_mask == 1
 964        ori     r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
 965        .else
 966        ori     r10,r10,\paca_irq
 967        .endif
 968        stb     r10,PACAIRQHAPPENED(r13)
 969
 970        .if \full_mask == 1
 971        rldicl  r10,r11,48,1            /* clear MSR_EE */
 972        rotldi  r11,r10,16
 973        mtspr   SPRN_SRR1,r11
 974        .endif
 975
 976        lwz     r11,PACA_EXGEN+EX_CR(r13)
 977        mtcr    r11
 978        ld      r10,PACA_EXGEN+EX_R10(r13)
 979        ld      r11,PACA_EXGEN+EX_R11(r13)
 980        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
 981        rfi
 982        b       .
 983.endm
 984
 985masked_interrupt_book3e_0x500:
 986        // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
 987        masked_interrupt_book3e PACA_IRQ_EE 1
 988
 989masked_interrupt_book3e_0x900:
 990        ACK_DEC(r10);
 991        masked_interrupt_book3e PACA_IRQ_DEC 0
 992
 993masked_interrupt_book3e_0x980:
 994        ACK_FIT(r10);
 995        masked_interrupt_book3e PACA_IRQ_DEC 0
 996
 997masked_interrupt_book3e_0x280:
 998masked_interrupt_book3e_0x2c0:
 999        masked_interrupt_book3e PACA_IRQ_DBELL 0
1000

1001/*
1002 * Called from arch_local_irq_enable when an interrupt needs
1003 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
1004 * to indicate the kind of interrupt. MSR:EE is already off.
1005 * We generate a stackframe like if a real interrupt had happened.
1006 *
1007 * Note: While MSR:EE is off, we need to make sure that _MSR
1008 * in the generated frame has EE set to 1 or the exception
1009 * handler will not properly re-enable them.
1010 */
1011_GLOBAL(__replay_interrupt)
1012        /* We are going to jump to the exception common code which
1013         * will retrieve various register values from the PACA which
1014         * we don't give a damn about.
1015         */
1016        mflr    r10
1017        mfmsr   r11
1018        mfcr    r4
1019        mtspr   SPRN_SPRG_GEN_SCRATCH,r13;
1020        std     r1,PACA_EXGEN+EX_R1(r13);
1021        stw     r4,PACA_EXGEN+EX_CR(r13);
1022        ori     r11,r11,MSR_EE
1023        subi    r1,r1,INT_FRAME_SIZE;
1024        cmpwi   cr0,r3,0x500
1025        beq     exc_0x500_common
1026        cmpwi   cr0,r3,0x900
1027        beq     exc_0x900_common
1028        cmpwi   cr0,r3,0x280
1029        beq     exc_0x280_common
1030        blr
1031
1032
1033/*
1034 * This is called from 0x300 and 0x400 handlers after the prologs with
1035 * r14 and r15 containing the fault address and error code, with the
1036 * original values stashed away in the PACA
1037 */
1038storage_fault_common:
1039        std     r14,_DAR(r1)
1040        std     r15,_DSISR(r1)
1041        addi    r3,r1,STACK_FRAME_OVERHEAD
1042        mr      r4,r14
1043        mr      r5,r15
1044        ld      r14,PACA_EXGEN+EX_R14(r13)
1045        ld      r15,PACA_EXGEN+EX_R15(r13)
1046        bl      do_page_fault
1047        cmpdi   r3,0
1048        bne-    1f
1049        b       ret_from_except_lite
10501:      bl      save_nvgprs
1051        mr      r5,r3
1052        addi    r3,r1,STACK_FRAME_OVERHEAD
1053        ld      r4,_DAR(r1)
1054        bl      bad_page_fault
1055        b       ret_from_except
1056
1057/*
1058 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1059 * continues here.
1060 */
1061alignment_more:
1062        std     r14,_DAR(r1)
1063        std     r15,_DSISR(r1)
1064        addi    r3,r1,STACK_FRAME_OVERHEAD
1065        ld      r14,PACA_EXGEN+EX_R14(r13)
1066        ld      r15,PACA_EXGEN+EX_R15(r13)
1067        bl      save_nvgprs
1068        INTS_RESTORE_HARD
1069        bl      alignment_exception
1070        b       ret_from_except
1071
1072/*
1073 * We branch here from entry_64.S for the last stage of the exception
1074 * return code path. MSR:EE is expected to be off at that point
1075 */
1076_GLOBAL(exception_return_book3e)
1077        b       1f
1078
1079/* This is the return from load_up_fpu fast path which could do with
1080 * less GPR restores in fact, but for now we have a single return path
1081 */
1082        .globl fast_exception_return
1083fast_exception_return:
1084        wrteei  0
10851:      mr      r0,r13
1086        ld      r10,_MSR(r1)
1087        REST_4GPRS(2, r1)
1088        andi.   r6,r10,MSR_PR
1089        REST_2GPRS(6, r1)
1090        beq     1f
1091        ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
1092        ld      r0,GPR13(r1)
1093
10941:      stdcx.  r0,0,r1         /* to clear the reservation */
1095
1096        ld      r8,_CCR(r1)
1097        ld      r9,_LINK(r1)
1098        ld      r10,_CTR(r1)
1099        ld      r11,_XER(r1)
1100        mtcr    r8
1101        mtlr    r9
1102        mtctr   r10
1103        mtxer   r11
1104        REST_2GPRS(8, r1)
1105        ld      r10,GPR10(r1)
1106        ld      r11,GPR11(r1)
1107        ld      r12,GPR12(r1)
1108        mtspr   SPRN_SPRG_GEN_SCRATCH,r0
1109
1110        std     r10,PACA_EXGEN+EX_R10(r13);
1111        std     r11,PACA_EXGEN+EX_R11(r13);
1112        ld      r10,_NIP(r1)
1113        ld      r11,_MSR(r1)
1114        ld      r0,GPR0(r1)
1115        ld      r1,GPR1(r1)
1116        mtspr   SPRN_SRR0,r10
1117        mtspr   SPRN_SRR1,r11
1118        ld      r10,PACA_EXGEN+EX_R10(r13)
1119        ld      r11,PACA_EXGEN+EX_R11(r13)
1120        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
1121        rfi
1122
1123/*
1124 * Trampolines used when spotting a bad kernel stack pointer in
1125 * the exception entry code.
1126 *
1127 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1128 * index around, etc... to handle crit & mcheck
1129 */
1130BAD_STACK_TRAMPOLINE(0x000)
1131BAD_STACK_TRAMPOLINE(0x100)
1132BAD_STACK_TRAMPOLINE(0x200)
1133BAD_STACK_TRAMPOLINE(0x220)
1134BAD_STACK_TRAMPOLINE(0x260)
1135BAD_STACK_TRAMPOLINE(0x280)
1136BAD_STACK_TRAMPOLINE(0x2a0)
1137BAD_STACK_TRAMPOLINE(0x2c0)
1138BAD_STACK_TRAMPOLINE(0x2e0)
1139BAD_STACK_TRAMPOLINE(0x300)
1140BAD_STACK_TRAMPOLINE(0x310)
1141BAD_STACK_TRAMPOLINE(0x320)
1142BAD_STACK_TRAMPOLINE(0x340)
1143BAD_STACK_TRAMPOLINE(0x400)
1144BAD_STACK_TRAMPOLINE(0x500)
1145BAD_STACK_TRAMPOLINE(0x600)
1146BAD_STACK_TRAMPOLINE(0x700)
1147BAD_STACK_TRAMPOLINE(0x800)
1148BAD_STACK_TRAMPOLINE(0x900)
1149BAD_STACK_TRAMPOLINE(0x980)
1150BAD_STACK_TRAMPOLINE(0x9f0)
1151BAD_STACK_TRAMPOLINE(0xa00)
1152BAD_STACK_TRAMPOLINE(0xb00)
1153BAD_STACK_TRAMPOLINE(0xc00)
1154BAD_STACK_TRAMPOLINE(0xd00)
1155BAD_STACK_TRAMPOLINE(0xd08)
1156BAD_STACK_TRAMPOLINE(0xe00)
1157BAD_STACK_TRAMPOLINE(0xf00)
1158BAD_STACK_TRAMPOLINE(0xf20)
1159
1160        .globl  bad_stack_book3e
1161bad_stack_book3e:
1162        /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1163        mfspr   r10,SPRN_SRR0;            /* read SRR0 before touching stack */
1164        ld      r1,PACAEMERGSP(r13)
1165        subi    r1,r1,64+INT_FRAME_SIZE
1166        std     r10,_NIP(r1)
1167        std     r11,_MSR(r1)
1168        ld      r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1169        lwz     r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1170        std     r10,GPR1(r1)
1171        std     r11,_CCR(r1)
1172        mfspr   r10,SPRN_DEAR
1173        mfspr   r11,SPRN_ESR
1174        std     r10,_DAR(r1)
1175        std     r11,_DSISR(r1)
1176        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
1177        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
1178        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
1179        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
1180        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
1181        ld      r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */                \
1182        ld      r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */                \
1183        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1184        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
1185        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
1186        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
1187        std     r5,GPR13(r1);           /* save it to stackframe */         \
1188        mflr    r10
1189        mfctr   r11
1190        mfxer   r12
1191        std     r10,_LINK(r1)
1192        std     r11,_CTR(r1)
1193        std     r12,_XER(r1)
1194        SAVE_10GPRS(14,r1)
1195        SAVE_8GPRS(24,r1)
1196        lhz     r12,PACA_TRAP_SAVE(r13)
1197        std     r12,_TRAP(r1)
1198        addi    r11,r1,INT_FRAME_SIZE
1199        std     r11,0(r1)
1200        li      r12,0
1201        std     r12,0(r11)
1202        ld      r2,PACATOC(r13)
12031:      addi    r3,r1,STACK_FRAME_OVERHEAD
1204        bl      kernel_bad_stack
1205        b       1b
1206
1207/*
1208 * Setup the initial TLB for a core. This current implementation
1209 * assume that whatever we are running off will not conflict with
1210 * the new mapping at PAGE_OFFSET.
1211 */
1212_GLOBAL(initial_tlb_book3e)
1213
1214        /* Look for the first TLB with IPROT set */
1215        mfspr   r4,SPRN_TLB0CFG
1216        andi.   r3,r4,TLBnCFG_IPROT
1217        lis     r3,MAS0_TLBSEL(0)@h
1218        bne     found_iprot
1219
1220        mfspr   r4,SPRN_TLB1CFG
1221        andi.   r3,r4,TLBnCFG_IPROT
1222        lis     r3,MAS0_TLBSEL(1)@h
1223        bne     found_iprot
1224
1225        mfspr   r4,SPRN_TLB2CFG
1226        andi.   r3,r4,TLBnCFG_IPROT
1227        lis     r3,MAS0_TLBSEL(2)@h
1228        bne     found_iprot
1229
1230        lis     r3,MAS0_TLBSEL(3)@h
1231        mfspr   r4,SPRN_TLB3CFG
1232        /* fall through */
1233
1234found_iprot:
1235        andi.   r5,r4,TLBnCFG_HES
1236        bne     have_hes
1237
1238        mflr    r8                              /* save LR */
1239/* 1. Find the index of the entry we're executing in
1240 *
1241 * r3 = MAS0_TLBSEL (for the iprot array)
1242 * r4 = SPRN_TLBnCFG
1243 */
1244        bl      invstr                          /* Find our address */
1245invstr: mflr    r6                              /* Make it accessible */
1246        mfmsr   r7
1247        rlwinm  r5,r7,27,31,31                  /* extract MSR[IS] */
1248        mfspr   r7,SPRN_PID
1249        slwi    r7,r7,16
1250        or      r7,r7,r5
1251        mtspr   SPRN_MAS6,r7
1252        tlbsx   0,r6                            /* search MSR[IS], SPID=PID */
1253
1254        mfspr   r3,SPRN_MAS0
1255        rlwinm  r5,r3,16,20,31                  /* Extract MAS0(Entry) */
1256
1257        mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
1258        oris    r7,r7,MAS1_IPROT@h
1259        mtspr   SPRN_MAS1,r7
1260        tlbwe
1261
1262/* 2. Invalidate all entries except the entry we're executing in
1263 *
1264 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1265 * r4 = SPRN_TLBnCFG
1266 * r5 = ESEL of entry we are running in
1267 */
1268        andi.   r4,r4,TLBnCFG_N_ENTRY           /* Extract # entries */
1269        li      r6,0                            /* Set Entry counter to 0 */
12701:      mr      r7,r3                           /* Set MAS0(TLBSEL) */
1271        rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
1272        mtspr   SPRN_MAS0,r7
1273        tlbre
1274        mfspr   r7,SPRN_MAS1
1275        rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
1276        cmpw    r5,r6
1277        beq     skpinv                          /* Dont update the current execution TLB */
1278        mtspr   SPRN_MAS1,r7
1279        tlbwe
1280        isync
1281skpinv: addi    r6,r6,1                         /* Increment */
1282        cmpw    r6,r4                           /* Are we done? */
1283        bne     1b                              /* If not, repeat */
1284
1285        /* Invalidate all TLBs */
1286        PPC_TLBILX_ALL(0,R0)
1287        sync
1288        isync
1289
1290/* 3. Setup a temp mapping and jump to it
1291 *
1292 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1293 * r5 = ESEL of entry we are running in
1294 */
1295        andi.   r7,r5,0x1       /* Find an entry not used and is non-zero */
1296        addi    r7,r7,0x1
1297        mr      r4,r3           /* Set MAS0(TLBSEL) = 1 */
1298        mtspr   SPRN_MAS0,r4
1299        tlbre
1300
1301        rlwimi  r4,r7,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r7) */
1302        mtspr   SPRN_MAS0,r4
1303
1304        mfspr   r7,SPRN_MAS1
1305        xori    r6,r7,MAS1_TS           /* Setup TMP mapping in the other Address space */
1306        mtspr   SPRN_MAS1,r6
1307
1308        tlbwe
1309
1310        mfmsr   r6
1311        xori    r6,r6,MSR_IS
1312        mtspr   SPRN_SRR1,r6
1313        bl      1f              /* Find our address */
13141:      mflr    r6
1315        addi    r6,r6,(2f - 1b)
1316        mtspr   SPRN_SRR0,r6
1317        rfi
13182:
1319
1320/* 4. Clear out PIDs & Search info
1321 *
1322 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1323 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1324 * r5 = MAS3
1325 */
1326        li      r6,0
1327        mtspr   SPRN_MAS6,r6
1328        mtspr   SPRN_PID,r6
1329
1330/* 5. Invalidate mapping we started in
1331 *
1332 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1333 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1334 * r5 = MAS3
1335 */
1336        mtspr   SPRN_MAS0,r3
1337        tlbre
1338        mfspr   r6,SPRN_MAS1
1339        rlwinm  r6,r6,0,2,31    /* clear IPROT and VALID */
1340        mtspr   SPRN_MAS1,r6
1341        tlbwe
1342        sync
1343        isync
1344
1345/*
1346 * The mapping only needs to be cache-coherent on SMP, except on
1347 * Freescale e500mc derivatives where it's also needed for coherent DMA.
1348 */
1349#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
1350#define M_IF_NEEDED     MAS2_M
1351#else
1352#define M_IF_NEEDED     0
1353#endif
1354
1355/* 6. Setup KERNELBASE mapping in TLB[0]
1356 *
1357 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1358 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1359 * r5 = MAS3
1360 */
1361        rlwinm  r3,r3,0,16,3    /* clear ESEL */
1362        mtspr   SPRN_MAS0,r3
1363        lis     r6,(MAS1_VALID|MAS1_IPROT)@h
1364        ori     r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1365        mtspr   SPRN_MAS1,r6
1366
1367        LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED)
1368        mtspr   SPRN_MAS2,r6
1369
1370        rlwinm  r5,r5,0,0,25
1371        ori     r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1372        mtspr   SPRN_MAS3,r5
1373        li      r5,-1
1374        rlwinm  r5,r5,0,0,25
1375
1376        tlbwe
1377
1378/* 7. Jump to KERNELBASE mapping
1379 *
1380 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1381 */
1382        /* Now we branch the new virtual address mapped by this entry */
1383        bl      1f              /* Find our address */
13841:      mflr    r6
1385        addi    r6,r6,(2f - 1b)
1386        tovirt(r6,r6)
1387        lis     r7,MSR_KERNEL@h
1388        ori     r7,r7,MSR_KERNEL@l
1389        mtspr   SPRN_SRR0,r6
1390        mtspr   SPRN_SRR1,r7
1391        rfi                             /* start execution out of TLB1[0] entry */
13922:
1393
1394/* 8. Clear out the temp mapping
1395 *
1396 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1397 */
1398        mtspr   SPRN_MAS0,r4
1399        tlbre
1400        mfspr   r5,SPRN_MAS1
1401        rlwinm  r5,r5,0,2,31    /* clear IPROT and VALID */
1402        mtspr   SPRN_MAS1,r5
1403        tlbwe
1404        sync
1405        isync
1406
1407        /* We translate LR and return */
1408        tovirt(r8,r8)
1409        mtlr    r8
1410        blr
1411
1412have_hes:
1413        /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1414         * kernel linear mapping. We also set MAS8 once for all here though
1415         * that will have to be made dependent on whether we are running under
1416         * a hypervisor I suppose.
1417         */
1418
1419        /* BEWARE, MAGIC
1420         * This code is called as an ordinary function on the boot CPU. But to
1421         * avoid duplication, this code is also used in SCOM bringup of
1422         * secondary CPUs. We read the code between the initial_tlb_code_start
1423         * and initial_tlb_code_end labels one instruction at a time and RAM it
1424         * into the new core via SCOM. That doesn't process branches, so there
1425         * must be none between those two labels. It also means if this code
1426         * ever takes any parameters, the SCOM code must also be updated to
1427         * provide them.
1428         */
1429        .globl a2_tlbinit_code_start
1430a2_tlbinit_code_start:
1431
1432        ori     r11,r3,MAS0_WQ_ALLWAYS
1433        oris    r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1434        mtspr   SPRN_MAS0,r11
1435        lis     r3,(MAS1_VALID | MAS1_IPROT)@h
1436        ori     r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1437        mtspr   SPRN_MAS1,r3
1438        LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1439        mtspr   SPRN_MAS2,r3
1440        li      r3,MAS3_SR | MAS3_SW | MAS3_SX
1441        mtspr   SPRN_MAS7_MAS3,r3
1442        li      r3,0
1443        mtspr   SPRN_MAS8,r3
1444
1445        /* Write the TLB entry */
1446        tlbwe
1447
1448        .globl a2_tlbinit_after_linear_map
1449a2_tlbinit_after_linear_map:
1450
1451        /* Now we branch the new virtual address mapped by this entry */
1452        LOAD_REG_IMMEDIATE(r3,1f)
1453        mtctr   r3
1454        bctr
1455
14561:      /* We are now running at PAGE_OFFSET, clean the TLB of everything
1457         * else (including IPROTed things left by firmware)
1458         * r4 = TLBnCFG
1459         * r3 = current address (more or less)
1460         */
1461
1462        li      r5,0
1463        mtspr   SPRN_MAS6,r5
1464        tlbsx   0,r3
1465
1466        rlwinm  r9,r4,0,TLBnCFG_N_ENTRY
1467        rlwinm  r10,r4,8,0xff
1468        addi    r10,r10,-1      /* Get inner loop mask */
1469
1470        li      r3,1
1471
1472        mfspr   r5,SPRN_MAS1
1473        rlwinm  r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1474
1475        mfspr   r6,SPRN_MAS2
1476        rldicr  r6,r6,0,51              /* Extract EPN */
1477
1478        mfspr   r7,SPRN_MAS0
1479        rlwinm  r7,r7,0,0xffff0fff      /* Clear HES and WQ */
1480
1481        rlwinm  r8,r7,16,0xfff          /* Extract ESEL */
1482
14832:      add     r4,r3,r8
1484        and     r4,r4,r10
1485
1486        rlwimi  r7,r4,16,MAS0_ESEL_MASK
1487
1488        mtspr   SPRN_MAS0,r7
1489        mtspr   SPRN_MAS1,r5
1490        mtspr   SPRN_MAS2,r6
1491        tlbwe
1492
1493        addi    r3,r3,1
1494        and.    r4,r3,r10
1495
1496        bne     3f
1497        addis   r6,r6,(1<<30)@h
14983:
1499        cmpw    r3,r9
1500        blt     2b
1501
1502        .globl  a2_tlbinit_after_iprot_flush
1503a2_tlbinit_after_iprot_flush:
1504
1505        PPC_TLBILX(0,0,R0)
1506        sync
1507        isync
1508
1509        .globl a2_tlbinit_code_end
1510a2_tlbinit_code_end:
1511
1512        /* We translate LR and return */
1513        mflr    r3
1514        tovirt(r3,r3)
1515        mtlr    r3
1516        blr
1517
1518/*
1519 * Main entry (boot CPU, thread 0)
1520 *
1521 * We enter here from head_64.S, possibly after the prom_init trampoline
1522 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1523 * mode. Anything else is as it was left by the bootloader
1524 *
1525 * Initial requirements of this port:
1526 *
1527 * - Kernel loaded at 0 physical
1528 * - A good lump of memory mapped 0:0 by UTLB entry 0
1529 * - MSR:IS & MSR:DS set to 0
1530 *
1531 * Note that some of the above requirements will be relaxed in the future
1532 * as the kernel becomes smarter at dealing with different initial conditions
1533 * but for now you have to be careful
1534 */
1535_GLOBAL(start_initialization_book3e)
1536        mflr    r28
1537
1538        /* First, we need to setup some initial TLBs to map the kernel
1539         * text, data and bss at PAGE_OFFSET. We don't have a real mode
1540         * and always use AS 0, so we just set it up to match our link
1541         * address and never use 0 based addresses.
1542         */
1543        bl      initial_tlb_book3e
1544
1545        /* Init global core bits */
1546        bl      init_core_book3e
1547
1548        /* Init per-thread bits */
1549        bl      init_thread_book3e
1550
1551        /* Return to common init code */
1552        tovirt(r28,r28)
1553        mtlr    r28
1554        blr
1555
1556
1557/*
1558 * Secondary core/processor entry
1559 *
1560 * This is entered for thread 0 of a secondary core, all other threads
1561 * are expected to be stopped. It's similar to start_initialization_book3e
1562 * except that it's generally entered from the holding loop in head_64.S
1563 * after CPUs have been gathered by Open Firmware.
1564 *
1565 * We assume we are in 32 bits mode running with whatever TLB entry was
1566 * set for us by the firmware or POR engine.
1567 */
1568_GLOBAL(book3e_secondary_core_init_tlb_set)
1569        li      r4,1
1570        b       generic_secondary_smp_init
1571
1572_GLOBAL(book3e_secondary_core_init)
1573        mflr    r28
1574
1575        /* Do we need to setup initial TLB entry ? */
1576        cmplwi  r4,0
1577        bne     2f
1578
1579        /* Setup TLB for this core */
1580        bl      initial_tlb_book3e
1581
1582        /* We can return from the above running at a different
1583         * address, so recalculate r2 (TOC)
1584         */
1585        bl      relative_toc
1586
1587        /* Init global core bits */
15882:      bl      init_core_book3e
1589
1590        /* Init per-thread bits */
15913:      bl      init_thread_book3e
1592
1593        /* Return to common init code at proper virtual address.
1594         *
1595         * Due to various previous assumptions, we know we entered this
1596         * function at either the final PAGE_OFFSET mapping or using a
1597         * 1:1 mapping at 0, so we don't bother doing a complicated check
1598         * here, we just ensure the return address has the right top bits.
1599         *
1600         * Note that if we ever want to be smarter about where we can be
1601         * started from, we have to be careful that by the time we reach
1602         * the code below we may already be running at a different location
1603         * than the one we were called from since initial_tlb_book3e can
1604         * have moved us already.
1605         */
1606        cmpdi   cr0,r28,0
1607        blt     1f
1608        lis     r3,PAGE_OFFSET@highest
1609        sldi    r3,r3,32
1610        or      r28,r28,r3
16111:      mtlr    r28
1612        blr
1613
1614_GLOBAL(book3e_secondary_thread_init)
1615        mflr    r28
1616        b       3b
1617
1618        .globl init_core_book3e
1619init_core_book3e:
1620        /* Establish the interrupt vector base */
1621        tovirt(r2,r2)
1622        LOAD_REG_ADDR(r3, interrupt_base_book3e)
1623        mtspr   SPRN_IVPR,r3
1624        sync
1625        blr
1626
1627init_thread_book3e:
1628        lis     r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1629        mtspr   SPRN_EPCR,r3
1630
1631        /* Make sure interrupts are off */
1632        wrteei  0
1633
1634        /* disable all timers and clear out status */
1635        li      r3,0
1636        mtspr   SPRN_TCR,r3
1637        mfspr   r3,SPRN_TSR
1638        mtspr   SPRN_TSR,r3
1639
1640        blr
1641
1642_GLOBAL(__setup_base_ivors)
1643        SET_IVOR(0, 0x020) /* Critical Input */
1644        SET_IVOR(1, 0x000) /* Machine Check */
1645        SET_IVOR(2, 0x060) /* Data Storage */ 
1646        SET_IVOR(3, 0x080) /* Instruction Storage */
1647        SET_IVOR(4, 0x0a0) /* External Input */ 
1648        SET_IVOR(5, 0x0c0) /* Alignment */ 
1649        SET_IVOR(6, 0x0e0) /* Program */ 
1650        SET_IVOR(7, 0x100) /* FP Unavailable */ 
1651        SET_IVOR(8, 0x120) /* System Call */ 
1652        SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 
1653        SET_IVOR(10, 0x160) /* Decrementer */ 
1654        SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 
1655        SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 
1656        SET_IVOR(13, 0x1c0) /* Data TLB Error */ 
1657        SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1658        SET_IVOR(15, 0x040) /* Debug */
1659
1660        sync
1661
1662        blr
1663
1664_GLOBAL(setup_altivec_ivors)
1665        SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1666        SET_IVOR(33, 0x220) /* AltiVec Assist */
1667        blr
1668
1669_GLOBAL(setup_perfmon_ivor)
1670        SET_IVOR(35, 0x260) /* Performance Monitor */
1671        blr
1672
1673_GLOBAL(setup_doorbell_ivors)
1674        SET_IVOR(36, 0x280) /* Processor Doorbell */
1675        SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1676        blr
1677
1678_GLOBAL(setup_ehv_ivors)
1679        SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1680        SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1681        SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1682        SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1683        blr
1684
1685_GLOBAL(setup_lrat_ivor)
1686        SET_IVOR(42, 0x340) /* LRAT Error */
1687        blr
1688