LXR linux/arch/powerpc/kernel/sysfs.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2#include <linux/device.h>
   3#include <linux/cpu.h>
   4#include <linux/smp.h>
   5#include <linux/percpu.h>
   6#include <linux/init.h>
   7#include <linux/sched.h>
   8#include <linux/export.h>
   9#include <linux/nodemask.h>
  10#include <linux/cpumask.h>
  11#include <linux/notifier.h>
  12
  13#include <asm/current.h>
  14#include <asm/processor.h>
  15#include <asm/cputable.h>
  16#include <asm/hvcall.h>
  17#include <asm/prom.h>
  18#include <asm/machdep.h>
  19#include <asm/smp.h>
  20#include <asm/pmc.h>
  21#include <asm/firmware.h>
  22
  23#include "cacheinfo.h"
  24#include "setup.h"
  25
  26#ifdef CONFIG_PPC64
  27#include <asm/paca.h>
  28#include <asm/lppaca.h>
  29#endif
  30
  31static DEFINE_PER_CPU(struct cpu, cpu_devices);
  32
  33/*
  34 * SMT snooze delay stuff, 64-bit only for now
  35 */
  36
  37#ifdef CONFIG_PPC64
  38
  39/* Time in microseconds we delay before sleeping in the idle loop */
  40static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
  41
  42static ssize_t store_smt_snooze_delay(struct device *dev,
  43                                      struct device_attribute *attr,
  44                                      const char *buf,
  45                                      size_t count)
  46{
  47        struct cpu *cpu = container_of(dev, struct cpu, dev);
  48        ssize_t ret;
  49        long snooze;
  50
  51        ret = sscanf(buf, "%ld", &snooze);
  52        if (ret != 1)
  53                return -EINVAL;
  54
  55        per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
  56        return count;
  57}
  58
  59static ssize_t show_smt_snooze_delay(struct device *dev,
  60                                     struct device_attribute *attr,
  61                                     char *buf)
  62{
  63        struct cpu *cpu = container_of(dev, struct cpu, dev);
  64
  65        return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
  66}
  67
  68static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  69                   store_smt_snooze_delay);
  70
  71static int __init setup_smt_snooze_delay(char *str)
  72{
  73        unsigned int cpu;
  74        long snooze;
  75
  76        if (!cpu_has_feature(CPU_FTR_SMT))
  77                return 1;
  78
  79        snooze = simple_strtol(str, NULL, 10);
  80        for_each_possible_cpu(cpu)
  81                per_cpu(smt_snooze_delay, cpu) = snooze;
  82
  83        return 1;
  84}
  85__setup("smt-snooze-delay=", setup_smt_snooze_delay);
  86
  87#endif /* CONFIG_PPC64 */
  88
  89#ifdef CONFIG_PPC_FSL_BOOK3E
  90#define MAX_BIT                         63
  91
  92static u64 pw20_wt;
  93static u64 altivec_idle_wt;
  94
  95static unsigned int get_idle_ticks_bit(u64 ns)
  96{
  97        u64 cycle;
  98
  99        if (ns >= 10000)
 100                cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
 101        else
 102                cycle = div_u64(ns * tb_ticks_per_usec, 1000);
 103
 104        if (!cycle)
 105                return 0;
 106
 107        return ilog2(cycle);
 108}
 109
 110static void do_show_pwrmgtcr0(void *val)
 111{
 112        u32 *value = val;
 113
 114        *value = mfspr(SPRN_PWRMGTCR0);
 115}
 116
 117static ssize_t show_pw20_state(struct device *dev,
 118                                struct device_attribute *attr, char *buf)
 119{
 120        u32 value;
 121        unsigned int cpu = dev->id;
 122
 123        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 124
 125        value &= PWRMGTCR0_PW20_WAIT;
 126
 127        return sprintf(buf, "%u\n", value ? 1 : 0);
 128}
 129
 130static void do_store_pw20_state(void *val)
 131{
 132        u32 *value = val;
 133        u32 pw20_state;
 134
 135        pw20_state = mfspr(SPRN_PWRMGTCR0);
 136
 137        if (*value)
 138                pw20_state |= PWRMGTCR0_PW20_WAIT;
 139        else
 140                pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 141
 142        mtspr(SPRN_PWRMGTCR0, pw20_state);
 143}
 144
 145static ssize_t store_pw20_state(struct device *dev,
 146                                struct device_attribute *attr,
 147                                const char *buf, size_t count)
 148{
 149        u32 value;
 150        unsigned int cpu = dev->id;
 151
 152        if (kstrtou32(buf, 0, &value))
 153                return -EINVAL;
 154
 155        if (value > 1)
 156                return -EINVAL;
 157
 158        smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 159
 160        return count;
 161}
 162
 163static ssize_t show_pw20_wait_time(struct device *dev,
 164                                struct device_attribute *attr, char *buf)
 165{
 166        u32 value;
 167        u64 tb_cycle = 1;
 168        u64 time;
 169
 170        unsigned int cpu = dev->id;
 171
 172        if (!pw20_wt) {
 173                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 174                value = (value & PWRMGTCR0_PW20_ENT) >>
 175                                        PWRMGTCR0_PW20_ENT_SHIFT;
 176
 177                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 178                /* convert ms to ns */
 179                if (tb_ticks_per_usec > 1000) {
 180                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 181                } else {
 182                        u32 rem_us;
 183
 184                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 185                                                &rem_us);
 186                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 187                }
 188        } else {
 189                time = pw20_wt;
 190        }
 191
 192        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 193}
 194
 195static void set_pw20_wait_entry_bit(void *val)
 196{
 197        u32 *value = val;
 198        u32 pw20_idle;
 199
 200        pw20_idle = mfspr(SPRN_PWRMGTCR0);
 201
 202        /* Set Automatic PW20 Core Idle Count */
 203        /* clear count */
 204        pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 205
 206        /* set count */
 207        pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 208
 209        mtspr(SPRN_PWRMGTCR0, pw20_idle);
 210}
 211
 212static ssize_t store_pw20_wait_time(struct device *dev,
 213                                struct device_attribute *attr,
 214                                const char *buf, size_t count)
 215{
 216        u32 entry_bit;
 217        u64 value;
 218
 219        unsigned int cpu = dev->id;
 220
 221        if (kstrtou64(buf, 0, &value))
 222                return -EINVAL;
 223
 224        if (!value)
 225                return -EINVAL;
 226
 227        entry_bit = get_idle_ticks_bit(value);
 228        if (entry_bit > MAX_BIT)
 229                return -EINVAL;
 230
 231        pw20_wt = value;
 232
 233        smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 234                                &entry_bit, 1);
 235
 236        return count;
 237}
 238
 239static ssize_t show_altivec_idle(struct device *dev,
 240                                struct device_attribute *attr, char *buf)
 241{
 242        u32 value;
 243        unsigned int cpu = dev->id;
 244
 245        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 246
 247        value &= PWRMGTCR0_AV_IDLE_PD_EN;
 248
 249        return sprintf(buf, "%u\n", value ? 1 : 0);
 250}
 251
 252static void do_store_altivec_idle(void *val)
 253{
 254        u32 *value = val;
 255        u32 altivec_idle;
 256
 257        altivec_idle = mfspr(SPRN_PWRMGTCR0);
 258
 259        if (*value)
 260                altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 261        else
 262                altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 263
 264        mtspr(SPRN_PWRMGTCR0, altivec_idle);
 265}
 266
 267static ssize_t store_altivec_idle(struct device *dev,
 268                                struct device_attribute *attr,
 269                                const char *buf, size_t count)
 270{
 271        u32 value;
 272        unsigned int cpu = dev->id;
 273
 274        if (kstrtou32(buf, 0, &value))
 275                return -EINVAL;
 276
 277        if (value > 1)
 278                return -EINVAL;
 279
 280        smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 281
 282        return count;
 283}
 284
 285static ssize_t show_altivec_idle_wait_time(struct device *dev,
 286                                struct device_attribute *attr, char *buf)
 287{
 288        u32 value;
 289        u64 tb_cycle = 1;
 290        u64 time;
 291
 292        unsigned int cpu = dev->id;
 293
 294        if (!altivec_idle_wt) {
 295                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 296                value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 297                                        PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 298
 299                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 300                /* convert ms to ns */
 301                if (tb_ticks_per_usec > 1000) {
 302                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 303                } else {
 304                        u32 rem_us;
 305
 306                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 307                                                &rem_us);
 308                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 309                }
 310        } else {
 311                time = altivec_idle_wt;
 312        }
 313
 314        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 315}
 316
 317static void set_altivec_idle_wait_entry_bit(void *val)
 318{
 319        u32 *value = val;
 320        u32 altivec_idle;
 321
 322        altivec_idle = mfspr(SPRN_PWRMGTCR0);
 323
 324        /* Set Automatic AltiVec Idle Count */
 325        /* clear count */
 326        altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 327
 328        /* set count */
 329        altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 330
 331        mtspr(SPRN_PWRMGTCR0, altivec_idle);
 332}
 333
 334static ssize_t store_altivec_idle_wait_time(struct device *dev,
 335                                struct device_attribute *attr,
 336                                const char *buf, size_t count)
 337{
 338        u32 entry_bit;
 339        u64 value;
 340
 341        unsigned int cpu = dev->id;
 342
 343        if (kstrtou64(buf, 0, &value))
 344                return -EINVAL;
 345
 346        if (!value)
 347                return -EINVAL;
 348
 349        entry_bit = get_idle_ticks_bit(value);
 350        if (entry_bit > MAX_BIT)
 351                return -EINVAL;
 352
 353        altivec_idle_wt = value;
 354
 355        smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 356                                &entry_bit, 1);
 357
 358        return count;
 359}
 360
 361/*
 362 * Enable/Disable interface:
 363 * 0, disable. 1, enable.
 364 */
 365static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 366static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 367
 368/*
 369 * Set wait time interface:(Nanosecond)
 370 * Example: Base on TBfreq is 41MHZ.
 371 * 1~48(ns): TB[63]
 372 * 49~97(ns): TB[62]
 373 * 98~195(ns): TB[61]
 374 * 196~390(ns): TB[60]
 375 * 391~780(ns): TB[59]
 376 * 781~1560(ns): TB[58]
 377 * ...
 378 */
 379static DEVICE_ATTR(pw20_wait_time, 0600,
 380                        show_pw20_wait_time,
 381                        store_pw20_wait_time);
 382static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 383                        show_altivec_idle_wait_time,
 384                        store_altivec_idle_wait_time);
 385#endif
 386
 387/*
 388 * Enabling PMCs will slow partition context switch times so we only do
 389 * it the first time we write to the PMCs.
 390 */
 391
 392static DEFINE_PER_CPU(char, pmcs_enabled);
 393
 394void ppc_enable_pmcs(void)
 395{
 396        ppc_set_pmu_inuse(1);
 397
 398        /* Only need to enable them once */
 399        if (__this_cpu_read(pmcs_enabled))
 400                return;
 401
 402        __this_cpu_write(pmcs_enabled, 1);
 403
 404        if (ppc_md.enable_pmcs)
 405                ppc_md.enable_pmcs();
 406}
 407EXPORT_SYMBOL(ppc_enable_pmcs);
 408
 409#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 410static void read_##NAME(void *val) \
 411{ \
 412        *(unsigned long *)val = mfspr(ADDRESS); \
 413} \
 414static void write_##NAME(void *val) \
 415{ \
 416        EXTRA; \
 417        mtspr(ADDRESS, *(unsigned long *)val);  \
 418}
 419
 420#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 421static ssize_t show_##NAME(struct device *dev, \
 422                        struct device_attribute *attr, \
 423                        char *buf) \
 424{ \
 425        struct cpu *cpu = container_of(dev, struct cpu, dev); \
 426        unsigned long val; \
 427        smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 428        return sprintf(buf, "%lx\n", val); \
 429} \
 430static ssize_t __used \
 431        store_##NAME(struct device *dev, struct device_attribute *attr, \
 432                        const char *buf, size_t count) \
 433{ \
 434        struct cpu *cpu = container_of(dev, struct cpu, dev); \
 435        unsigned long val; \
 436        int ret = sscanf(buf, "%lx", &val); \
 437        if (ret != 1) \
 438                return -EINVAL; \
 439        smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 440        return count; \
 441}
 442
 443#define SYSFS_PMCSETUP(NAME, ADDRESS) \
 444        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 445        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 446#define SYSFS_SPRSETUP(NAME, ADDRESS) \
 447        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 448        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 449
 450#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 451        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 452
 453/* Let's define all possible registers, we'll only hook up the ones
 454 * that are implemented on the current processor
 455 */
 456
 457#if defined(CONFIG_PPC64)
 458#define HAS_PPC_PMC_CLASSIC     1
 459#define HAS_PPC_PMC_IBM         1
 460#define HAS_PPC_PMC_PA6T        1
 461#elif defined(CONFIG_PPC_BOOK3S_32)
 462#define HAS_PPC_PMC_CLASSIC     1
 463#define HAS_PPC_PMC_IBM         1
 464#define HAS_PPC_PMC_G4          1
 465#endif
 466
 467
 468#ifdef HAS_PPC_PMC_CLASSIC
 469SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 470SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 471SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 472SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 473SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 474SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 475SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 476SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 477
 478#ifdef HAS_PPC_PMC_G4
 479SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 480#endif
 481
 482#ifdef CONFIG_PPC64
 483SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 484SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 485
 486SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 487SYSFS_SPRSETUP(purr, SPRN_PURR);
 488SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 489SYSFS_SPRSETUP(pir, SPRN_PIR);
 490SYSFS_SPRSETUP(tscr, SPRN_TSCR);
 491
 492/*
 493  Lets only enable read for phyp resources and
 494  enable write when needed with a separate function.
 495  Lets be conservative and default to pseries.
 496*/
 497static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 498static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 499static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 500static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 501static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
 502
 503/*
 504 * This is the system wide DSCR register default value. Any
 505 * change to this default value through the sysfs interface
 506 * will update all per cpu DSCR default values across the
 507 * system stored in their respective PACA structures.
 508 */
 509static unsigned long dscr_default;
 510
 511/**
 512 * read_dscr() - Fetch the cpu specific DSCR default
 513 * @val:        Returned cpu specific DSCR default value
 514 *
 515 * This function returns the per cpu DSCR default value
 516 * for any cpu which is contained in it's PACA structure.
 517 */
 518static void read_dscr(void *val)
 519{
 520        *(unsigned long *)val = get_paca()->dscr_default;
 521}
 522
 523
 524/**
 525 * write_dscr() - Update the cpu specific DSCR default
 526 * @val:        New cpu specific DSCR default value to update
 527 *
 528 * This function updates the per cpu DSCR default value
 529 * for any cpu which is contained in it's PACA structure.
 530 */
 531static void write_dscr(void *val)
 532{
 533        get_paca()->dscr_default = *(unsigned long *)val;
 534        if (!current->thread.dscr_inherit) {
 535                current->thread.dscr = *(unsigned long *)val;
 536                mtspr(SPRN_DSCR, *(unsigned long *)val);
 537        }
 538}
 539
 540SYSFS_SPRSETUP_SHOW_STORE(dscr);
 541static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 542
 543static void add_write_permission_dev_attr(struct device_attribute *attr)
 544{
 545        attr->attr.mode |= 0200;
 546}
 547
 548/**
 549 * show_dscr_default() - Fetch the system wide DSCR default
 550 * @dev:        Device structure
 551 * @attr:       Device attribute structure
 552 * @buf:        Interface buffer
 553 *
 554 * This function returns the system wide DSCR default value.
 555 */
 556static ssize_t show_dscr_default(struct device *dev,
 557                struct device_attribute *attr, char *buf)
 558{
 559        return sprintf(buf, "%lx\n", dscr_default);
 560}
 561
 562/**
 563 * store_dscr_default() - Update the system wide DSCR default
 564 * @dev:        Device structure
 565 * @attr:       Device attribute structure
 566 * @buf:        Interface buffer
 567 * @count:      Size of the update
 568 *
 569 * This function updates the system wide DSCR default value.
 570 */
 571static ssize_t __used store_dscr_default(struct device *dev,
 572                struct device_attribute *attr, const char *buf,
 573                size_t count)
 574{
 575        unsigned long val;
 576        int ret = 0;
 577        
 578        ret = sscanf(buf, "%lx", &val);
 579        if (ret != 1)
 580                return -EINVAL;
 581        dscr_default = val;
 582
 583        on_each_cpu(write_dscr, &val, 1);
 584
 585        return count;
 586}
 587
 588static DEVICE_ATTR(dscr_default, 0600,
 589                show_dscr_default, store_dscr_default);
 590
 591static void sysfs_create_dscr_default(void)
 592{
 593        if (cpu_has_feature(CPU_FTR_DSCR)) {
 594                int err = 0;
 595                int cpu;
 596
 597                dscr_default = spr_default_dscr;
 598                for_each_possible_cpu(cpu)
 599                        paca_ptrs[cpu]->dscr_default = dscr_default;
 600
 601                err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 602        }
 603}
 604
 605#endif /* CONFIG_PPC64 */
 606
 607#ifdef HAS_PPC_PMC_PA6T
 608SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 609SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 610SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 611SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 612SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 613SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 614#ifdef CONFIG_DEBUG_MISC
 615SYSFS_SPRSETUP(hid0, SPRN_HID0);
 616SYSFS_SPRSETUP(hid1, SPRN_HID1);
 617SYSFS_SPRSETUP(hid4, SPRN_HID4);
 618SYSFS_SPRSETUP(hid5, SPRN_HID5);
 619SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 620SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 621SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 622SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 623SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 624SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 625SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 626SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 627SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 628SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 629SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 630SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 631SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 632SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 633SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 634SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 635SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 636SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 637SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 638SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 639SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 640SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 641SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 642SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 643#endif /* CONFIG_DEBUG_MISC */
 644#endif /* HAS_PPC_PMC_PA6T */
 645
 646#ifdef HAS_PPC_PMC_IBM
 647static struct device_attribute ibm_common_attrs[] = {
 648        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 649        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 650};
 651#endif /* HAS_PPC_PMC_G4 */
 652
 653#ifdef HAS_PPC_PMC_G4
 654static struct device_attribute g4_common_attrs[] = {
 655        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 656        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 657        __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 658};
 659#endif /* HAS_PPC_PMC_G4 */
 660
 661static struct device_attribute classic_pmc_attrs[] = {
 662        __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 663        __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 664        __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 665        __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 666        __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 667        __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 668#ifdef CONFIG_PPC64
 669        __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 670        __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 671#endif
 672};
 673
 674#ifdef HAS_PPC_PMC_PA6T
 675static struct device_attribute pa6t_attrs[] = {
 676        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 677        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 678        __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 679        __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 680        __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 681        __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 682        __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 683        __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 684#ifdef CONFIG_DEBUG_MISC
 685        __ATTR(hid0, 0600, show_hid0, store_hid0),
 686        __ATTR(hid1, 0600, show_hid1, store_hid1),
 687        __ATTR(hid4, 0600, show_hid4, store_hid4),
 688        __ATTR(hid5, 0600, show_hid5, store_hid5),
 689        __ATTR(ima0, 0600, show_ima0, store_ima0),
 690        __ATTR(ima1, 0600, show_ima1, store_ima1),
 691        __ATTR(ima2, 0600, show_ima2, store_ima2),
 692        __ATTR(ima3, 0600, show_ima3, store_ima3),
 693        __ATTR(ima4, 0600, show_ima4, store_ima4),
 694        __ATTR(ima5, 0600, show_ima5, store_ima5),
 695        __ATTR(ima6, 0600, show_ima6, store_ima6),
 696        __ATTR(ima7, 0600, show_ima7, store_ima7),
 697        __ATTR(ima8, 0600, show_ima8, store_ima8),
 698        __ATTR(ima9, 0600, show_ima9, store_ima9),
 699        __ATTR(imaat, 0600, show_imaat, store_imaat),
 700        __ATTR(btcr, 0600, show_btcr, store_btcr),
 701        __ATTR(pccr, 0600, show_pccr, store_pccr),
 702        __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 703        __ATTR(der, 0600, show_der, store_der),
 704        __ATTR(mer, 0600, show_mer, store_mer),
 705        __ATTR(ber, 0600, show_ber, store_ber),
 706        __ATTR(ier, 0600, show_ier, store_ier),
 707        __ATTR(sier, 0600, show_sier, store_sier),
 708        __ATTR(siar, 0600, show_siar, store_siar),
 709        __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 710        __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 711        __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 712        __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 713#endif /* CONFIG_DEBUG_MISC */
 714};
 715#endif /* HAS_PPC_PMC_PA6T */
 716#endif /* HAS_PPC_PMC_CLASSIC */
 717
 718static int register_cpu_online(unsigned int cpu)
 719{
 720        struct cpu *c = &per_cpu(cpu_devices, cpu);
 721        struct device *s = &c->dev;
 722        struct device_attribute *attrs, *pmc_attrs;
 723        int i, nattrs;
 724
 725        /* For cpus present at boot a reference was already grabbed in register_cpu() */
 726        if (!s->of_node)
 727                s->of_node = of_get_cpu_node(cpu, NULL);
 728
 729#ifdef CONFIG_PPC64
 730        if (cpu_has_feature(CPU_FTR_SMT))
 731                device_create_file(s, &dev_attr_smt_snooze_delay);
 732#endif
 733
 734        /* PMC stuff */
 735        switch (cur_cpu_spec->pmc_type) {
 736#ifdef HAS_PPC_PMC_IBM
 737        case PPC_PMC_IBM:
 738                attrs = ibm_common_attrs;
 739                nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 740                pmc_attrs = classic_pmc_attrs;
 741                break;
 742#endif /* HAS_PPC_PMC_IBM */
 743#ifdef HAS_PPC_PMC_G4
 744        case PPC_PMC_G4:
 745                attrs = g4_common_attrs;
 746                nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 747                pmc_attrs = classic_pmc_attrs;
 748                break;
 749#endif /* HAS_PPC_PMC_G4 */
 750#ifdef HAS_PPC_PMC_PA6T
 751        case PPC_PMC_PA6T:
 752                /* PA Semi starts counting at PMC0 */
 753                attrs = pa6t_attrs;
 754                nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 755                pmc_attrs = NULL;
 756                break;
 757#endif /* HAS_PPC_PMC_PA6T */
 758        default:
 759                attrs = NULL;
 760                nattrs = 0;
 761                pmc_attrs = NULL;
 762        }
 763
 764        for (i = 0; i < nattrs; i++)
 765                device_create_file(s, &attrs[i]);
 766
 767        if (pmc_attrs)
 768                for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 769                        device_create_file(s, &pmc_attrs[i]);
 770
 771#ifdef CONFIG_PPC64
 772        if (cpu_has_feature(CPU_FTR_MMCRA))
 773                device_create_file(s, &dev_attr_mmcra);
 774
 775        if (cpu_has_feature(CPU_FTR_PURR)) {
 776                if (!firmware_has_feature(FW_FEATURE_LPAR))
 777                        add_write_permission_dev_attr(&dev_attr_purr);
 778                device_create_file(s, &dev_attr_purr);
 779        }
 780
 781        if (cpu_has_feature(CPU_FTR_SPURR))
 782                device_create_file(s, &dev_attr_spurr);
 783
 784        if (cpu_has_feature(CPU_FTR_DSCR))
 785                device_create_file(s, &dev_attr_dscr);
 786
 787        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 788                device_create_file(s, &dev_attr_pir);
 789
 790        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 791                !firmware_has_feature(FW_FEATURE_LPAR))
 792                device_create_file(s, &dev_attr_tscr);
 793#endif /* CONFIG_PPC64 */
 794
 795#ifdef CONFIG_PPC_FSL_BOOK3E
 796        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 797                device_create_file(s, &dev_attr_pw20_state);
 798                device_create_file(s, &dev_attr_pw20_wait_time);
 799
 800                device_create_file(s, &dev_attr_altivec_idle);
 801                device_create_file(s, &dev_attr_altivec_idle_wait_time);
 802        }
 803#endif
 804        cacheinfo_cpu_online(cpu);
 805        return 0;
 806}
 807
 808#ifdef CONFIG_HOTPLUG_CPU
 809static int unregister_cpu_online(unsigned int cpu)
 810{
 811        struct cpu *c = &per_cpu(cpu_devices, cpu);
 812        struct device *s = &c->dev;
 813        struct device_attribute *attrs, *pmc_attrs;
 814        int i, nattrs;
 815
 816        BUG_ON(!c->hotpluggable);
 817
 818#ifdef CONFIG_PPC64
 819        if (cpu_has_feature(CPU_FTR_SMT))
 820                device_remove_file(s, &dev_attr_smt_snooze_delay);
 821#endif
 822
 823        /* PMC stuff */
 824        switch (cur_cpu_spec->pmc_type) {
 825#ifdef HAS_PPC_PMC_IBM
 826        case PPC_PMC_IBM:
 827                attrs = ibm_common_attrs;
 828                nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 829                pmc_attrs = classic_pmc_attrs;
 830                break;
 831#endif /* HAS_PPC_PMC_IBM */
 832#ifdef HAS_PPC_PMC_G4
 833        case PPC_PMC_G4:
 834                attrs = g4_common_attrs;
 835                nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 836                pmc_attrs = classic_pmc_attrs;
 837                break;
 838#endif /* HAS_PPC_PMC_G4 */
 839#ifdef HAS_PPC_PMC_PA6T
 840        case PPC_PMC_PA6T:
 841                /* PA Semi starts counting at PMC0 */
 842                attrs = pa6t_attrs;
 843                nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 844                pmc_attrs = NULL;
 845                break;
 846#endif /* HAS_PPC_PMC_PA6T */
 847        default:
 848                attrs = NULL;
 849                nattrs = 0;
 850                pmc_attrs = NULL;
 851        }
 852
 853        for (i = 0; i < nattrs; i++)
 854                device_remove_file(s, &attrs[i]);
 855
 856        if (pmc_attrs)
 857                for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 858                        device_remove_file(s, &pmc_attrs[i]);
 859
 860#ifdef CONFIG_PPC64
 861        if (cpu_has_feature(CPU_FTR_MMCRA))
 862                device_remove_file(s, &dev_attr_mmcra);
 863
 864        if (cpu_has_feature(CPU_FTR_PURR))
 865                device_remove_file(s, &dev_attr_purr);
 866
 867        if (cpu_has_feature(CPU_FTR_SPURR))
 868                device_remove_file(s, &dev_attr_spurr);
 869
 870        if (cpu_has_feature(CPU_FTR_DSCR))
 871                device_remove_file(s, &dev_attr_dscr);
 872
 873        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 874                device_remove_file(s, &dev_attr_pir);
 875
 876        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 877                !firmware_has_feature(FW_FEATURE_LPAR))
 878                device_remove_file(s, &dev_attr_tscr);
 879#endif /* CONFIG_PPC64 */
 880
 881#ifdef CONFIG_PPC_FSL_BOOK3E
 882        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 883                device_remove_file(s, &dev_attr_pw20_state);
 884                device_remove_file(s, &dev_attr_pw20_wait_time);
 885
 886                device_remove_file(s, &dev_attr_altivec_idle);
 887                device_remove_file(s, &dev_attr_altivec_idle_wait_time);
 888        }
 889#endif
 890        cacheinfo_cpu_offline(cpu);
 891        of_node_put(s->of_node);
 892        s->of_node = NULL;
 893        return 0;
 894}
 895#else /* !CONFIG_HOTPLUG_CPU */
 896#define unregister_cpu_online NULL
 897#endif
 898
 899#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
 900ssize_t arch_cpu_probe(const char *buf, size_t count)
 901{
 902        if (ppc_md.cpu_probe)
 903                return ppc_md.cpu_probe(buf, count);
 904
 905        return -EINVAL;
 906}
 907
 908ssize_t arch_cpu_release(const char *buf, size_t count)
 909{
 910        if (ppc_md.cpu_release)
 911                return ppc_md.cpu_release(buf, count);
 912
 913        return -EINVAL;
 914}
 915#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 916
 917static DEFINE_MUTEX(cpu_mutex);
 918
 919int cpu_add_dev_attr(struct device_attribute *attr)
 920{
 921        int cpu;
 922
 923        mutex_lock(&cpu_mutex);
 924
 925        for_each_possible_cpu(cpu) {
 926                device_create_file(get_cpu_device(cpu), attr);
 927        }
 928
 929        mutex_unlock(&cpu_mutex);
 930        return 0;
 931}
 932EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
 933
 934int cpu_add_dev_attr_group(struct attribute_group *attrs)
 935{
 936        int cpu;
 937        struct device *dev;
 938        int ret;
 939
 940        mutex_lock(&cpu_mutex);
 941
 942        for_each_possible_cpu(cpu) {
 943                dev = get_cpu_device(cpu);
 944                ret = sysfs_create_group(&dev->kobj, attrs);
 945                WARN_ON(ret != 0);
 946        }
 947
 948        mutex_unlock(&cpu_mutex);
 949        return 0;
 950}
 951EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
 952
 953
 954void cpu_remove_dev_attr(struct device_attribute *attr)
 955{
 956        int cpu;
 957
 958        mutex_lock(&cpu_mutex);
 959
 960        for_each_possible_cpu(cpu) {
 961                device_remove_file(get_cpu_device(cpu), attr);
 962        }
 963
 964        mutex_unlock(&cpu_mutex);
 965}
 966EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
 967
 968void cpu_remove_dev_attr_group(struct attribute_group *attrs)
 969{
 970        int cpu;
 971        struct device *dev;
 972
 973        mutex_lock(&cpu_mutex);
 974
 975        for_each_possible_cpu(cpu) {
 976                dev = get_cpu_device(cpu);
 977                sysfs_remove_group(&dev->kobj, attrs);
 978        }
 979
 980        mutex_unlock(&cpu_mutex);
 981}
 982EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
 983
 984
 985/* NUMA stuff */
 986
 987#ifdef CONFIG_NUMA
 988static void register_nodes(void)
 989{
 990        int i;
 991
 992        for (i = 0; i < MAX_NUMNODES; i++)
 993                register_one_node(i);
 994}
 995
 996int sysfs_add_device_to_node(struct device *dev, int nid)
 997{
 998        struct node *node = node_devices[nid];
 999        return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1000                        kobject_name(&dev->kobj));

1001}
1002EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1003
1004void sysfs_remove_device_from_node(struct device *dev, int nid)
1005{
1006        struct node *node = node_devices[nid];
1007        sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1008}
1009EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1010
1011#else
1012static void register_nodes(void)
1013{
1014        return;
1015}
1016
1017#endif
1018
1019/* Only valid if CPU is present. */
1020static ssize_t show_physical_id(struct device *dev,
1021                                struct device_attribute *attr, char *buf)
1022{
1023        struct cpu *cpu = container_of(dev, struct cpu, dev);
1024
1025        return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1026}
1027static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1028
1029static int __init topology_init(void)
1030{
1031        int cpu, r;
1032
1033        register_nodes();
1034
1035        for_each_possible_cpu(cpu) {
1036                struct cpu *c = &per_cpu(cpu_devices, cpu);
1037
1038                /*
1039                 * For now, we just see if the system supports making
1040                 * the RTAS calls for CPU hotplug.  But, there may be a
1041                 * more comprehensive way to do this for an individual
1042                 * CPU.  For instance, the boot cpu might never be valid
1043                 * for hotplugging.
1044                 */
1045                if (ppc_md.cpu_die)
1046                        c->hotpluggable = 1;
1047
1048                if (cpu_online(cpu) || c->hotpluggable) {
1049                        register_cpu(c, cpu);
1050
1051                        device_create_file(&c->dev, &dev_attr_physical_id);
1052                }
1053        }
1054        r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1055                              register_cpu_online, unregister_cpu_online);
1056        WARN_ON(r < 0);
1057#ifdef CONFIG_PPC64
1058        sysfs_create_dscr_default();
1059#endif /* CONFIG_PPC64 */
1060
1061        return 0;
1062}
1063subsys_initcall(topology_init);
1064