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17#undef DEBUG
18#undef DEBUG_LOW
19
20#define pr_fmt(fmt) "hash-mmu: " fmt
21#include <linux/spinlock.h>
22#include <linux/errno.h>
23#include <linux/sched/mm.h>
24#include <linux/proc_fs.h>
25#include <linux/stat.h>
26#include <linux/sysctl.h>
27#include <linux/export.h>
28#include <linux/ctype.h>
29#include <linux/cache.h>
30#include <linux/init.h>
31#include <linux/signal.h>
32#include <linux/memblock.h>
33#include <linux/context_tracking.h>
34#include <linux/libfdt.h>
35#include <linux/pkeys.h>
36#include <linux/hugetlb.h>
37
38#include <asm/debugfs.h>
39#include <asm/processor.h>
40#include <asm/pgtable.h>
41#include <asm/mmu.h>
42#include <asm/mmu_context.h>
43#include <asm/page.h>
44#include <asm/types.h>
45#include <linux/uaccess.h>
46#include <asm/machdep.h>
47#include <asm/prom.h>
48#include <asm/io.h>
49#include <asm/eeh.h>
50#include <asm/tlb.h>
51#include <asm/cacheflush.h>
52#include <asm/cputable.h>
53#include <asm/sections.h>
54#include <asm/copro.h>
55#include <asm/udbg.h>
56#include <asm/code-patching.h>
57#include <asm/fadump.h>
58#include <asm/firmware.h>
59#include <asm/tm.h>
60#include <asm/trace.h>
61#include <asm/ps3.h>
62#include <asm/pte-walk.h>
63#include <asm/asm-prototypes.h>
64
65#include <mm/mmu_decl.h>
66
67#ifdef DEBUG
68#define DBG(fmt...) udbg_printf(fmt)
69#else
70#define DBG(fmt...)
71#endif
72
73#ifdef DEBUG_LOW
74#define DBG_LOW(fmt...) udbg_printf(fmt)
75#else
76#define DBG_LOW(fmt...)
77#endif
78
79#define KB (1024)
80#define MB (1024*KB)
81#define GB (1024L*MB)
82
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93
94
95static unsigned long _SDR1;
96struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
97EXPORT_SYMBOL_GPL(mmu_psize_defs);
98
99u8 hpte_page_sizes[1 << LP_BITS];
100EXPORT_SYMBOL_GPL(hpte_page_sizes);
101
102struct hash_pte *htab_address;
103unsigned long htab_size_bytes;
104unsigned long htab_hash_mask;
105EXPORT_SYMBOL_GPL(htab_hash_mask);
106int mmu_linear_psize = MMU_PAGE_4K;
107EXPORT_SYMBOL_GPL(mmu_linear_psize);
108int mmu_virtual_psize = MMU_PAGE_4K;
109int mmu_vmalloc_psize = MMU_PAGE_4K;
110#ifdef CONFIG_SPARSEMEM_VMEMMAP
111int mmu_vmemmap_psize = MMU_PAGE_4K;
112#endif
113int mmu_io_psize = MMU_PAGE_4K;
114int mmu_kernel_ssize = MMU_SEGSIZE_256M;
115EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
116int mmu_highuser_ssize = MMU_SEGSIZE_256M;
117u16 mmu_slb_size = 64;
118EXPORT_SYMBOL_GPL(mmu_slb_size);
119#ifdef CONFIG_PPC_64K_PAGES
120int mmu_ci_restrictions;
121#endif
122#ifdef CONFIG_DEBUG_PAGEALLOC
123static u8 *linear_map_hash_slots;
124static unsigned long linear_map_hash_count;
125static DEFINE_SPINLOCK(linear_map_hash_lock);
126#endif
127struct mmu_hash_ops mmu_hash_ops;
128EXPORT_SYMBOL(mmu_hash_ops);
129
130
131
132
133
134
135
136
137
138static struct mmu_psize_def mmu_psize_defaults[] = {
139 [MMU_PAGE_4K] = {
140 .shift = 12,
141 .sllp = 0,
142 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
143 .avpnm = 0,
144 .tlbiel = 0,
145 },
146};
147
148
149
150
151
152
153static struct mmu_psize_def mmu_psize_defaults_gp[] = {
154 [MMU_PAGE_4K] = {
155 .shift = 12,
156 .sllp = 0,
157 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
158 .avpnm = 0,
159 .tlbiel = 1,
160 },
161 [MMU_PAGE_16M] = {
162 .shift = 24,
163 .sllp = SLB_VSID_L,
164 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
165 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
166 .avpnm = 0x1UL,
167 .tlbiel = 0,
168 },
169};
170
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182
183
184unsigned long htab_convert_pte_flags(unsigned long pteflags)
185{
186 unsigned long rflags = 0;
187
188
189 if ((pteflags & _PAGE_EXEC) == 0)
190 rflags |= HPTE_R_N;
191
192
193
194
195
196
197
198 if (pteflags & _PAGE_PRIVILEGED) {
199
200
201
202 if (!(pteflags & _PAGE_WRITE)) {
203 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
204 rflags |= (HPTE_R_PP0 | 0x2);
205 else
206 rflags |= 0x3;
207 }
208 } else {
209 if (pteflags & _PAGE_RWX)
210 rflags |= 0x2;
211 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
212 rflags |= 0x1;
213 }
214
215
216
217
218 rflags |= HPTE_R_R;
219
220 if (pteflags & _PAGE_DIRTY)
221 rflags |= HPTE_R_C;
222
223
224
225
226 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
227 rflags |= HPTE_R_I;
228 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
229 rflags |= (HPTE_R_I | HPTE_R_G);
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
231 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
232 else
233
234
235
236 rflags |= HPTE_R_M;
237
238 rflags |= pte_to_hpte_pkey_bits(pteflags);
239 return rflags;
240}
241
242int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
243 unsigned long pstart, unsigned long prot,
244 int psize, int ssize)
245{
246 unsigned long vaddr, paddr;
247 unsigned int step, shift;
248 int ret = 0;
249
250 shift = mmu_psize_defs[psize].shift;
251 step = 1 << shift;
252
253 prot = htab_convert_pte_flags(prot);
254
255 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
256 vstart, vend, pstart, prot, psize, ssize);
257
258 for (vaddr = vstart, paddr = pstart; vaddr < vend;
259 vaddr += step, paddr += step) {
260 unsigned long hash, hpteg;
261 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
262 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
263 unsigned long tprot = prot;
264
265
266
267
268 if (!vsid)
269 return -1;
270
271 if (overlaps_kernel_text(vaddr, vaddr + step))
272 tprot &= ~HPTE_R_N;
273
274
275 if (overlaps_kvm_tmp(vaddr, vaddr + step))
276 tprot &= ~HPTE_R_N;
277
278
279
280
281
282
283
284
285
286
287
288 if ((PHYSICAL_START > MEMORY_START) &&
289 overlaps_interrupt_vector_text(vaddr, vaddr + step))
290 tprot &= ~HPTE_R_N;
291
292 hash = hpt_hash(vpn, shift, ssize);
293 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
294
295 BUG_ON(!mmu_hash_ops.hpte_insert);
296 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
297 HPTE_V_BOLTED, psize, psize,
298 ssize);
299
300 if (ret < 0)
301 break;
302
303#ifdef CONFIG_DEBUG_PAGEALLOC
304 if (debug_pagealloc_enabled() &&
305 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
306 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
307#endif
308 }
309 return ret < 0 ? ret : 0;
310}
311
312int htab_remove_mapping(unsigned long vstart, unsigned long vend,
313 int psize, int ssize)
314{
315 unsigned long vaddr;
316 unsigned int step, shift;
317 int rc;
318 int ret = 0;
319
320 shift = mmu_psize_defs[psize].shift;
321 step = 1 << shift;
322
323 if (!mmu_hash_ops.hpte_removebolted)
324 return -ENODEV;
325
326 for (vaddr = vstart; vaddr < vend; vaddr += step) {
327 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
328 if (rc == -ENOENT) {
329 ret = -ENOENT;
330 continue;
331 }
332 if (rc < 0)
333 return rc;
334 }
335
336 return ret;
337}
338
339static bool disable_1tb_segments = false;
340
341static int __init parse_disable_1tb_segments(char *p)
342{
343 disable_1tb_segments = true;
344 return 0;
345}
346early_param("disable_1tb_segments", parse_disable_1tb_segments);
347
348static int __init htab_dt_scan_seg_sizes(unsigned long node,
349 const char *uname, int depth,
350 void *data)
351{
352 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
353 const __be32 *prop;
354 int size = 0;
355
356
357 if (type == NULL || strcmp(type, "cpu") != 0)
358 return 0;
359
360 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
361 if (prop == NULL)
362 return 0;
363 for (; size >= 4; size -= 4, ++prop) {
364 if (be32_to_cpu(prop[0]) == 40) {
365 DBG("1T segment support detected\n");
366
367 if (disable_1tb_segments) {
368 DBG("1T segments disabled by command line\n");
369 break;
370 }
371
372 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
373 return 1;
374 }
375 }
376 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
377 return 0;
378}
379
380static int __init get_idx_from_shift(unsigned int shift)
381{
382 int idx = -1;
383
384 switch (shift) {
385 case 0xc:
386 idx = MMU_PAGE_4K;
387 break;
388 case 0x10:
389 idx = MMU_PAGE_64K;
390 break;
391 case 0x14:
392 idx = MMU_PAGE_1M;
393 break;
394 case 0x18:
395 idx = MMU_PAGE_16M;
396 break;
397 case 0x22:
398 idx = MMU_PAGE_16G;
399 break;
400 }
401 return idx;
402}
403
404static int __init htab_dt_scan_page_sizes(unsigned long node,
405 const char *uname, int depth,
406 void *data)
407{
408 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
409 const __be32 *prop;
410 int size = 0;
411
412
413 if (type == NULL || strcmp(type, "cpu") != 0)
414 return 0;
415
416 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
417 if (!prop)
418 return 0;
419
420 pr_info("Page sizes from device-tree:\n");
421 size /= 4;
422 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
423 while(size > 0) {
424 unsigned int base_shift = be32_to_cpu(prop[0]);
425 unsigned int slbenc = be32_to_cpu(prop[1]);
426 unsigned int lpnum = be32_to_cpu(prop[2]);
427 struct mmu_psize_def *def;
428 int idx, base_idx;
429
430 size -= 3; prop += 3;
431 base_idx = get_idx_from_shift(base_shift);
432 if (base_idx < 0) {
433
434 prop += lpnum * 2; size -= lpnum * 2;
435 continue;
436 }
437 def = &mmu_psize_defs[base_idx];
438 if (base_idx == MMU_PAGE_16M)
439 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
440
441 def->shift = base_shift;
442 if (base_shift <= 23)
443 def->avpnm = 0;
444 else
445 def->avpnm = (1 << (base_shift - 23)) - 1;
446 def->sllp = slbenc;
447
448
449
450
451 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
452 def->tlbiel = 1;
453 else
454 def->tlbiel = 0;
455
456 while (size > 0 && lpnum) {
457 unsigned int shift = be32_to_cpu(prop[0]);
458 int penc = be32_to_cpu(prop[1]);
459
460 prop += 2; size -= 2;
461 lpnum--;
462
463 idx = get_idx_from_shift(shift);
464 if (idx < 0)
465 continue;
466
467 if (penc == -1)
468 pr_err("Invalid penc for base_shift=%d "
469 "shift=%d\n", base_shift, shift);
470
471 def->penc[idx] = penc;
472 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
473 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
474 base_shift, shift, def->sllp,
475 def->avpnm, def->tlbiel, def->penc[idx]);
476 }
477 }
478
479 return 1;
480}
481
482#ifdef CONFIG_HUGETLB_PAGE
483
484
485
486
487static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
488 const char *uname, int depth,
489 void *data) {
490 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
491 const __be64 *addr_prop;
492 const __be32 *page_count_prop;
493 unsigned int expected_pages;
494 long unsigned int phys_addr;
495 long unsigned int block_size;
496
497
498 if (type == NULL || strcmp(type, "memory") != 0)
499 return 0;
500
501
502
503
504
505 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
506 if (page_count_prop == NULL)
507 return 0;
508 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
509 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
510 if (addr_prop == NULL)
511 return 0;
512 phys_addr = be64_to_cpu(addr_prop[0]);
513 block_size = be64_to_cpu(addr_prop[1]);
514 if (block_size != (16 * GB))
515 return 0;
516 printk(KERN_INFO "Huge page(16GB) memory: "
517 "addr = 0x%lX size = 0x%lX pages = %d\n",
518 phys_addr, block_size, expected_pages);
519 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
520 memblock_reserve(phys_addr, block_size * expected_pages);
521 pseries_add_gpage(phys_addr, block_size, expected_pages);
522 }
523 return 0;
524}
525#endif
526
527static void mmu_psize_set_default_penc(void)
528{
529 int bpsize, apsize;
530 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
531 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
532 mmu_psize_defs[bpsize].penc[apsize] = -1;
533}
534
535#ifdef CONFIG_PPC_64K_PAGES
536
537static bool might_have_hea(void)
538{
539
540
541
542
543
544#ifdef CONFIG_IBMEBUS
545 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
546 firmware_has_feature(FW_FEATURE_SPLPAR);
547#else
548 return false;
549#endif
550}
551
552#endif
553
554static void __init htab_scan_page_sizes(void)
555{
556 int rc;
557
558
559 mmu_psize_set_default_penc();
560
561
562 memcpy(mmu_psize_defs, mmu_psize_defaults,
563 sizeof(mmu_psize_defaults));
564
565
566
567
568 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
569 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
570
571
572
573
574 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
575 sizeof(mmu_psize_defaults_gp));
576 }
577
578#ifdef CONFIG_HUGETLB_PAGE
579 if (!hugetlb_disabled) {
580
581 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
582 }
583#endif
584}
585
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607
608static void init_hpte_page_sizes(void)
609{
610 long int ap, bp;
611 long int shift, penc;
612
613 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
614 if (!mmu_psize_defs[bp].shift)
615 continue;
616 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
617 penc = mmu_psize_defs[bp].penc[ap];
618 if (penc == -1 || !mmu_psize_defs[ap].shift)
619 continue;
620 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
621 if (shift <= 0)
622 continue;
623
624
625
626
627
628 while (penc < (1 << LP_BITS)) {
629 hpte_page_sizes[penc] = (ap << 4) | bp;
630 penc += 1 << shift;
631 }
632 }
633 }
634}
635
636static void __init htab_init_page_sizes(void)
637{
638 init_hpte_page_sizes();
639
640 if (!debug_pagealloc_enabled()) {
641
642
643
644
645 if (mmu_psize_defs[MMU_PAGE_16M].shift)
646 mmu_linear_psize = MMU_PAGE_16M;
647 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
648 mmu_linear_psize = MMU_PAGE_1M;
649 }
650
651#ifdef CONFIG_PPC_64K_PAGES
652
653
654
655
656
657
658
659
660
661 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
662 mmu_virtual_psize = MMU_PAGE_64K;
663 mmu_vmalloc_psize = MMU_PAGE_64K;
664 if (mmu_linear_psize == MMU_PAGE_4K)
665 mmu_linear_psize = MMU_PAGE_64K;
666 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
667
668
669
670
671
672 if (!might_have_hea())
673 mmu_io_psize = MMU_PAGE_64K;
674 } else
675 mmu_ci_restrictions = 1;
676 }
677#endif
678
679#ifdef CONFIG_SPARSEMEM_VMEMMAP
680
681
682
683
684 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
685 memblock_phys_mem_size() >= 0x40000000)
686 mmu_vmemmap_psize = MMU_PAGE_16M;
687 else
688 mmu_vmemmap_psize = mmu_virtual_psize;
689#endif
690
691 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
692 "virtual = %d, io = %d"
693#ifdef CONFIG_SPARSEMEM_VMEMMAP
694 ", vmemmap = %d"
695#endif
696 "\n",
697 mmu_psize_defs[mmu_linear_psize].shift,
698 mmu_psize_defs[mmu_virtual_psize].shift,
699 mmu_psize_defs[mmu_io_psize].shift
700#ifdef CONFIG_SPARSEMEM_VMEMMAP
701 ,mmu_psize_defs[mmu_vmemmap_psize].shift
702#endif
703 );
704}
705
706static int __init htab_dt_scan_pftsize(unsigned long node,
707 const char *uname, int depth,
708 void *data)
709{
710 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
711 const __be32 *prop;
712
713
714 if (type == NULL || strcmp(type, "cpu") != 0)
715 return 0;
716
717 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
718 if (prop != NULL) {
719
720 ppc64_pft_size = be32_to_cpu(prop[1]);
721 return 1;
722 }
723 return 0;
724}
725
726unsigned htab_shift_for_mem_size(unsigned long mem_size)
727{
728 unsigned memshift = __ilog2(mem_size);
729 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
730 unsigned pteg_shift;
731
732
733 if ((1UL << memshift) < mem_size)
734 memshift += 1;
735
736
737 pteg_shift = memshift - (pshift + 1);
738
739
740
741
742
743 return max(pteg_shift + 7, 18U);
744}
745
746static unsigned long __init htab_get_table_size(void)
747{
748
749
750
751
752
753 if (ppc64_pft_size == 0)
754 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
755 if (ppc64_pft_size)
756 return 1UL << ppc64_pft_size;
757
758 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
759}
760
761#ifdef CONFIG_MEMORY_HOTPLUG
762int resize_hpt_for_hotplug(unsigned long new_mem_size)
763{
764 unsigned target_hpt_shift;
765
766 if (!mmu_hash_ops.resize_hpt)
767 return 0;
768
769 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
770
771
772
773
774
775
776
777
778
779 if (target_hpt_shift > ppc64_pft_size ||
780 target_hpt_shift < ppc64_pft_size - 1)
781 return mmu_hash_ops.resize_hpt(target_hpt_shift);
782
783 return 0;
784}
785
786int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
787{
788 int rc;
789
790 if (end >= H_VMALLOC_START) {
791 pr_warn("Outside the supported range\n");
792 return -1;
793 }
794
795 rc = htab_bolt_mapping(start, end, __pa(start),
796 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
797 mmu_kernel_ssize);
798
799 if (rc < 0) {
800 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
801 mmu_kernel_ssize);
802 BUG_ON(rc2 && (rc2 != -ENOENT));
803 }
804 return rc;
805}
806
807int hash__remove_section_mapping(unsigned long start, unsigned long end)
808{
809 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
810 mmu_kernel_ssize);
811 WARN_ON(rc < 0);
812 return rc;
813}
814#endif
815
816static void __init hash_init_partition_table(phys_addr_t hash_table,
817 unsigned long htab_size)
818{
819 mmu_partition_table_init();
820
821
822
823
824
825 htab_size = __ilog2(htab_size) - 18;
826 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
827 pr_info("Partition table %p\n", partition_tb);
828}
829
830static void __init htab_initialize(void)
831{
832 unsigned long table;
833 unsigned long pteg_count;
834 unsigned long prot;
835 unsigned long base = 0, size = 0;
836 struct memblock_region *reg;
837
838 DBG(" -> htab_initialize()\n");
839
840 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
841 mmu_kernel_ssize = MMU_SEGSIZE_1T;
842 mmu_highuser_ssize = MMU_SEGSIZE_1T;
843 printk(KERN_INFO "Using 1TB segments\n");
844 }
845
846
847
848
849
850 htab_size_bytes = htab_get_table_size();
851 pteg_count = htab_size_bytes >> 7;
852
853 htab_hash_mask = pteg_count - 1;
854
855 if (firmware_has_feature(FW_FEATURE_LPAR) ||
856 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
857
858 htab_address = NULL;
859 _SDR1 = 0;
860
861
862
863
864 if (cpu_has_feature(CPU_FTR_ARCH_300))
865 register_process_table(0, 0, 0);
866#ifdef CONFIG_FA_DUMP
867
868
869
870
871
872
873 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
874 mmu_hash_ops.hpte_clear_all();
875#endif
876 } else {
877 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
878
879#ifdef CONFIG_PPC_CELL
880
881
882
883
884
885 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
886 limit = 0x80000000;
887 pr_info("Hash table forced below 2G for Axon IOMMU\n");
888 }
889#endif
890
891 table = memblock_phys_alloc_range(htab_size_bytes,
892 htab_size_bytes,
893 0, limit);
894 if (!table)
895 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
896 &htab_size_bytes, &limit);
897
898 DBG("Hash table allocated at %lx, size: %lx\n", table,
899 htab_size_bytes);
900
901 htab_address = __va(table);
902
903
904 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
905
906
907 memset((void *)table, 0, htab_size_bytes);
908
909 if (!cpu_has_feature(CPU_FTR_ARCH_300))
910
911 mtspr(SPRN_SDR1, _SDR1);
912 else
913 hash_init_partition_table(table, htab_size_bytes);
914 }
915
916 prot = pgprot_val(PAGE_KERNEL);
917
918#ifdef CONFIG_DEBUG_PAGEALLOC
919 if (debug_pagealloc_enabled()) {
920 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
921 linear_map_hash_slots = memblock_alloc_try_nid(
922 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
923 ppc64_rma_size, NUMA_NO_NODE);
924 if (!linear_map_hash_slots)
925 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
926 __func__, linear_map_hash_count, &ppc64_rma_size);
927 }
928#endif
929
930
931 for_each_memblock(memory, reg) {
932 base = (unsigned long)__va(reg->base);
933 size = reg->size;
934
935 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
936 base, size, prot);
937
938 if ((base + size) >= H_VMALLOC_START) {
939 pr_warn("Outside the supported range\n");
940 continue;
941 }
942
943 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
944 prot, mmu_linear_psize, mmu_kernel_ssize));
945 }
946 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
947
948
949
950
951
952
953
954
955 if (tce_alloc_start) {
956 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
957 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
958
959 if (base + size >= tce_alloc_start)
960 tce_alloc_start = base + size + 1;
961
962 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
963 __pa(tce_alloc_start), prot,
964 mmu_linear_psize, mmu_kernel_ssize));
965 }
966
967
968 DBG(" <- htab_initialize()\n");
969}
970#undef KB
971#undef MB
972
973void __init hash__early_init_devtree(void)
974{
975
976 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
977
978
979 htab_scan_page_sizes();
980}
981
982static struct hash_mm_context init_hash_mm_context;
983void __init hash__early_init_mmu(void)
984{
985#ifndef CONFIG_PPC_64K_PAGES
986
987
988
989
990
991
992
993
994
995
996
997 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
998#endif
999
1000 htab_init_page_sizes();
1001
1002
1003
1004
1005 __pte_frag_nr = H_PTE_FRAG_NR;
1006 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1007 __pmd_frag_nr = H_PMD_FRAG_NR;
1008 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1009
1010 __pte_index_size = H_PTE_INDEX_SIZE;
1011 __pmd_index_size = H_PMD_INDEX_SIZE;
1012 __pud_index_size = H_PUD_INDEX_SIZE;
1013 __pgd_index_size = H_PGD_INDEX_SIZE;
1014 __pud_cache_index = H_PUD_CACHE_INDEX;
1015 __pte_table_size = H_PTE_TABLE_SIZE;
1016 __pmd_table_size = H_PMD_TABLE_SIZE;
1017 __pud_table_size = H_PUD_TABLE_SIZE;
1018 __pgd_table_size = H_PGD_TABLE_SIZE;
1019
1020
1021
1022
1023 __pmd_val_bits = HASH_PMD_VAL_BITS;
1024 __pud_val_bits = HASH_PUD_VAL_BITS;
1025 __pgd_val_bits = HASH_PGD_VAL_BITS;
1026
1027 __kernel_virt_start = H_KERN_VIRT_START;
1028 __vmalloc_start = H_VMALLOC_START;
1029 __vmalloc_end = H_VMALLOC_END;
1030 __kernel_io_start = H_KERN_IO_START;
1031 __kernel_io_end = H_KERN_IO_END;
1032 vmemmap = (struct page *)H_VMEMMAP_START;
1033 ioremap_bot = IOREMAP_BASE;
1034
1035#ifdef CONFIG_PCI
1036 pci_io_base = ISA_IO_BASE;
1037#endif
1038
1039
1040 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1041 ps3_early_mm_init();
1042 else if (firmware_has_feature(FW_FEATURE_LPAR))
1043 hpte_init_pseries();
1044 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1045 hpte_init_native();
1046
1047 if (!mmu_hash_ops.hpte_insert)
1048 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1049
1050
1051
1052
1053
1054
1055 htab_initialize();
1056
1057 init_mm.context.hash_context = &init_hash_mm_context;
1058 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1059
1060 pr_info("Initializing hash mmu with SLB\n");
1061
1062 slb_initialize();
1063
1064 if (cpu_has_feature(CPU_FTR_ARCH_206)
1065 && cpu_has_feature(CPU_FTR_HVMODE))
1066 tlbiel_all();
1067}
1068
1069#ifdef CONFIG_SMP
1070void hash__early_init_mmu_secondary(void)
1071{
1072
1073 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1074
1075 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1076 mtspr(SPRN_SDR1, _SDR1);
1077 else
1078 mtspr(SPRN_PTCR,
1079 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1080 }
1081
1082 slb_initialize();
1083
1084 if (cpu_has_feature(CPU_FTR_ARCH_206)
1085 && cpu_has_feature(CPU_FTR_HVMODE))
1086 tlbiel_all();
1087}
1088#endif
1089
1090
1091
1092
1093unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1094{
1095 struct page *page;
1096
1097 if (!pfn_valid(pte_pfn(pte)))
1098 return pp;
1099
1100 page = pte_page(pte);
1101
1102
1103 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1104 if (trap == 0x400) {
1105 flush_dcache_icache_page(page);
1106 set_bit(PG_arch_1, &page->flags);
1107 } else
1108 pp |= HPTE_R_N;
1109 }
1110 return pp;
1111}
1112
1113#ifdef CONFIG_PPC_MM_SLICES
1114static unsigned int get_paca_psize(unsigned long addr)
1115{
1116 unsigned char *psizes;
1117 unsigned long index, mask_index;
1118
1119 if (addr < SLICE_LOW_TOP) {
1120 psizes = get_paca()->mm_ctx_low_slices_psize;
1121 index = GET_LOW_SLICE_INDEX(addr);
1122 } else {
1123 psizes = get_paca()->mm_ctx_high_slices_psize;
1124 index = GET_HIGH_SLICE_INDEX(addr);
1125 }
1126 mask_index = index & 0x1;
1127 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1128}
1129
1130#else
1131unsigned int get_paca_psize(unsigned long addr)
1132{
1133 return get_paca()->mm_ctx_user_psize;
1134}
1135#endif
1136
1137
1138
1139
1140
1141#ifdef CONFIG_PPC_64K_PAGES
1142void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1143{
1144 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1145 return;
1146 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1147 copro_flush_all_slbs(mm);
1148 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1149
1150 copy_mm_to_paca(mm);
1151 slb_flush_and_restore_bolted();
1152 }
1153}
1154#endif
1155
1156#ifdef CONFIG_PPC_SUBPAGE_PROT
1157
1158
1159
1160
1161
1162
1163
1164static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1165{
1166 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1167 u32 spp = 0;
1168 u32 **sbpm, *sbpp;
1169
1170 if (!spt)
1171 return 0;
1172
1173 if (ea >= spt->maxaddr)
1174 return 0;
1175 if (ea < 0x100000000UL) {
1176
1177 sbpm = spt->low_prot;
1178 } else {
1179 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1180 if (!sbpm)
1181 return 0;
1182 }
1183 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1184 if (!sbpp)
1185 return 0;
1186 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1187
1188
1189 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1190
1191
1192
1193
1194
1195
1196
1197 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1198 return spp;
1199}
1200
1201#else
1202static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1203{
1204 return 0;
1205}
1206#endif
1207
1208void hash_failure_debug(unsigned long ea, unsigned long access,
1209 unsigned long vsid, unsigned long trap,
1210 int ssize, int psize, int lpsize, unsigned long pte)
1211{
1212 if (!printk_ratelimit())
1213 return;
1214 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1215 ea, access, current->comm);
1216 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1217 trap, vsid, ssize, psize, lpsize, pte);
1218}
1219
1220static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1221 int psize, bool user_region)
1222{
1223 if (user_region) {
1224 if (psize != get_paca_psize(ea)) {
1225 copy_mm_to_paca(mm);
1226 slb_flush_and_restore_bolted();
1227 }
1228 } else if (get_paca()->vmalloc_sllp !=
1229 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1230 get_paca()->vmalloc_sllp =
1231 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1232 slb_vmalloc_update();
1233 }
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1244 unsigned long access, unsigned long trap,
1245 unsigned long flags)
1246{
1247 bool is_thp;
1248 enum ctx_state prev_state = exception_enter();
1249 pgd_t *pgdir;
1250 unsigned long vsid;
1251 pte_t *ptep;
1252 unsigned hugeshift;
1253 int rc, user_region = 0;
1254 int psize, ssize;
1255
1256 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1257 ea, access, trap);
1258 trace_hash_fault(ea, access, trap);
1259
1260
1261 switch (get_region_id(ea)) {
1262 case USER_REGION_ID:
1263 user_region = 1;
1264 if (! mm) {
1265 DBG_LOW(" user region with no mm !\n");
1266 rc = 1;
1267 goto bail;
1268 }
1269 psize = get_slice_psize(mm, ea);
1270 ssize = user_segment_size(ea);
1271 vsid = get_user_vsid(&mm->context, ea, ssize);
1272 break;
1273 case VMALLOC_REGION_ID:
1274 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1275 psize = mmu_vmalloc_psize;
1276 ssize = mmu_kernel_ssize;
1277 break;
1278
1279 case IO_REGION_ID:
1280 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1281 psize = mmu_io_psize;
1282 ssize = mmu_kernel_ssize;
1283 break;
1284 default:
1285
1286
1287
1288
1289 rc = 1;
1290 goto bail;
1291 }
1292 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1293
1294
1295 if (!vsid) {
1296 DBG_LOW("Bad address!\n");
1297 rc = 1;
1298 goto bail;
1299 }
1300
1301 pgdir = mm->pgd;
1302 if (pgdir == NULL) {
1303 rc = 1;
1304 goto bail;
1305 }
1306
1307
1308 if (user_region && mm_is_thread_local(mm))
1309 flags |= HPTE_LOCAL_UPDATE;
1310
1311#ifndef CONFIG_PPC_64K_PAGES
1312
1313
1314
1315
1316
1317
1318
1319
1320 if (psize != MMU_PAGE_4K)
1321 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1322#endif
1323
1324
1325 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1326 if (ptep == NULL || !pte_present(*ptep)) {
1327 DBG_LOW(" no PTE !\n");
1328 rc = 1;
1329 goto bail;
1330 }
1331
1332
1333 access |= _PAGE_PRESENT;
1334
1335
1336
1337
1338
1339 if (!check_pte_access(access, pte_val(*ptep))) {
1340 DBG_LOW(" no access !\n");
1341 rc = 1;
1342 goto bail;
1343 }
1344
1345 if (hugeshift) {
1346 if (is_thp)
1347 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1348 trap, flags, ssize, psize);
1349#ifdef CONFIG_HUGETLB_PAGE
1350 else
1351 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1352 flags, ssize, hugeshift, psize);
1353#else
1354 else {
1355
1356
1357
1358
1359 rc = 1;
1360 WARN_ON(1);
1361 }
1362#endif
1363 if (current->mm == mm)
1364 check_paca_psize(ea, mm, psize, user_region);
1365
1366 goto bail;
1367 }
1368
1369#ifndef CONFIG_PPC_64K_PAGES
1370 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1371#else
1372 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1373 pte_val(*(ptep + PTRS_PER_PTE)));
1374#endif
1375
1376#ifdef CONFIG_PPC_64K_PAGES
1377
1378 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1379 demote_segment_4k(mm, ea);
1380 psize = MMU_PAGE_4K;
1381 }
1382
1383
1384
1385
1386
1387 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1388 if (user_region) {
1389 demote_segment_4k(mm, ea);
1390 psize = MMU_PAGE_4K;
1391 } else if (ea < VMALLOC_END) {
1392
1393
1394
1395
1396
1397 printk(KERN_ALERT "Reducing vmalloc segment "
1398 "to 4kB pages because of "
1399 "non-cacheable mapping\n");
1400 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1401 copro_flush_all_slbs(mm);
1402 }
1403 }
1404
1405#endif
1406
1407 if (current->mm == mm)
1408 check_paca_psize(ea, mm, psize, user_region);
1409
1410#ifdef CONFIG_PPC_64K_PAGES
1411 if (psize == MMU_PAGE_64K)
1412 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1413 flags, ssize);
1414 else
1415#endif
1416 {
1417 int spp = subpage_protection(mm, ea);
1418 if (access & spp)
1419 rc = -2;
1420 else
1421 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1422 flags, ssize, spp);
1423 }
1424
1425
1426
1427
1428
1429 if (rc == -1)
1430 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1431 psize, pte_val(*ptep));
1432#ifndef CONFIG_PPC_64K_PAGES
1433 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1434#else
1435 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1436 pte_val(*(ptep + PTRS_PER_PTE)));
1437#endif
1438 DBG_LOW(" -> rc=%d\n", rc);
1439
1440bail:
1441 exception_exit(prev_state);
1442 return rc;
1443}
1444EXPORT_SYMBOL_GPL(hash_page_mm);
1445
1446int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1447 unsigned long dsisr)
1448{
1449 unsigned long flags = 0;
1450 struct mm_struct *mm = current->mm;
1451
1452 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1453 (get_region_id(ea) == IO_REGION_ID))
1454 mm = &init_mm;
1455
1456 if (dsisr & DSISR_NOHPTE)
1457 flags |= HPTE_NOHPTE_UPDATE;
1458
1459 return hash_page_mm(mm, ea, access, trap, flags);
1460}
1461EXPORT_SYMBOL_GPL(hash_page);
1462
1463int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1464 unsigned long dsisr)
1465{
1466 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1467 unsigned long flags = 0;
1468 struct mm_struct *mm = current->mm;
1469 unsigned int region_id = get_region_id(ea);
1470
1471 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1472 mm = &init_mm;
1473
1474 if (dsisr & DSISR_NOHPTE)
1475 flags |= HPTE_NOHPTE_UPDATE;
1476
1477 if (dsisr & DSISR_ISSTORE)
1478 access |= _PAGE_WRITE;
1479
1480
1481
1482
1483
1484
1485
1486
1487 access |= _PAGE_PRIVILEGED;
1488 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1489 access &= ~_PAGE_PRIVILEGED;
1490
1491 if (trap == 0x400)
1492 access |= _PAGE_EXEC;
1493
1494 return hash_page_mm(mm, ea, access, trap, flags);
1495}
1496
1497#ifdef CONFIG_PPC_MM_SLICES
1498static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1499{
1500 int psize = get_slice_psize(mm, ea);
1501
1502
1503 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1504 return false;
1505
1506
1507
1508
1509 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1510 return false;
1511
1512 return true;
1513}
1514#else
1515static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1516{
1517 return true;
1518}
1519#endif
1520
1521void hash_preload(struct mm_struct *mm, unsigned long ea,
1522 bool is_exec, unsigned long trap)
1523{
1524 int hugepage_shift;
1525 unsigned long vsid;
1526 pgd_t *pgdir;
1527 pte_t *ptep;
1528 unsigned long flags;
1529 int rc, ssize, update_flags = 0;
1530 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1531
1532 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1533
1534 if (!should_hash_preload(mm, ea))
1535 return;
1536
1537 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1538 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1539
1540
1541 pgdir = mm->pgd;
1542 if (pgdir == NULL)
1543 return;
1544
1545
1546 ssize = user_segment_size(ea);
1547 vsid = get_user_vsid(&mm->context, ea, ssize);
1548 if (!vsid)
1549 return;
1550
1551
1552
1553
1554 local_irq_save(flags);
1555
1556
1557
1558
1559
1560 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1561 if (!ptep)
1562 goto out_exit;
1563
1564 WARN_ON(hugepage_shift);
1565#ifdef CONFIG_PPC_64K_PAGES
1566
1567
1568
1569
1570
1571
1572 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1573 goto out_exit;
1574#endif
1575
1576
1577 if (mm_is_thread_local(mm))
1578 update_flags |= HPTE_LOCAL_UPDATE;
1579
1580
1581#ifdef CONFIG_PPC_64K_PAGES
1582 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1583 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1584 update_flags, ssize);
1585 else
1586#endif
1587 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1588 ssize, subpage_protection(mm, ea));
1589
1590
1591
1592
1593 if (rc == -1)
1594 hash_failure_debug(ea, access, vsid, trap, ssize,
1595 mm_ctx_user_psize(&mm->context),
1596 mm_ctx_user_psize(&mm->context),
1597 pte_val(*ptep));
1598out_exit:
1599 local_irq_restore(flags);
1600}
1601
1602#ifdef CONFIG_PPC_MEM_KEYS
1603
1604
1605
1606
1607u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1608{
1609 pte_t *ptep;
1610 u16 pkey = 0;
1611 unsigned long flags;
1612
1613 if (!mm || !mm->pgd)
1614 return 0;
1615
1616 local_irq_save(flags);
1617 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1618 if (ptep)
1619 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1620 local_irq_restore(flags);
1621
1622 return pkey;
1623}
1624#endif
1625
1626#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1627static inline void tm_flush_hash_page(int local)
1628{
1629
1630
1631
1632
1633
1634
1635
1636
1637 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1638 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1639 tm_enable();
1640 tm_abort(TM_CAUSE_TLBI);
1641 }
1642}
1643#else
1644static inline void tm_flush_hash_page(int local)
1645{
1646}
1647#endif
1648
1649
1650
1651
1652
1653unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1654 int ssize, real_pte_t rpte, unsigned int subpg_index)
1655{
1656 unsigned long hash, gslot, hidx;
1657
1658 hash = hpt_hash(vpn, shift, ssize);
1659 hidx = __rpte_to_hidx(rpte, subpg_index);
1660 if (hidx & _PTEIDX_SECONDARY)
1661 hash = ~hash;
1662 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1663 gslot += hidx & _PTEIDX_GROUP_IX;
1664 return gslot;
1665}
1666
1667
1668
1669
1670
1671void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1672 unsigned long flags)
1673{
1674 unsigned long index, shift, gslot;
1675 int local = flags & HPTE_LOCAL_UPDATE;
1676
1677 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1678 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1679 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1680 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1681
1682
1683
1684
1685 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1686 ssize, local);
1687 } pte_iterate_hashed_end();
1688
1689 tm_flush_hash_page(local);
1690}
1691
1692#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1693void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1694 pmd_t *pmdp, unsigned int psize, int ssize,
1695 unsigned long flags)
1696{
1697 int i, max_hpte_count, valid;
1698 unsigned long s_addr;
1699 unsigned char *hpte_slot_array;
1700 unsigned long hidx, shift, vpn, hash, slot;
1701 int local = flags & HPTE_LOCAL_UPDATE;
1702
1703 s_addr = addr & HPAGE_PMD_MASK;
1704 hpte_slot_array = get_hpte_slot_array(pmdp);
1705
1706
1707
1708
1709
1710 if (!hpte_slot_array)
1711 return;
1712
1713 if (mmu_hash_ops.hugepage_invalidate) {
1714 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1715 psize, ssize, local);
1716 goto tm_abort;
1717 }
1718
1719
1720
1721 shift = mmu_psize_defs[psize].shift;
1722 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1723 for (i = 0; i < max_hpte_count; i++) {
1724
1725
1726
1727
1728 valid = hpte_valid(hpte_slot_array, i);
1729 if (!valid)
1730 continue;
1731 hidx = hpte_hash_index(hpte_slot_array, i);
1732
1733
1734 addr = s_addr + (i * (1ul << shift));
1735 vpn = hpt_vpn(addr, vsid, ssize);
1736 hash = hpt_hash(vpn, shift, ssize);
1737 if (hidx & _PTEIDX_SECONDARY)
1738 hash = ~hash;
1739
1740 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1741 slot += hidx & _PTEIDX_GROUP_IX;
1742 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1743 MMU_PAGE_16M, ssize, local);
1744 }
1745tm_abort:
1746 tm_flush_hash_page(local);
1747}
1748#endif
1749
1750void flush_hash_range(unsigned long number, int local)
1751{
1752 if (mmu_hash_ops.flush_hash_range)
1753 mmu_hash_ops.flush_hash_range(number, local);
1754 else {
1755 int i;
1756 struct ppc64_tlb_batch *batch =
1757 this_cpu_ptr(&ppc64_tlb_batch);
1758
1759 for (i = 0; i < number; i++)
1760 flush_hash_page(batch->vpn[i], batch->pte[i],
1761 batch->psize, batch->ssize, local);
1762 }
1763}
1764
1765
1766
1767
1768
1769void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1770{
1771 enum ctx_state prev_state = exception_enter();
1772
1773 if (user_mode(regs)) {
1774#ifdef CONFIG_PPC_SUBPAGE_PROT
1775 if (rc == -2)
1776 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1777 else
1778#endif
1779 _exception(SIGBUS, regs, BUS_ADRERR, address);
1780 } else
1781 bad_page_fault(regs, address, SIGBUS);
1782
1783 exception_exit(prev_state);
1784}
1785
1786long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1787 unsigned long pa, unsigned long rflags,
1788 unsigned long vflags, int psize, int ssize)
1789{
1790 unsigned long hpte_group;
1791 long slot;
1792
1793repeat:
1794 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1795
1796
1797 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1798 psize, psize, ssize);
1799
1800
1801 if (unlikely(slot == -1)) {
1802 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1803 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1804 vflags | HPTE_V_SECONDARY,
1805 psize, psize, ssize);
1806 if (slot == -1) {
1807 if (mftb() & 0x1)
1808 hpte_group = (hash & htab_hash_mask) *
1809 HPTES_PER_GROUP;
1810
1811 mmu_hash_ops.hpte_remove(hpte_group);
1812 goto repeat;
1813 }
1814 }
1815
1816 return slot;
1817}
1818
1819#ifdef CONFIG_DEBUG_PAGEALLOC
1820static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1821{
1822 unsigned long hash;
1823 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1824 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1825 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1826 long ret;
1827
1828 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1829
1830
1831 if (!vsid)
1832 return;
1833
1834 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1835 HPTE_V_BOLTED,
1836 mmu_linear_psize, mmu_kernel_ssize);
1837
1838 BUG_ON (ret < 0);
1839 spin_lock(&linear_map_hash_lock);
1840 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1841 linear_map_hash_slots[lmi] = ret | 0x80;
1842 spin_unlock(&linear_map_hash_lock);
1843}
1844
1845static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1846{
1847 unsigned long hash, hidx, slot;
1848 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1849 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1850
1851 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1852 spin_lock(&linear_map_hash_lock);
1853 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1854 hidx = linear_map_hash_slots[lmi] & 0x7f;
1855 linear_map_hash_slots[lmi] = 0;
1856 spin_unlock(&linear_map_hash_lock);
1857 if (hidx & _PTEIDX_SECONDARY)
1858 hash = ~hash;
1859 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1860 slot += hidx & _PTEIDX_GROUP_IX;
1861 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1862 mmu_linear_psize,
1863 mmu_kernel_ssize, 0);
1864}
1865
1866void __kernel_map_pages(struct page *page, int numpages, int enable)
1867{
1868 unsigned long flags, vaddr, lmi;
1869 int i;
1870
1871 local_irq_save(flags);
1872 for (i = 0; i < numpages; i++, page++) {
1873 vaddr = (unsigned long)page_address(page);
1874 lmi = __pa(vaddr) >> PAGE_SHIFT;
1875 if (lmi >= linear_map_hash_count)
1876 continue;
1877 if (enable)
1878 kernel_map_linear_page(vaddr, lmi);
1879 else
1880 kernel_unmap_linear_page(vaddr, lmi);
1881 }
1882 local_irq_restore(flags);
1883}
1884#endif
1885
1886void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1887 phys_addr_t first_memblock_size)
1888{
1889
1890
1891
1892
1893 BUG_ON(first_memblock_base != 0);
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1910 ppc64_rma_size = first_memblock_size;
1911 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1912 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1913 else
1914 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1915 1UL << SID_SHIFT_1T);
1916
1917
1918 memblock_set_current_limit(ppc64_rma_size);
1919 } else {
1920 ppc64_rma_size = ULONG_MAX;
1921 }
1922}
1923
1924#ifdef CONFIG_DEBUG_FS
1925
1926static int hpt_order_get(void *data, u64 *val)
1927{
1928 *val = ppc64_pft_size;
1929 return 0;
1930}
1931
1932static int hpt_order_set(void *data, u64 val)
1933{
1934 if (!mmu_hash_ops.resize_hpt)
1935 return -ENODEV;
1936
1937 return mmu_hash_ops.resize_hpt(val);
1938}
1939
1940DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1941
1942static int __init hash64_debugfs(void)
1943{
1944 if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
1945 NULL, &fops_hpt_order)) {
1946 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1947 }
1948
1949 return 0;
1950}
1951machine_device_initcall(pseries, hash64_debugfs);
1952#endif
1953
1954void __init print_system_hash_info(void)
1955{
1956 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
1957
1958 if (htab_hash_mask)
1959 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
1960 pr_info("kernel vmalloc start = 0x%lx\n", KERN_VIRT_START);
1961 pr_info("kernel IO start = 0x%lx\n", KERN_IO_START);
1962 pr_info("kernel vmemmap start = 0x%lx\n", (unsigned long)vmemmap);
1963}
1964