LXR linux/arch/powerpc/platforms/85xx/common.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Routines common to most mpc85xx-based boards.
   4 */
   5
   6#include <linux/of_irq.h>
   7#include <linux/of_platform.h>
   8
   9#include <asm/fsl_pm.h>
  10#include <soc/fsl/qe/qe.h>
  11#include <sysdev/cpm2_pic.h>
  12
  13#include "mpc85xx.h"
  14
  15const struct fsl_pm_ops *qoriq_pm_ops;
  16
  17static const struct of_device_id mpc85xx_common_ids[] __initconst = {
  18        { .type = "soc", },
  19        { .compatible = "soc", },
  20        { .compatible = "simple-bus", },
  21        { .name = "cpm", },
  22        { .name = "localbus", },
  23        { .compatible = "gianfar", },
  24        { .compatible = "fsl,qe", },
  25        { .compatible = "fsl,cpm2", },
  26        { .compatible = "fsl,srio", },
  27        /* So that the DMA channel nodes can be probed individually: */
  28        { .compatible = "fsl,eloplus-dma", },
  29        /* For the PMC driver */
  30        { .compatible = "fsl,mpc8548-guts", },
  31        /* Probably unnecessary? */
  32        { .compatible = "gpio-leds", },
  33        /* For all PCI controllers */
  34        { .compatible = "fsl,mpc8540-pci", },
  35        { .compatible = "fsl,mpc8548-pcie", },
  36        { .compatible = "fsl,p1022-pcie", },
  37        { .compatible = "fsl,p1010-pcie", },
  38        { .compatible = "fsl,p1023-pcie", },
  39        { .compatible = "fsl,p4080-pcie", },
  40        { .compatible = "fsl,qoriq-pcie-v2.4", },
  41        { .compatible = "fsl,qoriq-pcie-v2.3", },
  42        { .compatible = "fsl,qoriq-pcie-v2.2", },
  43        { .compatible = "fsl,fman", },
  44        {},
  45};
  46
  47int __init mpc85xx_common_publish_devices(void)
  48{
  49        return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
  50}
  51#ifdef CONFIG_CPM2
  52static void cpm2_cascade(struct irq_desc *desc)
  53{
  54        struct irq_chip *chip = irq_desc_get_chip(desc);
  55        int cascade_irq;
  56
  57        while ((cascade_irq = cpm2_get_irq()) >= 0)
  58                generic_handle_irq(cascade_irq);
  59
  60        chip->irq_eoi(&desc->irq_data);
  61}
  62
  63
  64void __init mpc85xx_cpm2_pic_init(void)
  65{
  66        struct device_node *np;
  67        int irq;
  68
  69        /* Setup CPM2 PIC */
  70        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
  71        if (np == NULL) {
  72                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
  73                return;
  74        }
  75        irq = irq_of_parse_and_map(np, 0);
  76        if (!irq) {
  77                of_node_put(np);
  78                printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
  79                return;
  80        }
  81
  82        cpm2_pic_init(np);
  83        of_node_put(np);
  84        irq_set_chained_handler(irq, cpm2_cascade);
  85}
  86#endif
  87
  88#ifdef CONFIG_QUICC_ENGINE
  89void __init mpc85xx_qe_init(void)
  90{
  91        struct device_node *np;
  92
  93        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
  94        if (!np) {
  95                np = of_find_node_by_name(NULL, "qe");
  96                if (!np) {
  97                        pr_err("%s: Could not find Quicc Engine node\n",
  98                                        __func__);
  99                        return;
 100                }
 101        }
 102
 103        if (!of_device_is_available(np)) {
 104                of_node_put(np);
 105                return;
 106        }
 107
 108        of_node_put(np);
 109
 110}
 111
 112void __init mpc85xx_qe_par_io_init(void)
 113{
 114        struct device_node *np;
 115
 116        np = of_find_node_by_name(NULL, "par_io");
 117        if (np) {
 118                struct device_node *ucc;
 119
 120                par_io_init(np);
 121                of_node_put(np);
 122
 123                for_each_node_by_name(ucc, "ucc")
 124                        par_io_of_config(ucc);
 125
 126        }
 127}
 128#endif
 129