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15#include <linux/cpu.h>
16#include <linux/errno.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/unistd.h>
22#include <linux/user.h>
23#include <linux/tty.h>
24#include <linux/major.h>
25#include <linux/interrupt.h>
26#include <linux/reboot.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/console.h>
30#include <linux/pci.h>
31#include <linux/utsname.h>
32#include <linux/adb.h>
33#include <linux/export.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/seq_file.h>
37#include <linux/root_dev.h>
38#include <linux/of.h>
39#include <linux/of_pci.h>
40#include <linux/memblock.h>
41#include <linux/swiotlb.h>
42
43#include <asm/mmu.h>
44#include <asm/processor.h>
45#include <asm/io.h>
46#include <asm/pgtable.h>
47#include <asm/prom.h>
48#include <asm/rtas.h>
49#include <asm/pci-bridge.h>
50#include <asm/iommu.h>
51#include <asm/dma.h>
52#include <asm/machdep.h>
53#include <asm/irq.h>
54#include <asm/time.h>
55#include <asm/nvram.h>
56#include <asm/pmc.h>
57#include <asm/xics.h>
58#include <asm/xive.h>
59#include <asm/ppc-pci.h>
60#include <asm/i8259.h>
61#include <asm/udbg.h>
62#include <asm/smp.h>
63#include <asm/firmware.h>
64#include <asm/eeh.h>
65#include <asm/reg.h>
66#include <asm/plpar_wrappers.h>
67#include <asm/kexec.h>
68#include <asm/isa-bridge.h>
69#include <asm/security_features.h>
70#include <asm/asm-const.h>
71#include <asm/swiotlb.h>
72
73#include "pseries.h"
74#include "../../../../drivers/pci/pci.h"
75
76int CMO_PrPSP = -1;
77int CMO_SecPSP = -1;
78unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
79EXPORT_SYMBOL(CMO_PageSize);
80
81int fwnmi_active;
82
83static void pSeries_show_cpuinfo(struct seq_file *m)
84{
85 struct device_node *root;
86 const char *model = "";
87
88 root = of_find_node_by_path("/");
89 if (root)
90 model = of_get_property(root, "model", NULL);
91 seq_printf(m, "machine\t\t: CHRP %s\n", model);
92 of_node_put(root);
93 if (radix_enabled())
94 seq_printf(m, "MMU\t\t: Radix\n");
95 else
96 seq_printf(m, "MMU\t\t: Hash\n");
97}
98
99
100
101
102static void __init fwnmi_init(void)
103{
104 unsigned long system_reset_addr, machine_check_addr;
105 u8 *mce_data_buf;
106 unsigned int i;
107 int nr_cpus = num_possible_cpus();
108#ifdef CONFIG_PPC_BOOK3S_64
109 struct slb_entry *slb_ptr;
110 size_t size;
111#endif
112
113 int ibm_nmi_register = rtas_token("ibm,nmi-register");
114 if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE)
115 return;
116
117
118
119 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START;
120 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START;
121
122 if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr,
123 machine_check_addr))
124 fwnmi_active = 1;
125
126
127
128
129
130
131 mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus,
132 RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT,
133 ppc64_rma_size, NUMA_NO_NODE);
134 if (!mce_data_buf)
135 panic("Failed to allocate %d bytes below %pa for MCE buffer\n",
136 RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size);
137
138 for_each_possible_cpu(i) {
139 paca_ptrs[i]->mce_data_buf = mce_data_buf +
140 (RTAS_ERROR_LOG_MAX * i);
141 }
142
143#ifdef CONFIG_PPC_BOOK3S_64
144
145 size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus;
146 slb_ptr = memblock_alloc_try_nid_raw(size, sizeof(struct slb_entry),
147 MEMBLOCK_LOW_LIMIT, ppc64_rma_size,
148 NUMA_NO_NODE);
149 if (!slb_ptr)
150 panic("Failed to allocate %zu bytes below %pa for slb area\n",
151 size, &ppc64_rma_size);
152
153 for_each_possible_cpu(i)
154 paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i);
155#endif
156}
157
158static void pseries_8259_cascade(struct irq_desc *desc)
159{
160 struct irq_chip *chip = irq_desc_get_chip(desc);
161 unsigned int cascade_irq = i8259_irq();
162
163 if (cascade_irq)
164 generic_handle_irq(cascade_irq);
165
166 chip->irq_eoi(&desc->irq_data);
167}
168
169static void __init pseries_setup_i8259_cascade(void)
170{
171 struct device_node *np, *old, *found = NULL;
172 unsigned int cascade;
173 const u32 *addrp;
174 unsigned long intack = 0;
175 int naddr;
176
177 for_each_node_by_type(np, "interrupt-controller") {
178 if (of_device_is_compatible(np, "chrp,iic")) {
179 found = np;
180 break;
181 }
182 }
183
184 if (found == NULL) {
185 printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
186 return;
187 }
188
189 cascade = irq_of_parse_and_map(found, 0);
190 if (!cascade) {
191 printk(KERN_ERR "pic: failed to map cascade interrupt");
192 return;
193 }
194 pr_debug("pic: cascade mapped to irq %d\n", cascade);
195
196 for (old = of_node_get(found); old != NULL ; old = np) {
197 np = of_get_parent(old);
198 of_node_put(old);
199 if (np == NULL)
200 break;
201 if (!of_node_name_eq(np, "pci"))
202 continue;
203 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
204 if (addrp == NULL)
205 continue;
206 naddr = of_n_addr_cells(np);
207 intack = addrp[naddr-1];
208 if (naddr > 1)
209 intack |= ((unsigned long)addrp[naddr-2]) << 32;
210 }
211 if (intack)
212 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
213 i8259_init(found, intack);
214 of_node_put(found);
215 irq_set_chained_handler(cascade, pseries_8259_cascade);
216}
217
218static void __init pseries_init_irq(void)
219{
220
221 if (!xive_spapr_init()) {
222 xics_init();
223 pseries_setup_i8259_cascade();
224 }
225}
226
227static void pseries_lpar_enable_pmcs(void)
228{
229 unsigned long set, reset;
230
231 set = 1UL << 63;
232 reset = 0;
233 plpar_hcall_norets(H_PERFMON, set, reset);
234}
235
236static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
237{
238 struct of_reconfig_data *rd = data;
239 struct device_node *parent, *np = rd->dn;
240 struct pci_dn *pdn;
241 int err = NOTIFY_OK;
242
243 switch (action) {
244 case OF_RECONFIG_ATTACH_NODE:
245 parent = of_get_parent(np);
246 pdn = parent ? PCI_DN(parent) : NULL;
247 if (pdn)
248 pci_add_device_node_info(pdn->phb, np);
249
250 of_node_put(parent);
251 break;
252 case OF_RECONFIG_DETACH_NODE:
253 pdn = PCI_DN(np);
254 if (pdn)
255 list_del(&pdn->list);
256 break;
257 default:
258 err = NOTIFY_DONE;
259 break;
260 }
261 return err;
262}
263
264static struct notifier_block pci_dn_reconfig_nb = {
265 .notifier_call = pci_dn_reconfig_notifier,
266};
267
268struct kmem_cache *dtl_cache;
269
270#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
271
272
273
274
275
276static int alloc_dispatch_logs(void)
277{
278 if (!firmware_has_feature(FW_FEATURE_SPLPAR))
279 return 0;
280
281 if (!dtl_cache)
282 return 0;
283
284 alloc_dtl_buffers(0);
285
286
287 register_dtl_buffer(smp_processor_id());
288
289 return 0;
290}
291#else
292static inline int alloc_dispatch_logs(void)
293{
294 return 0;
295}
296#endif
297
298static int alloc_dispatch_log_kmem_cache(void)
299{
300 dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES,
301 DISPATCH_LOG_BYTES, 0, NULL);
302 if (!dtl_cache) {
303 pr_warn("Failed to create dispatch trace log buffer cache\n");
304 pr_warn("Stolen time statistics will be unreliable\n");
305 return 0;
306 }
307
308 return alloc_dispatch_logs();
309}
310machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
311
312static void pseries_lpar_idle(void)
313{
314
315
316
317
318
319
320 get_lppaca()->idle = 1;
321
322
323
324
325
326
327
328
329 cede_processor();
330
331 get_lppaca()->idle = 0;
332}
333
334
335
336
337
338
339
340
341void pseries_enable_reloc_on_exc(void)
342{
343 long rc;
344 unsigned int delay, total_delay = 0;
345
346 while (1) {
347 rc = enable_reloc_on_exceptions();
348 if (!H_IS_LONG_BUSY(rc)) {
349 if (rc == H_P2) {
350 pr_info("Relocation on exceptions not"
351 " supported\n");
352 } else if (rc != H_SUCCESS) {
353 pr_warn("Unable to enable relocation"
354 " on exceptions: %ld\n", rc);
355 }
356 break;
357 }
358
359 delay = get_longbusy_msecs(rc);
360 total_delay += delay;
361 if (total_delay > 1000) {
362 pr_warn("Warning: Giving up waiting to enable "
363 "relocation on exceptions (%u msec)!\n",
364 total_delay);
365 return;
366 }
367
368 mdelay(delay);
369 }
370}
371EXPORT_SYMBOL(pseries_enable_reloc_on_exc);
372
373void pseries_disable_reloc_on_exc(void)
374{
375 long rc;
376
377 while (1) {
378 rc = disable_reloc_on_exceptions();
379 if (!H_IS_LONG_BUSY(rc))
380 break;
381 mdelay(get_longbusy_msecs(rc));
382 }
383 if (rc != H_SUCCESS)
384 pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n",
385 rc);
386}
387EXPORT_SYMBOL(pseries_disable_reloc_on_exc);
388
389#ifdef CONFIG_KEXEC_CORE
390static void pSeries_machine_kexec(struct kimage *image)
391{
392 if (firmware_has_feature(FW_FEATURE_SET_MODE))
393 pseries_disable_reloc_on_exc();
394
395 default_machine_kexec(image);
396}
397#endif
398
399#ifdef __LITTLE_ENDIAN__
400void pseries_big_endian_exceptions(void)
401{
402 long rc;
403
404 while (1) {
405 rc = enable_big_endian_exceptions();
406 if (!H_IS_LONG_BUSY(rc))
407 break;
408 mdelay(get_longbusy_msecs(rc));
409 }
410
411
412
413
414
415
416
417
418
419
420
421
422 if (rc && !kdump_in_progress())
423 panic("Could not enable big endian exceptions");
424}
425
426void pseries_little_endian_exceptions(void)
427{
428 long rc;
429
430 while (1) {
431 rc = enable_little_endian_exceptions();
432 if (!H_IS_LONG_BUSY(rc))
433 break;
434 mdelay(get_longbusy_msecs(rc));
435 }
436 if (rc) {
437 ppc_md.progress("H_SET_MODE LE exception fail", 0);
438 panic("Could not enable little endian exceptions");
439 }
440}
441#endif
442
443static void __init find_and_init_phbs(void)
444{
445 struct device_node *node;
446 struct pci_controller *phb;
447 struct device_node *root = of_find_node_by_path("/");
448
449 for_each_child_of_node(root, node) {
450 if (!of_node_is_type(node, "pci") &&
451 !of_node_is_type(node, "pciex"))
452 continue;
453
454 phb = pcibios_alloc_controller(node);
455 if (!phb)
456 continue;
457 rtas_setup_phb(phb);
458 pci_process_bridge_OF_ranges(phb, node, 0);
459 isa_bridge_find_early(phb);
460 phb->controller_ops = pseries_pci_controller_ops;
461 }
462
463 of_node_put(root);
464
465
466
467
468
469 of_pci_check_probe_only();
470}
471
472static void init_cpu_char_feature_flags(struct h_cpu_char_result *result)
473{
474
475
476
477
478 if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31)
479 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
480
481 if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED)
482 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
483
484 if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30)
485 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
486
487 if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
488 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
489
490 if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV)
491 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
492
493 if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED)
494 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
495
496 if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
497 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
498
499 if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE)
500 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
501
502
503
504
505
506 if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY))
507 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
508
509 if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
510 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
511
512 if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR))
513 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
514}
515
516void pseries_setup_rfi_flush(void)
517{
518 struct h_cpu_char_result result;
519 enum l1d_flush_type types;
520 bool enable;
521 long rc;
522
523
524
525
526
527
528 powerpc_security_features = SEC_FTR_DEFAULT;
529
530 rc = plpar_get_cpu_characteristics(&result);
531 if (rc == H_SUCCESS)
532 init_cpu_char_feature_flags(&result);
533
534
535
536
537
538 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
539
540 types = L1D_FLUSH_FALLBACK;
541
542 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
543 types |= L1D_FLUSH_MTTRIG;
544
545 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
546 types |= L1D_FLUSH_ORI;
547
548 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
549 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR);
550
551 setup_rfi_flush(types, enable);
552 setup_count_cache_flush();
553}
554
555#ifdef CONFIG_PCI_IOV
556enum rtas_iov_fw_value_map {
557 NUM_RES_PROPERTY = 0,
558 LOW_INT = 1,
559 START_OF_ENTRIES = 2,
560 APERTURE_PROPERTY = 2,
561 WDW_SIZE_PROPERTY = 4,
562 NEXT_ENTRY = 7
563};
564
565enum get_iov_fw_value_index {
566 BAR_ADDRS = 1,
567 APERTURE_SIZE = 2,
568 WDW_SIZE = 3
569};
570
571resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno,
572 enum get_iov_fw_value_index value)
573{
574 const int *indexes;
575 struct device_node *dn = pci_device_to_OF_node(dev);
576 int i, num_res, ret = 0;
577
578 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
579 if (!indexes)
580 return 0;
581
582
583
584
585
586
587 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
588 if (resno >= num_res)
589 return 0;
590
591 i = START_OF_ENTRIES + NEXT_ENTRY * resno;
592 switch (value) {
593 case BAR_ADDRS:
594 ret = of_read_number(&indexes[i], 2);
595 break;
596 case APERTURE_SIZE:
597 ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
598 break;
599 case WDW_SIZE:
600 ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
601 break;
602 }
603
604 return ret;
605}
606
607void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes)
608{
609 struct resource *res;
610 resource_size_t base, size;
611 int i, r, num_res;
612
613 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
614 num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS);
615 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
616 i += NEXT_ENTRY, r++) {
617 res = &dev->resource[r + PCI_IOV_RESOURCES];
618 base = of_read_number(&indexes[i], 2);
619 size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2);
620 res->flags = pci_parse_of_flags(of_read_number
621 (&indexes[i + LOW_INT], 1), 0);
622 res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED);
623 res->name = pci_name(dev);
624 res->start = base;
625 res->end = base + size - 1;
626 }
627}
628
629void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes)
630{
631 struct resource *res, *root, *conflict;
632 resource_size_t base, size;
633 int i, r, num_res;
634
635
636
637
638
639
640 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1);
641 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS;
642 i += NEXT_ENTRY, r++) {
643 res = &dev->resource[r + PCI_IOV_RESOURCES];
644 base = of_read_number(&indexes[i], 2);
645 size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2);
646 res->name = pci_name(dev);
647 res->start = base;
648 res->end = base + size - 1;
649 root = &iomem_resource;
650 dev_dbg(&dev->dev,
651 "pSeries IOV BAR %d: trying firmware assignment %pR\n",
652 r + PCI_IOV_RESOURCES, res);
653 conflict = request_resource_conflict(root, res);
654 if (conflict) {
655 dev_info(&dev->dev,
656 "BAR %d: %pR conflicts with %s %pR\n",
657 r + PCI_IOV_RESOURCES, res,
658 conflict->name, conflict);
659 res->flags |= IORESOURCE_UNSET;
660 }
661 }
662}
663
664static void pseries_disable_sriov_resources(struct pci_dev *pdev)
665{
666 int i;
667
668 pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n");
669 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
670 pdev->resource[i + PCI_IOV_RESOURCES].flags = 0;
671}
672
673static void pseries_pci_fixup_resources(struct pci_dev *pdev)
674{
675 const int *indexes;
676 struct device_node *dn = pci_device_to_OF_node(pdev);
677
678
679 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
680 if (indexes)
681 of_pci_set_vf_bar_size(pdev, indexes);
682 else
683 pseries_disable_sriov_resources(pdev);
684}
685
686static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev)
687{
688 const int *indexes;
689 struct device_node *dn = pci_device_to_OF_node(pdev);
690
691 if (!pdev->is_physfn || pci_dev_is_added(pdev))
692 return;
693
694 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL);
695 if (indexes)
696 of_pci_parse_iov_addrs(pdev, indexes);
697 else
698 pseries_disable_sriov_resources(pdev);
699}
700
701static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev,
702 int resno)
703{
704 const __be32 *reg;
705 struct device_node *dn = pci_device_to_OF_node(pdev);
706
707
708 reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL);
709 if (!reg)
710 return pci_iov_resource_size(pdev, resno);
711
712 if (!pdev->is_physfn)
713 return 0;
714 return pseries_get_iov_fw_value(pdev,
715 resno - PCI_IOV_RESOURCES,
716 APERTURE_SIZE);
717}
718#endif
719
720static void __init pSeries_setup_arch(void)
721{
722 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
723
724
725 smp_init_pseries();
726
727
728
729
730
731
732
733 loops_per_jiffy = 50000000;
734
735 fwnmi_init();
736
737 pseries_setup_rfi_flush();
738 setup_stf_barrier();
739
740
741 pci_add_flags(PCI_PROBE_ONLY);
742
743
744 init_pci_config_tokens();
745 find_and_init_phbs();
746 of_reconfig_notifier_register(&pci_dn_reconfig_nb);
747
748 pSeries_nvram_init();
749
750 if (firmware_has_feature(FW_FEATURE_LPAR)) {
751 vpa_init(boot_cpuid);
752 ppc_md.power_save = pseries_lpar_idle;
753 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
754#ifdef CONFIG_PCI_IOV
755 ppc_md.pcibios_fixup_resources =
756 pseries_pci_fixup_resources;
757 ppc_md.pcibios_fixup_sriov =
758 pseries_pci_fixup_iov_resources;
759 ppc_md.pcibios_iov_resource_alignment =
760 pseries_pci_iov_resource_alignment;
761#endif
762 } else {
763
764 ppc_md.enable_pmcs = power4_enable_pmcs;
765 }
766
767 ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
768
769 if (swiotlb_force == SWIOTLB_FORCE)
770 ppc_swiotlb_enable = 1;
771}
772
773static void pseries_panic(char *str)
774{
775 panic_flush_kmsg_end();
776 rtas_os_term(str);
777}
778
779static int __init pSeries_init_panel(void)
780{
781
782#ifdef __BIG_ENDIAN__
783 ppc_md.progress("Linux ppc64\n", 0);
784#else
785 ppc_md.progress("Linux ppc64le\n", 0);
786#endif
787 ppc_md.progress(init_utsname()->version, 0);
788
789 return 0;
790}
791machine_arch_initcall(pseries, pSeries_init_panel);
792
793static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx)
794{
795 return plpar_hcall_norets(H_SET_DABR, dabr);
796}
797
798static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx)
799{
800
801 if (dabrx == 0 && dabr == 0)
802 dabrx = DABRX_USER;
803
804 dabrx &= DABRX_KERNEL | DABRX_USER;
805
806 return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx);
807}
808
809static int pseries_set_dawr(unsigned long dawr, unsigned long dawrx)
810{
811
812 dawrx &= ~DAWRX_HYP;
813
814 return plpar_set_watchpoint0(dawr, dawrx);
815}
816
817#define CMO_CHARACTERISTICS_TOKEN 44
818#define CMO_MAXLENGTH 1026
819
820void pSeries_coalesce_init(void)
821{
822 struct hvcall_mpp_x_data mpp_x_data;
823
824 if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data))
825 powerpc_firmware_features |= FW_FEATURE_XCMO;
826 else
827 powerpc_firmware_features &= ~FW_FEATURE_XCMO;
828}
829
830
831
832
833
834static void pSeries_cmo_feature_init(void)
835{
836 char *ptr, *key, *value, *end;
837 int call_status;
838 int page_order = IOMMU_PAGE_SHIFT_4K;
839
840 pr_debug(" -> fw_cmo_feature_init()\n");
841 spin_lock(&rtas_data_buf_lock);
842 memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE);
843 call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
844 NULL,
845 CMO_CHARACTERISTICS_TOKEN,
846 __pa(rtas_data_buf),
847 RTAS_DATA_BUF_SIZE);
848
849 if (call_status != 0) {
850 spin_unlock(&rtas_data_buf_lock);
851 pr_debug("CMO not available\n");
852 pr_debug(" <- fw_cmo_feature_init()\n");
853 return;
854 }
855
856 end = rtas_data_buf + CMO_MAXLENGTH - 2;
857 ptr = rtas_data_buf + 2;
858 key = value = ptr;
859
860 while (*ptr && (ptr <= end)) {
861
862
863
864 if (ptr[0] == '=') {
865 ptr[0] = '\0';
866 value = ptr + 1;
867 } else if (ptr[0] == '\0' || ptr[0] == ',') {
868
869 ptr[0] = '\0';
870
871 if (key == value) {
872 pr_debug("Malformed key/value pair\n");
873
874 break;
875 }
876
877 if (0 == strcmp(key, "CMOPageSize"))
878 page_order = simple_strtol(value, NULL, 10);
879 else if (0 == strcmp(key, "PrPSP"))
880 CMO_PrPSP = simple_strtol(value, NULL, 10);
881 else if (0 == strcmp(key, "SecPSP"))
882 CMO_SecPSP = simple_strtol(value, NULL, 10);
883 value = key = ptr + 1;
884 }
885 ptr++;
886 }
887
888
889
890
891 CMO_PageSize = 1 << page_order;
892 pr_debug("CMO_PageSize = %lu\n", CMO_PageSize);
893
894 if (CMO_PrPSP != -1 || CMO_SecPSP != -1) {
895 pr_info("CMO enabled\n");
896 pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
897 CMO_SecPSP);
898 powerpc_firmware_features |= FW_FEATURE_CMO;
899 pSeries_coalesce_init();
900 } else
901 pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP,
902 CMO_SecPSP);
903 spin_unlock(&rtas_data_buf_lock);
904 pr_debug(" <- fw_cmo_feature_init()\n");
905}
906
907
908
909
910static void __init pseries_init(void)
911{
912 pr_debug(" -> pseries_init()\n");
913
914#ifdef CONFIG_HVC_CONSOLE
915 if (firmware_has_feature(FW_FEATURE_LPAR))
916 hvc_vio_init_early();
917#endif
918 if (firmware_has_feature(FW_FEATURE_XDABR))
919 ppc_md.set_dabr = pseries_set_xdabr;
920 else if (firmware_has_feature(FW_FEATURE_DABR))
921 ppc_md.set_dabr = pseries_set_dabr;
922
923 if (firmware_has_feature(FW_FEATURE_SET_MODE))
924 ppc_md.set_dawr = pseries_set_dawr;
925
926 pSeries_cmo_feature_init();
927 iommu_init_early_pSeries();
928
929 pr_debug(" <- pseries_init()\n");
930}
931
932
933
934
935
936
937
938
939
940
941static void pseries_power_off(void)
942{
943 int rc;
944 int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups");
945
946 if (rtas_flash_term_hook)
947 rtas_flash_term_hook(SYS_POWER_OFF);
948
949 if (rtas_poweron_auto == 0 ||
950 rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) {
951 rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1);
952 printk(KERN_INFO "RTAS power-off returned %d\n", rc);
953 } else {
954 rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL);
955 printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc);
956 }
957 for (;;);
958}
959
960static int __init pSeries_probe(void)
961{
962 if (!of_node_is_type(of_root, "chrp"))
963 return 0;
964
965
966
967
968 if (of_machine_is_compatible("IBM,CPBW-1.0") ||
969 of_machine_is_compatible("IBM,CBEA"))
970 return 0;
971
972 pm_power_off = pseries_power_off;
973
974 pr_debug("Machine is%s LPAR !\n",
975 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not");
976
977 pseries_init();
978
979 return 1;
980}
981
982static int pSeries_pci_probe_mode(struct pci_bus *bus)
983{
984 if (firmware_has_feature(FW_FEATURE_LPAR))
985 return PCI_PROBE_DEVTREE;
986 return PCI_PROBE_NORMAL;
987}
988
989struct pci_controller_ops pseries_pci_controller_ops = {
990 .probe_mode = pSeries_pci_probe_mode,
991};
992
993define_machine(pseries) {
994 .name = "pSeries",
995 .probe = pSeries_probe,
996 .setup_arch = pSeries_setup_arch,
997 .init_IRQ = pseries_init_irq,
998 .show_cpuinfo = pSeries_show_cpuinfo,
999 .log_error = pSeries_log_error,
1000 .pcibios_fixup = pSeries_final_fixup,
1001 .restart = rtas_restart,
1002 .halt = rtas_halt,
1003 .panic = pseries_panic,
1004 .get_boot_time = rtas_get_boot_time,
1005 .get_rtc_time = rtas_get_rtc_time,
1006 .set_rtc_time = rtas_set_rtc_time,
1007 .calibrate_decr = generic_calibrate_decr,
1008 .progress = rtas_progress,
1009 .system_reset_exception = pSeries_system_reset_exception,
1010 .machine_check_early = pseries_machine_check_realmode,
1011 .machine_check_exception = pSeries_machine_check_exception,
1012#ifdef CONFIG_KEXEC_CORE
1013 .machine_kexec = pSeries_machine_kexec,
1014 .kexec_cpu_down = pseries_kexec_cpu_down,
1015#endif
1016#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
1017 .memory_block_size = pseries_memory_block_size,
1018#endif
1019};
1020