1
2#ifndef _ASM_X86_IO_APIC_H
3#define _ASM_X86_IO_APIC_H
4
5#include <linux/types.h>
6#include <asm/mpspec.h>
7#include <asm/apicdef.h>
8#include <asm/irq_vectors.h>
9#include <asm/x86_init.h>
10
11
12
13
14
15
16
17#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
18#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
19#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
20#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
21#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
22#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
23#define IO_APIC_REDIR_MASKED (1 << 16)
24
25
26
27
28union IO_APIC_reg_00 {
29 u32 raw;
30 struct {
31 u32 __reserved_2 : 14,
32 LTS : 1,
33 delivery_type : 1,
34 __reserved_1 : 8,
35 ID : 8;
36 } __attribute__ ((packed)) bits;
37};
38
39union IO_APIC_reg_01 {
40 u32 raw;
41 struct {
42 u32 version : 8,
43 __reserved_2 : 7,
44 PRQ : 1,
45 entries : 8,
46 __reserved_1 : 8;
47 } __attribute__ ((packed)) bits;
48};
49
50union IO_APIC_reg_02 {
51 u32 raw;
52 struct {
53 u32 __reserved_2 : 24,
54 arbitration : 4,
55 __reserved_1 : 4;
56 } __attribute__ ((packed)) bits;
57};
58
59union IO_APIC_reg_03 {
60 u32 raw;
61 struct {
62 u32 boot_DT : 1,
63 __reserved_1 : 31;
64 } __attribute__ ((packed)) bits;
65};
66
67struct IO_APIC_route_entry {
68 __u32 vector : 8,
69 delivery_mode : 3,
70
71
72
73 dest_mode : 1,
74 delivery_status : 1,
75 polarity : 1,
76 irr : 1,
77 trigger : 1,
78 mask : 1,
79 __reserved_2 : 15;
80
81 __u32 __reserved_3 : 24,
82 dest : 8;
83} __attribute__ ((packed));
84
85struct IR_IO_APIC_route_entry {
86 __u64 vector : 8,
87 zero : 3,
88 index2 : 1,
89 delivery_status : 1,
90 polarity : 1,
91 irr : 1,
92 trigger : 1,
93 mask : 1,
94 reserved : 31,
95 format : 1,
96 index : 15;
97} __attribute__ ((packed));
98
99struct irq_alloc_info;
100struct ioapic_domain_cfg;
101
102#define IOAPIC_AUTO -1
103#define IOAPIC_EDGE 0
104#define IOAPIC_LEVEL 1
105
106#define IOAPIC_MASKED 1
107#define IOAPIC_UNMASKED 0
108
109#define IOAPIC_POL_HIGH 0
110#define IOAPIC_POL_LOW 1
111
112#define IOAPIC_DEST_MODE_PHYSICAL 0
113#define IOAPIC_DEST_MODE_LOGICAL 1
114
115#define IOAPIC_MAP_ALLOC 0x1
116#define IOAPIC_MAP_CHECK 0x2
117
118#ifdef CONFIG_X86_IO_APIC
119
120
121
122
123extern int nr_ioapics;
124
125extern int mpc_ioapic_id(int ioapic);
126extern unsigned int mpc_ioapic_addr(int ioapic);
127
128
129extern int mp_irq_entries;
130
131
132extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
133
134
135extern int skip_ioapic_setup;
136
137
138extern int noioapicquirk;
139
140
141extern int noioapicreroute;
142
143extern u32 gsi_top;
144
145extern unsigned long io_apic_irqs;
146
147#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
148
149
150
151
152
153#define io_apic_assign_pci_irqs \
154 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
155
156struct irq_cfg;
157extern void ioapic_insert_resources(void);
158extern int arch_early_ioapic_init(void);
159
160extern int save_ioapic_entries(void);
161extern void mask_ioapic_entries(void);
162extern int restore_ioapic_entries(void);
163
164extern void setup_ioapic_ids_from_mpc(void);
165extern void setup_ioapic_ids_from_mpc_nocheck(void);
166
167extern int mp_find_ioapic(u32 gsi);
168extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
169extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
170 struct irq_alloc_info *info);
171extern void mp_unmap_irq(int irq);
172extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
173 struct ioapic_domain_cfg *cfg);
174extern int mp_unregister_ioapic(u32 gsi_base);
175extern int mp_ioapic_registered(u32 gsi_base);
176
177extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
178 int node, int trigger, int polarity);
179
180extern void mp_save_irq(struct mpc_intsrc *m);
181
182extern void disable_ioapic_support(void);
183
184extern void __init io_apic_init_mappings(void);
185extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
186extern void native_restore_boot_irq_mode(void);
187
188static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
189{
190 return x86_apic_ops.io_apic_read(apic, reg);
191}
192
193extern void setup_IO_APIC(void);
194extern void enable_IO_APIC(void);
195extern void clear_IO_APIC(void);
196extern void restore_boot_irq_mode(void);
197extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
198extern void print_IO_APICs(void);
199#else
200
201#define IO_APIC_IRQ(x) 0
202#define io_apic_assign_pci_irqs 0
203#define setup_ioapic_ids_from_mpc x86_init_noop
204static inline void ioapic_insert_resources(void) { }
205static inline int arch_early_ioapic_init(void) { return 0; }
206static inline void print_IO_APICs(void) {}
207#define gsi_top (NR_IRQS_LEGACY)
208static inline int mp_find_ioapic(u32 gsi) { return 0; }
209static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
210 struct irq_alloc_info *info)
211{
212 return gsi;
213}
214
215static inline void mp_unmap_irq(int irq) { }
216
217static inline int save_ioapic_entries(void)
218{
219 return -ENOMEM;
220}
221
222static inline void mask_ioapic_entries(void) { }
223static inline int restore_ioapic_entries(void)
224{
225 return -ENOMEM;
226}
227
228static inline void mp_save_irq(struct mpc_intsrc *m) { }
229static inline void disable_ioapic_support(void) { }
230static inline void io_apic_init_mappings(void) { }
231#define native_io_apic_read NULL
232#define native_restore_boot_irq_mode NULL
233
234static inline void setup_IO_APIC(void) { }
235static inline void enable_IO_APIC(void) { }
236static inline void restore_boot_irq_mode(void) { }
237
238#endif
239
240#endif
241
