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10#include <linux/mm.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/pci.h>
14#include <linux/dmar.h>
15#include <linux/hpet.h>
16#include <linux/msi.h>
17#include <asm/irqdomain.h>
18#include <asm/msidef.h>
19#include <asm/hpet.h>
20#include <asm/hw_irq.h>
21#include <asm/apic.h>
22#include <asm/irq_remapping.h>
23
24static struct irq_domain *msi_default_domain;
25
26static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
27{
28 struct irq_cfg *cfg = irqd_cfg(data);
29
30 msg->address_hi = MSI_ADDR_BASE_HI;
31
32 if (x2apic_enabled())
33 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
34
35 msg->address_lo =
36 MSI_ADDR_BASE_LO |
37 ((apic->irq_dest_mode == 0) ?
38 MSI_ADDR_DEST_MODE_PHYSICAL :
39 MSI_ADDR_DEST_MODE_LOGICAL) |
40 MSI_ADDR_REDIRECTION_CPU |
41 MSI_ADDR_DEST_ID(cfg->dest_apicid);
42
43 msg->data =
44 MSI_DATA_TRIGGER_EDGE |
45 MSI_DATA_LEVEL_ASSERT |
46 MSI_DATA_DELIVERY_FIXED |
47 MSI_DATA_VECTOR(cfg->vector);
48}
49
50
51
52
53
54static struct irq_chip pci_msi_controller = {
55 .name = "PCI-MSI",
56 .irq_unmask = pci_msi_unmask_irq,
57 .irq_mask = pci_msi_mask_irq,
58 .irq_ack = irq_chip_ack_parent,
59 .irq_retrigger = irq_chip_retrigger_hierarchy,
60 .irq_compose_msi_msg = irq_msi_compose_msg,
61 .flags = IRQCHIP_SKIP_SET_WAKE,
62};
63
64int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
65{
66 struct irq_domain *domain;
67 struct irq_alloc_info info;
68
69 init_irq_alloc_info(&info, NULL);
70 info.type = X86_IRQ_ALLOC_TYPE_MSI;
71 info.msi_dev = dev;
72
73 domain = irq_remapping_get_irq_domain(&info);
74 if (domain == NULL)
75 domain = msi_default_domain;
76 if (domain == NULL)
77 return -ENOSYS;
78
79 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
80}
81
82void native_teardown_msi_irq(unsigned int irq)
83{
84 irq_domain_free_irqs(irq, 1);
85}
86
87static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
88 msi_alloc_info_t *arg)
89{
90 return arg->msi_hwirq;
91}
92
93int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
94 msi_alloc_info_t *arg)
95{
96 struct pci_dev *pdev = to_pci_dev(dev);
97 struct msi_desc *desc = first_pci_msi_entry(pdev);
98
99 init_irq_alloc_info(arg, NULL);
100 arg->msi_dev = pdev;
101 if (desc->msi_attrib.is_msix) {
102 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
103 } else {
104 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
105 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
106 }
107
108 return 0;
109}
110EXPORT_SYMBOL_GPL(pci_msi_prepare);
111
112void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
113{
114 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
115}
116EXPORT_SYMBOL_GPL(pci_msi_set_desc);
117
118static struct msi_domain_ops pci_msi_domain_ops = {
119 .get_hwirq = pci_msi_get_hwirq,
120 .msi_prepare = pci_msi_prepare,
121 .set_desc = pci_msi_set_desc,
122};
123
124static struct msi_domain_info pci_msi_domain_info = {
125 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
126 MSI_FLAG_PCI_MSIX,
127 .ops = &pci_msi_domain_ops,
128 .chip = &pci_msi_controller,
129 .handler = handle_edge_irq,
130 .handler_name = "edge",
131};
132
133void __init arch_init_msi_domain(struct irq_domain *parent)
134{
135 struct fwnode_handle *fn;
136
137 if (disable_apic)
138 return;
139
140 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
141 if (fn) {
142 msi_default_domain =
143 pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
144 parent);
145 irq_domain_free_fwnode(fn);
146 }
147 if (!msi_default_domain)
148 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
149}
150
151#ifdef CONFIG_IRQ_REMAP
152static struct irq_chip pci_msi_ir_controller = {
153 .name = "IR-PCI-MSI",
154 .irq_unmask = pci_msi_unmask_irq,
155 .irq_mask = pci_msi_mask_irq,
156 .irq_ack = irq_chip_ack_parent,
157 .irq_retrigger = irq_chip_retrigger_hierarchy,
158 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
159 .flags = IRQCHIP_SKIP_SET_WAKE,
160};
161
162static struct msi_domain_info pci_msi_ir_domain_info = {
163 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
164 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
165 .ops = &pci_msi_domain_ops,
166 .chip = &pci_msi_ir_controller,
167 .handler = handle_edge_irq,
168 .handler_name = "edge",
169};
170
171struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
172 const char *name, int id)
173{
174 struct fwnode_handle *fn;
175 struct irq_domain *d;
176
177 fn = irq_domain_alloc_named_id_fwnode(name, id);
178 if (!fn)
179 return NULL;
180 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
181 irq_domain_free_fwnode(fn);
182 return d;
183}
184#endif
185
186#ifdef CONFIG_DMAR_TABLE
187static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
188{
189 dmar_msi_write(data->irq, msg);
190}
191
192static struct irq_chip dmar_msi_controller = {
193 .name = "DMAR-MSI",
194 .irq_unmask = dmar_msi_unmask,
195 .irq_mask = dmar_msi_mask,
196 .irq_ack = irq_chip_ack_parent,
197 .irq_set_affinity = msi_domain_set_affinity,
198 .irq_retrigger = irq_chip_retrigger_hierarchy,
199 .irq_compose_msi_msg = irq_msi_compose_msg,
200 .irq_write_msi_msg = dmar_msi_write_msg,
201 .flags = IRQCHIP_SKIP_SET_WAKE,
202};
203
204static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
205 msi_alloc_info_t *arg)
206{
207 return arg->dmar_id;
208}
209
210static int dmar_msi_init(struct irq_domain *domain,
211 struct msi_domain_info *info, unsigned int virq,
212 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
213{
214 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
215 handle_edge_irq, arg->dmar_data, "edge");
216
217 return 0;
218}
219
220static struct msi_domain_ops dmar_msi_domain_ops = {
221 .get_hwirq = dmar_msi_get_hwirq,
222 .msi_init = dmar_msi_init,
223};
224
225static struct msi_domain_info dmar_msi_domain_info = {
226 .ops = &dmar_msi_domain_ops,
227 .chip = &dmar_msi_controller,
228};
229
230static struct irq_domain *dmar_get_irq_domain(void)
231{
232 static struct irq_domain *dmar_domain;
233 static DEFINE_MUTEX(dmar_lock);
234 struct fwnode_handle *fn;
235
236 mutex_lock(&dmar_lock);
237 if (dmar_domain)
238 goto out;
239
240 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
241 if (fn) {
242 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
243 x86_vector_domain);
244 irq_domain_free_fwnode(fn);
245 }
246out:
247 mutex_unlock(&dmar_lock);
248 return dmar_domain;
249}
250
251int dmar_alloc_hwirq(int id, int node, void *arg)
252{
253 struct irq_domain *domain = dmar_get_irq_domain();
254 struct irq_alloc_info info;
255
256 if (!domain)
257 return -1;
258
259 init_irq_alloc_info(&info, NULL);
260 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
261 info.dmar_id = id;
262 info.dmar_data = arg;
263
264 return irq_domain_alloc_irqs(domain, 1, node, &info);
265}
266
267void dmar_free_hwirq(int irq)
268{
269 irq_domain_free_irqs(irq, 1);
270}
271#endif
272
273
274
275
276#ifdef CONFIG_HPET_TIMER
277static inline int hpet_dev_id(struct irq_domain *domain)
278{
279 struct msi_domain_info *info = msi_get_domain_info(domain);
280
281 return (int)(long)info->data;
282}
283
284static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
285{
286 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
287}
288
289static struct irq_chip hpet_msi_controller __ro_after_init = {
290 .name = "HPET-MSI",
291 .irq_unmask = hpet_msi_unmask,
292 .irq_mask = hpet_msi_mask,
293 .irq_ack = irq_chip_ack_parent,
294 .irq_set_affinity = msi_domain_set_affinity,
295 .irq_retrigger = irq_chip_retrigger_hierarchy,
296 .irq_compose_msi_msg = irq_msi_compose_msg,
297 .irq_write_msi_msg = hpet_msi_write_msg,
298 .flags = IRQCHIP_SKIP_SET_WAKE,
299};
300
301static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
302 msi_alloc_info_t *arg)
303{
304 return arg->hpet_index;
305}
306
307static int hpet_msi_init(struct irq_domain *domain,
308 struct msi_domain_info *info, unsigned int virq,
309 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
310{
311 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
312 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
313 handle_edge_irq, arg->hpet_data, "edge");
314
315 return 0;
316}
317
318static void hpet_msi_free(struct irq_domain *domain,
319 struct msi_domain_info *info, unsigned int virq)
320{
321 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
322}
323
324static struct msi_domain_ops hpet_msi_domain_ops = {
325 .get_hwirq = hpet_msi_get_hwirq,
326 .msi_init = hpet_msi_init,
327 .msi_free = hpet_msi_free,
328};
329
330static struct msi_domain_info hpet_msi_domain_info = {
331 .ops = &hpet_msi_domain_ops,
332 .chip = &hpet_msi_controller,
333};
334
335struct irq_domain *hpet_create_irq_domain(int hpet_id)
336{
337 struct msi_domain_info *domain_info;
338 struct irq_domain *parent, *d;
339 struct irq_alloc_info info;
340 struct fwnode_handle *fn;
341
342 if (x86_vector_domain == NULL)
343 return NULL;
344
345 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
346 if (!domain_info)
347 return NULL;
348
349 *domain_info = hpet_msi_domain_info;
350 domain_info->data = (void *)(long)hpet_id;
351
352 init_irq_alloc_info(&info, NULL);
353 info.type = X86_IRQ_ALLOC_TYPE_HPET;
354 info.hpet_id = hpet_id;
355 parent = irq_remapping_get_ir_irq_domain(&info);
356 if (parent == NULL)
357 parent = x86_vector_domain;
358 else
359 hpet_msi_controller.name = "IR-HPET-MSI";
360
361 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
362 hpet_id);
363 if (!fn) {
364 kfree(domain_info);
365 return NULL;
366 }
367
368 d = msi_create_irq_domain(fn, domain_info, parent);
369 irq_domain_free_fwnode(fn);
370 return d;
371}
372
373int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc,
374 int dev_num)
375{
376 struct irq_alloc_info info;
377
378 init_irq_alloc_info(&info, NULL);
379 info.type = X86_IRQ_ALLOC_TYPE_HPET;
380 info.hpet_data = hc;
381 info.hpet_id = hpet_dev_id(domain);
382 info.hpet_index = dev_num;
383
384 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
385}
386#endif
387
