LXR linux/arch/x86/kvm/lapic.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __KVM_X86_LAPIC_H
   3#define __KVM_X86_LAPIC_H
   4
   5#include <kvm/iodev.h>
   6
   7#include <linux/kvm_host.h>
   8
   9#define KVM_APIC_INIT           0
  10#define KVM_APIC_SIPI           1
  11#define KVM_APIC_LVT_NUM        6
  12
  13#define KVM_APIC_SHORT_MASK     0xc0000
  14#define KVM_APIC_DEST_MASK      0x800
  15
  16#define APIC_BUS_CYCLE_NS       1
  17#define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
  18
  19enum lapic_mode {
  20        LAPIC_MODE_DISABLED = 0,
  21        LAPIC_MODE_INVALID = X2APIC_ENABLE,
  22        LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
  23        LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
  24};
  25
  26struct kvm_timer {
  27        struct hrtimer timer;
  28        s64 period;                             /* unit: ns */
  29        ktime_t target_expiration;
  30        u32 timer_mode;
  31        u32 timer_mode_mask;
  32        u64 tscdeadline;
  33        u64 expired_tscdeadline;
  34        u32 timer_advance_ns;
  35        s64 advance_expire_delta;
  36        atomic_t pending;                       /* accumulated triggered timers */
  37        bool hv_timer_in_use;
  38        bool timer_advance_adjust_done;
  39};
  40
  41struct kvm_lapic {
  42        unsigned long base_address;
  43        struct kvm_io_device dev;
  44        struct kvm_timer lapic_timer;
  45        u32 divide_count;
  46        struct kvm_vcpu *vcpu;
  47        bool sw_enabled;
  48        bool irr_pending;
  49        bool lvt0_in_nmi_mode;
  50        /* Number of bits set in ISR. */
  51        s16 isr_count;
  52        /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
  53        int highest_isr_cache;
  54        /**
  55         * APIC register page.  The layout matches the register layout seen by
  56         * the guest 1:1, because it is accessed by the vmx microcode.
  57         * Note: Only one register, the TPR, is used by the microcode.
  58         */
  59        void *regs;
  60        gpa_t vapic_addr;
  61        struct gfn_to_hva_cache vapic_cache;
  62        unsigned long pending_events;
  63        unsigned int sipi_vector;
  64};
  65
  66struct dest_map;
  67
  68int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
  69void kvm_free_lapic(struct kvm_vcpu *vcpu);
  70
  71int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
  72int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
  73int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
  74void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
  75void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
  76u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
  77void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
  78void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
  79void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
  80u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
  81void kvm_apic_set_version(struct kvm_vcpu *vcpu);
  82int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
  83int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
  84                       void *data);
  85bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
  86                           int short_hand, unsigned int dest, int dest_mode);
  87
  88bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
  89bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
  90void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
  91int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
  92                     struct dest_map *dest_map);
  93int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
  94
  95bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
  96                struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
  97
  98u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
  99int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 100int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 101int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 102enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
 103int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
 104
 105u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
 106void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
 107
 108void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
 109void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
 110
 111int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
 112void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
 113void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
 114
 115int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 116int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 117
 118int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 119int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 120
 121static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
 122{
 123        return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
 124}
 125
 126int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
 127void kvm_lapic_init(void);
 128void kvm_lapic_exit(void);
 129
 130#define VEC_POS(v) ((v) & (32 - 1))
 131#define REG_POS(v) (((v) >> 5) << 4)
 132
 133static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
 134{
 135        clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 136}
 137
 138static inline void kvm_lapic_set_vector(int vec, void *bitmap)
 139{
 140        set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 141}
 142
 143static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
 144{
 145        kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
 146        /*
 147         * irr_pending must be true if any interrupt is pending; set it after
 148         * APIC_IRR to avoid race with apic_clear_irr
 149         */
 150        apic->irr_pending = true;
 151}
 152
 153static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
 154{
 155        return *((u32 *) (apic->regs + reg_off));
 156}
 157
 158static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 159{
 160        *((u32 *) (apic->regs + reg_off)) = val;
 161}
 162
 163extern struct static_key kvm_no_apic_vcpu;
 164
 165static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
 166{
 167        if (static_key_false(&kvm_no_apic_vcpu))
 168                return vcpu->arch.apic;
 169        return true;
 170}
 171
 172extern struct static_key_deferred apic_hw_disabled;
 173
 174static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
 175{
 176        if (static_key_false(&apic_hw_disabled.key))
 177                return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 178        return MSR_IA32_APICBASE_ENABLE;
 179}
 180
 181extern struct static_key_deferred apic_sw_disabled;
 182
 183static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
 184{
 185        if (static_key_false(&apic_sw_disabled.key))
 186                return apic->sw_enabled;
 187        return true;
 188}
 189
 190static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
 191{
 192        return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
 193}
 194
 195static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 196{
 197        return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
 198}
 199
 200static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 201{
 202        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 203}
 204
 205static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
 206{
 207        return vcpu->arch.apic && vcpu->arch.apicv_active;
 208}
 209
 210static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
 211{
 212        return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
 213}
 214
 215static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
 216{
 217        return (irq->delivery_mode == APIC_DM_LOWEST ||
 218                        irq->msi_redir_hint);
 219}
 220
 221static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
 222{
 223        return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
 224}
 225
 226bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
 227
 228void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
 229
 230bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 231                        struct kvm_vcpu **dest_vcpu);
 232int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 233                        const unsigned long *bitmap, u32 bitmap_size);
 234void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
 235void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
 236void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
 237bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
 238void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
 239bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu);
 240
 241static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
 242{
 243        return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 244}
 245
 246#endif
 247