LXR linux/drivers/char/xillybus/xillybus.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * linux/drivers/misc/xillybus.h
   4 *
   5 * Copyright 2011 Xillybus Ltd, http://xillybus.com
   6 *
   7 * Header file for the Xillybus FPGA/host framework.
   8 */
   9
  10#ifndef __XILLYBUS_H
  11#define __XILLYBUS_H
  12
  13#include <linux/list.h>
  14#include <linux/device.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/interrupt.h>
  17#include <linux/sched.h>
  18#include <linux/cdev.h>
  19#include <linux/spinlock.h>
  20#include <linux/mutex.h>
  21#include <linux/workqueue.h>
  22
  23struct xilly_endpoint_hardware;
  24
  25struct xilly_buffer {
  26        void *addr;
  27        dma_addr_t dma_addr;
  28        int end_offset; /* Counting elements, not bytes */
  29};
  30
  31struct xilly_idt_handle {
  32        unsigned char *chandesc;
  33        unsigned char *idt;
  34        int entries;
  35};
  36
  37/*
  38 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
  39 * wr_* buffers are those consumed by read(), since the FPGA writes to them
  40 * and vice versa.
  41 */
  42
  43struct xilly_channel {
  44        struct xilly_endpoint *endpoint;
  45        int chan_num;
  46        int log2_element_size;
  47        int seekable;
  48
  49        struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
  50        int num_wr_buffers;
  51        unsigned int wr_buf_size; /* In bytes */
  52        int wr_fpga_buf_idx;
  53        int wr_host_buf_idx;
  54        int wr_host_buf_pos;
  55        int wr_empty;
  56        int wr_ready; /* Significant only when wr_empty == 1 */
  57        int wr_sleepy;
  58        int wr_eof;
  59        int wr_hangup;
  60        spinlock_t wr_spinlock;
  61        struct mutex wr_mutex;
  62        wait_queue_head_t wr_wait;
  63        wait_queue_head_t wr_ready_wait;
  64        int wr_ref_count;
  65        int wr_synchronous;
  66        int wr_allow_partial;
  67        int wr_exclusive_open;
  68        int wr_supports_nonempty;
  69
  70        struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
  71        int num_rd_buffers;
  72        unsigned int rd_buf_size; /* In bytes */
  73        int rd_fpga_buf_idx;
  74        int rd_host_buf_pos;
  75        int rd_host_buf_idx;
  76        int rd_full;
  77        spinlock_t rd_spinlock;
  78        struct mutex rd_mutex;
  79        wait_queue_head_t rd_wait;
  80        int rd_ref_count;
  81        int rd_allow_partial;
  82        int rd_synchronous;
  83        int rd_exclusive_open;
  84        struct delayed_work rd_workitem;
  85        unsigned char rd_leftovers[4];
  86};
  87
  88struct xilly_endpoint {
  89        /*
  90         * One of pdev and dev is always NULL, and the other is a valid
  91         * pointer, depending on the type of device
  92         */
  93        struct pci_dev *pdev;
  94        struct device *dev;
  95        struct xilly_endpoint_hardware *ephw;
  96
  97        struct list_head ep_list;
  98        int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
  99        __iomem void *registers;
 100        int fatal_error;
 101
 102        struct mutex register_mutex;
 103        wait_queue_head_t ep_wait;
 104
 105        /* Channels and message handling */
 106        struct cdev cdev;
 107
 108        int major;
 109        int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
 110
 111        int num_channels; /* EXCLUDING message buffer */
 112        struct xilly_channel **channels;
 113        int msg_counter;
 114        int failed_messages;
 115        int idtlen;
 116
 117        u32 *msgbuf_addr;
 118        dma_addr_t msgbuf_dma_addr;
 119        unsigned int msg_buf_size;
 120};
 121
 122struct xilly_endpoint_hardware {
 123        struct module *owner;
 124        void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
 125                                    dma_addr_t,
 126                                    size_t,
 127                                    int);
 128        void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
 129                                       dma_addr_t,
 130                                       size_t,
 131                                       int);
 132        int (*map_single)(struct xilly_endpoint *,
 133                          void *,
 134                          size_t,
 135                          int,
 136                          dma_addr_t *);
 137};
 138
 139struct xilly_mapping {
 140        void *device;
 141        dma_addr_t dma_addr;
 142        size_t size;
 143        int direction;
 144};
 145
 146irqreturn_t xillybus_isr(int irq, void *data);
 147
 148struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
 149                                              struct device *dev,
 150                                              struct xilly_endpoint_hardware
 151                                              *ephw);
 152
 153int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
 154
 155void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
 156
 157#endif /* __XILLYBUS_H */
 158