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6#include <linux/kernel.h>
7#include <linux/export.h>
8#include <linux/clk-provider.h>
9#include <linux/regmap.h>
10#include <linux/delay.h>
11
12#include "clk-alpha-pll.h"
13#include "common.h"
14
15#define PLL_MODE(p) ((p)->offset + 0x0)
16# define PLL_OUTCTRL BIT(0)
17# define PLL_BYPASSNL BIT(1)
18# define PLL_RESET_N BIT(2)
19# define PLL_OFFLINE_REQ BIT(7)
20# define PLL_LOCK_COUNT_SHIFT 8
21# define PLL_LOCK_COUNT_MASK 0x3f
22# define PLL_BIAS_COUNT_SHIFT 14
23# define PLL_BIAS_COUNT_MASK 0x3f
24# define PLL_VOTE_FSM_ENA BIT(20)
25# define PLL_FSM_ENA BIT(20)
26# define PLL_VOTE_FSM_RESET BIT(21)
27# define PLL_UPDATE BIT(22)
28# define PLL_UPDATE_BYPASS BIT(23)
29# define PLL_OFFLINE_ACK BIT(28)
30# define ALPHA_PLL_ACK_LATCH BIT(29)
31# define PLL_ACTIVE_FLAG BIT(30)
32# define PLL_LOCK_DET BIT(31)
33
34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
36#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
37
38#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
39# define PLL_POST_DIV_SHIFT 8
40# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
41# define PLL_ALPHA_EN BIT(24)
42# define PLL_ALPHA_MODE BIT(25)
43# define PLL_VCO_SHIFT 20
44# define PLL_VCO_MASK 0x3
45
46#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
47
48#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
49#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
50#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
51#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
52#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
53#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
54#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
55
56const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
58 [PLL_OFF_L_VAL] = 0x04,
59 [PLL_OFF_ALPHA_VAL] = 0x08,
60 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
61 [PLL_OFF_USER_CTL] = 0x10,
62 [PLL_OFF_USER_CTL_U] = 0x14,
63 [PLL_OFF_CONFIG_CTL] = 0x18,
64 [PLL_OFF_TEST_CTL] = 0x1c,
65 [PLL_OFF_TEST_CTL_U] = 0x20,
66 [PLL_OFF_STATUS] = 0x24,
67 },
68 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
69 [PLL_OFF_L_VAL] = 0x04,
70 [PLL_OFF_ALPHA_VAL] = 0x08,
71 [PLL_OFF_USER_CTL] = 0x10,
72 [PLL_OFF_CONFIG_CTL] = 0x14,
73 [PLL_OFF_CONFIG_CTL_U] = 0x18,
74 [PLL_OFF_TEST_CTL] = 0x1c,
75 [PLL_OFF_TEST_CTL_U] = 0x20,
76 [PLL_OFF_STATUS] = 0x24,
77 },
78 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
79 [PLL_OFF_L_VAL] = 0x04,
80 [PLL_OFF_ALPHA_VAL] = 0x08,
81 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
82 [PLL_OFF_USER_CTL] = 0x10,
83 [PLL_OFF_CONFIG_CTL] = 0x18,
84 [PLL_OFF_TEST_CTL] = 0x1c,
85 [PLL_OFF_STATUS] = 0x24,
86 },
87 [CLK_ALPHA_PLL_TYPE_FABIA] = {
88 [PLL_OFF_L_VAL] = 0x04,
89 [PLL_OFF_USER_CTL] = 0x0c,
90 [PLL_OFF_USER_CTL_U] = 0x10,
91 [PLL_OFF_CONFIG_CTL] = 0x14,
92 [PLL_OFF_CONFIG_CTL_U] = 0x18,
93 [PLL_OFF_TEST_CTL] = 0x1c,
94 [PLL_OFF_TEST_CTL_U] = 0x20,
95 [PLL_OFF_STATUS] = 0x24,
96 [PLL_OFF_OPMODE] = 0x2c,
97 [PLL_OFF_FRAC] = 0x38,
98 },
99};
100EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
101
102
103
104
105#define ALPHA_REG_BITWIDTH 40
106#define ALPHA_REG_16BIT_WIDTH 16
107#define ALPHA_BITWIDTH 32U
108#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
109
110#define PLL_HUAYRA_M_WIDTH 8
111#define PLL_HUAYRA_M_SHIFT 8
112#define PLL_HUAYRA_M_MASK 0xff
113#define PLL_HUAYRA_N_SHIFT 0
114#define PLL_HUAYRA_N_MASK 0xff
115#define PLL_HUAYRA_ALPHA_WIDTH 16
116
117#define FABIA_OPMODE_STANDBY 0x0
118#define FABIA_OPMODE_RUN 0x1
119
120#define FABIA_PLL_OUT_MASK 0x7
121#define FABIA_PLL_RATE_MARGIN 500
122
123#define pll_alpha_width(p) \
124 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
125 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
126
127#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
128
129#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
130 struct clk_alpha_pll, clkr)
131
132#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
133 struct clk_alpha_pll_postdiv, clkr)
134
135static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
136 const char *action)
137{
138 u32 val;
139 int count;
140 int ret;
141 const char *name = clk_hw_get_name(&pll->clkr.hw);
142
143 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
144 if (ret)
145 return ret;
146
147 for (count = 100; count > 0; count--) {
148 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
149 if (ret)
150 return ret;
151 if (inverse && !(val & mask))
152 return 0;
153 else if ((val & mask) == mask)
154 return 0;
155
156 udelay(1);
157 }
158
159 WARN(1, "%s failed to %s!\n", name, action);
160 return -ETIMEDOUT;
161}
162
163#define wait_for_pll_enable_active(pll) \
164 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
165
166#define wait_for_pll_enable_lock(pll) \
167 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
168
169#define wait_for_pll_disable(pll) \
170 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
171
172#define wait_for_pll_offline(pll) \
173 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
174
175#define wait_for_pll_update(pll) \
176 wait_for_pll(pll, PLL_UPDATE, 1, "update")
177
178#define wait_for_pll_update_ack_set(pll) \
179 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
180
181#define wait_for_pll_update_ack_clear(pll) \
182 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
183
184void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
185 const struct alpha_pll_config *config)
186{
187 u32 val, mask;
188
189 regmap_write(regmap, PLL_L_VAL(pll), config->l);
190 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
191 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
192
193 if (pll_has_64bit_config(pll))
194 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
195 config->config_ctl_hi_val);
196
197 if (pll_alpha_width(pll) > 32)
198 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
199
200 val = config->main_output_mask;
201 val |= config->aux_output_mask;
202 val |= config->aux2_output_mask;
203 val |= config->early_output_mask;
204 val |= config->pre_div_val;
205 val |= config->post_div_val;
206 val |= config->vco_val;
207 val |= config->alpha_en_mask;
208 val |= config->alpha_mode_mask;
209
210 mask = config->main_output_mask;
211 mask |= config->aux_output_mask;
212 mask |= config->aux2_output_mask;
213 mask |= config->early_output_mask;
214 mask |= config->pre_div_mask;
215 mask |= config->post_div_mask;
216 mask |= config->vco_mask;
217
218 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
219
220 if (pll->flags & SUPPORTS_FSM_MODE)
221 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
222}
223EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
224
225static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
226{
227 int ret;
228 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
229 u32 val;
230
231 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
232 if (ret)
233 return ret;
234
235 val |= PLL_FSM_ENA;
236
237 if (pll->flags & SUPPORTS_OFFLINE_REQ)
238 val &= ~PLL_OFFLINE_REQ;
239
240 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
241 if (ret)
242 return ret;
243
244
245 mb();
246
247 return wait_for_pll_enable_active(pll);
248}
249
250static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
251{
252 int ret;
253 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
254 u32 val;
255
256 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
257 if (ret)
258 return;
259
260 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
261 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
262 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
263 if (ret)
264 return;
265
266 ret = wait_for_pll_offline(pll);
267 if (ret)
268 return;
269 }
270
271
272 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
273 PLL_FSM_ENA, 0);
274 if (ret)
275 return;
276
277 wait_for_pll_disable(pll);
278}
279
280static int pll_is_enabled(struct clk_hw *hw, u32 mask)
281{
282 int ret;
283 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
284 u32 val;
285
286 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
287 if (ret)
288 return ret;
289
290 return !!(val & mask);
291}
292
293static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
294{
295 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
296}
297
298static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
299{
300 return pll_is_enabled(hw, PLL_LOCK_DET);
301}
302
303static int clk_alpha_pll_enable(struct clk_hw *hw)
304{
305 int ret;
306 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
307 u32 val, mask;
308
309 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
310 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
311 if (ret)
312 return ret;
313
314
315 if (val & PLL_VOTE_FSM_ENA) {
316 ret = clk_enable_regmap(hw);
317 if (ret)
318 return ret;
319 return wait_for_pll_enable_active(pll);
320 }
321
322
323 if ((val & mask) == mask)
324 return 0;
325
326 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
327 PLL_BYPASSNL, PLL_BYPASSNL);
328 if (ret)
329 return ret;
330
331
332
333
334
335 mb();
336 udelay(5);
337
338 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
339 PLL_RESET_N, PLL_RESET_N);
340 if (ret)
341 return ret;
342
343 ret = wait_for_pll_enable_lock(pll);
344 if (ret)
345 return ret;
346
347 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
348 PLL_OUTCTRL, PLL_OUTCTRL);
349
350
351 mb();
352 return ret;
353}
354
355static void clk_alpha_pll_disable(struct clk_hw *hw)
356{
357 int ret;
358 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
359 u32 val, mask;
360
361 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
362 if (ret)
363 return;
364
365
366 if (val & PLL_VOTE_FSM_ENA) {
367 clk_disable_regmap(hw);
368 return;
369 }
370
371 mask = PLL_OUTCTRL;
372 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
373
374
375 mb();
376 udelay(1);
377
378 mask = PLL_RESET_N | PLL_BYPASSNL;
379 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
380}
381
382static unsigned long
383alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
384{
385 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
386}
387
388static unsigned long
389alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
390 u32 alpha_width)
391{
392 u64 remainder;
393 u64 quotient;
394
395 quotient = rate;
396 remainder = do_div(quotient, prate);
397 *l = quotient;
398
399 if (!remainder) {
400 *a = 0;
401 return rate;
402 }
403
404
405 quotient = remainder << ALPHA_SHIFT(alpha_width);
406
407 remainder = do_div(quotient, prate);
408
409 if (remainder)
410 quotient++;
411
412 *a = quotient;
413 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
414}
415
416static const struct pll_vco *
417alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
418{
419 const struct pll_vco *v = pll->vco_table;
420 const struct pll_vco *end = v + pll->num_vco;
421
422 for (; v < end; v++)
423 if (rate >= v->min_freq && rate <= v->max_freq)
424 return v;
425
426 return NULL;
427}
428
429static unsigned long
430clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
431{
432 u32 l, low, high, ctl;
433 u64 a = 0, prate = parent_rate;
434 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
435 u32 alpha_width = pll_alpha_width(pll);
436
437 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
438
439 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
440 if (ctl & PLL_ALPHA_EN) {
441 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
442 if (alpha_width > 32) {
443 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
444 &high);
445 a = (u64)high << 32 | low;
446 } else {
447 a = low & GENMASK(alpha_width - 1, 0);
448 }
449
450 if (alpha_width > ALPHA_BITWIDTH)
451 a >>= alpha_width - ALPHA_BITWIDTH;
452 }
453
454 return alpha_pll_calc_rate(prate, l, a, alpha_width);
455}
456
457
458static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
459{
460 int ret;
461 u32 mode;
462
463 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
464
465
466 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
467 PLL_UPDATE);
468
469
470 udelay(1);
471
472
473
474
475
476
477
478
479 if (mode & PLL_UPDATE_BYPASS) {
480 ret = wait_for_pll_update_ack_set(pll);
481 if (ret)
482 return ret;
483
484 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
485 } else {
486 ret = wait_for_pll_update(pll);
487 if (ret)
488 return ret;
489 }
490
491 ret = wait_for_pll_update_ack_clear(pll);
492 if (ret)
493 return ret;
494
495
496 udelay(10);
497
498 return 0;
499}
500
501static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
502 int (*is_enabled)(struct clk_hw *))
503{
504 if (!is_enabled(&pll->clkr.hw) ||
505 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
506 return 0;
507
508 return __clk_alpha_pll_update_latch(pll);
509}
510
511static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
512 unsigned long prate,
513 int (*is_enabled)(struct clk_hw *))
514{
515 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
516 const struct pll_vco *vco;
517 u32 l, alpha_width = pll_alpha_width(pll);
518 u64 a;
519
520 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
521 vco = alpha_pll_find_vco(pll, rate);
522 if (pll->vco_table && !vco) {
523 pr_err("alpha pll not in a valid vco range\n");
524 return -EINVAL;
525 }
526
527 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
528
529 if (alpha_width > ALPHA_BITWIDTH)
530 a <<= alpha_width - ALPHA_BITWIDTH;
531
532 if (alpha_width > 32)
533 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
534
535 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
536
537 if (vco) {
538 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
539 PLL_VCO_MASK << PLL_VCO_SHIFT,
540 vco->val << PLL_VCO_SHIFT);
541 }
542
543 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
544 PLL_ALPHA_EN, PLL_ALPHA_EN);
545
546 return clk_alpha_pll_update_latch(pll, is_enabled);
547}
548
549static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
550 unsigned long prate)
551{
552 return __clk_alpha_pll_set_rate(hw, rate, prate,
553 clk_alpha_pll_is_enabled);
554}
555
556static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
557 unsigned long prate)
558{
559 return __clk_alpha_pll_set_rate(hw, rate, prate,
560 clk_alpha_pll_hwfsm_is_enabled);
561}
562
563static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
564 unsigned long *prate)
565{
566 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
567 u32 l, alpha_width = pll_alpha_width(pll);
568 u64 a;
569 unsigned long min_freq, max_freq;
570
571 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
572 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
573 return rate;
574
575 min_freq = pll->vco_table[0].min_freq;
576 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
577
578 return clamp(rate, min_freq, max_freq);
579}
580
581static unsigned long
582alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
583{
584
585
586
587
588 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
589 l -= 1;
590
591 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
592}
593
594static unsigned long
595alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
596 u32 *l, u32 *a)
597{
598 u64 remainder;
599 u64 quotient;
600
601 quotient = rate;
602 remainder = do_div(quotient, prate);
603 *l = quotient;
604
605 if (!remainder) {
606 *a = 0;
607 return rate;
608 }
609
610 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
611 remainder = do_div(quotient, prate);
612
613 if (remainder)
614 quotient++;
615
616
617
618
619
620
621 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
622 *l += 1;
623
624 *a = quotient;
625 return alpha_huayra_pll_calc_rate(prate, *l, *a);
626}
627
628static unsigned long
629alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
630{
631 u64 rate = parent_rate, tmp;
632 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
633 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
634
635 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
636 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
637
638 if (ctl & PLL_ALPHA_EN) {
639 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657 if (!(ctl & PLL_ALPHA_MODE))
658 return alpha_huayra_pll_calc_rate(rate, l, alpha);
659
660 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
661 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
662
663 rate *= l;
664 tmp = parent_rate;
665 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
666 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
667 tmp *= alpha_m;
668 do_div(tmp, alpha_n);
669 rate -= tmp;
670 } else {
671 tmp *= alpha_m;
672 do_div(tmp, alpha_n);
673 rate += tmp;
674 }
675
676 return rate;
677 }
678
679 return alpha_huayra_pll_calc_rate(rate, l, alpha);
680}
681
682static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
683 unsigned long prate)
684{
685 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
686 u32 l, a, ctl, cur_alpha = 0;
687
688 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
689
690 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
691
692 if (ctl & PLL_ALPHA_EN)
693 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
694
695
696
697
698
699 if (clk_alpha_pll_is_enabled(hw)) {
700 if (cur_alpha != a) {
701 pr_err("clock needs to be gated %s\n",
702 clk_hw_get_name(hw));
703 return -EBUSY;
704 }
705
706 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
707
708 mb();
709 return wait_for_pll_enable_lock(pll);
710 }
711
712 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
713 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
714
715 if (a == 0)
716 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
717 PLL_ALPHA_EN, 0x0);
718 else
719 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
720 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
721
722 return 0;
723}
724
725static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
726 unsigned long *prate)
727{
728 u32 l, a;
729
730 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
731}
732
733const struct clk_ops clk_alpha_pll_ops = {
734 .enable = clk_alpha_pll_enable,
735 .disable = clk_alpha_pll_disable,
736 .is_enabled = clk_alpha_pll_is_enabled,
737 .recalc_rate = clk_alpha_pll_recalc_rate,
738 .round_rate = clk_alpha_pll_round_rate,
739 .set_rate = clk_alpha_pll_set_rate,
740};
741EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
742
743const struct clk_ops clk_alpha_pll_huayra_ops = {
744 .enable = clk_alpha_pll_enable,
745 .disable = clk_alpha_pll_disable,
746 .is_enabled = clk_alpha_pll_is_enabled,
747 .recalc_rate = alpha_pll_huayra_recalc_rate,
748 .round_rate = alpha_pll_huayra_round_rate,
749 .set_rate = alpha_pll_huayra_set_rate,
750};
751EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
752
753const struct clk_ops clk_alpha_pll_hwfsm_ops = {
754 .enable = clk_alpha_pll_hwfsm_enable,
755 .disable = clk_alpha_pll_hwfsm_disable,
756 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
757 .recalc_rate = clk_alpha_pll_recalc_rate,
758 .round_rate = clk_alpha_pll_round_rate,
759 .set_rate = clk_alpha_pll_hwfsm_set_rate,
760};
761EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
762
763static unsigned long
764clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
765{
766 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
767 u32 ctl;
768
769 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
770
771 ctl >>= PLL_POST_DIV_SHIFT;
772 ctl &= PLL_POST_DIV_MASK(pll);
773
774 return parent_rate >> fls(ctl);
775}
776
777static const struct clk_div_table clk_alpha_div_table[] = {
778 { 0x0, 1 },
779 { 0x1, 2 },
780 { 0x3, 4 },
781 { 0x7, 8 },
782 { 0xf, 16 },
783 { }
784};
785
786static const struct clk_div_table clk_alpha_2bit_div_table[] = {
787 { 0x0, 1 },
788 { 0x1, 2 },
789 { 0x3, 4 },
790 { }
791};
792
793static long
794clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
795 unsigned long *prate)
796{
797 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
798 const struct clk_div_table *table;
799
800 if (pll->width == 2)
801 table = clk_alpha_2bit_div_table;
802 else
803 table = clk_alpha_div_table;
804
805 return divider_round_rate(hw, rate, prate, table,
806 pll->width, CLK_DIVIDER_POWER_OF_TWO);
807}
808
809static long
810clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
811 unsigned long *prate)
812{
813 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
814 u32 ctl, div;
815
816 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
817
818 ctl >>= PLL_POST_DIV_SHIFT;
819 ctl &= BIT(pll->width) - 1;
820 div = 1 << fls(ctl);
821
822 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
823 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
824
825 return DIV_ROUND_UP_ULL((u64)*prate, div);
826}
827
828static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
829 unsigned long parent_rate)
830{
831 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
832 int div;
833
834
835 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
836
837 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
838 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
839 div << PLL_POST_DIV_SHIFT);
840}
841
842const struct clk_ops clk_alpha_pll_postdiv_ops = {
843 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
844 .round_rate = clk_alpha_pll_postdiv_round_rate,
845 .set_rate = clk_alpha_pll_postdiv_set_rate,
846};
847EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
848
849const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
850 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
851 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
852};
853EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
854
855void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
856 const struct alpha_pll_config *config)
857{
858 u32 val, mask;
859
860 if (config->l)
861 regmap_write(regmap, PLL_L_VAL(pll), config->l);
862
863 if (config->alpha)
864 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
865
866 if (config->config_ctl_val)
867 regmap_write(regmap, PLL_CONFIG_CTL(pll),
868 config->config_ctl_val);
869
870 if (config->post_div_mask) {
871 mask = config->post_div_mask;
872 val = config->post_div_val;
873 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
874 }
875
876 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
877 PLL_UPDATE_BYPASS);
878
879 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
880}
881EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
882
883static int alpha_pll_fabia_enable(struct clk_hw *hw)
884{
885 int ret;
886 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
887 u32 val, opmode_val;
888 struct regmap *regmap = pll->clkr.regmap;
889
890 ret = regmap_read(regmap, PLL_MODE(pll), &val);
891 if (ret)
892 return ret;
893
894
895 if (val & PLL_VOTE_FSM_ENA) {
896 ret = clk_enable_regmap(hw);
897 if (ret)
898 return ret;
899 return wait_for_pll_enable_active(pll);
900 }
901
902 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
903 if (ret)
904 return ret;
905
906
907 if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
908 return 0;
909
910 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
911 if (ret)
912 return ret;
913
914 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
915 if (ret)
916 return ret;
917
918 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
919 PLL_RESET_N);
920 if (ret)
921 return ret;
922
923 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
924 if (ret)
925 return ret;
926
927 ret = wait_for_pll_enable_lock(pll);
928 if (ret)
929 return ret;
930
931 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
932 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
933 if (ret)
934 return ret;
935
936 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
937 PLL_OUTCTRL);
938}
939
940static void alpha_pll_fabia_disable(struct clk_hw *hw)
941{
942 int ret;
943 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
944 u32 val;
945 struct regmap *regmap = pll->clkr.regmap;
946
947 ret = regmap_read(regmap, PLL_MODE(pll), &val);
948 if (ret)
949 return;
950
951
952 if (val & PLL_FSM_ENA) {
953 clk_disable_regmap(hw);
954 return;
955 }
956
957 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
958 if (ret)
959 return;
960
961
962 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
963 0);
964 if (ret)
965 return;
966
967
968 regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
969}
970
971static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
972 unsigned long parent_rate)
973{
974 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
975 u32 l, frac, alpha_width = pll_alpha_width(pll);
976
977 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
978 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
979
980 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
981}
982
983static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
984 unsigned long prate)
985{
986 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
987 u32 val, l, alpha_width = pll_alpha_width(pll);
988 u64 a;
989 unsigned long rrate;
990 int ret = 0;
991
992 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
993 if (ret)
994 return ret;
995
996 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
997
998
999
1000
1001
1002 if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
1003 pr_err("Call set rate on the PLL with rounded rates!\n");
1004 return -EINVAL;
1005 }
1006
1007 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1008 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1009
1010 return __clk_alpha_pll_update_latch(pll);
1011}
1012
1013const struct clk_ops clk_alpha_pll_fabia_ops = {
1014 .enable = alpha_pll_fabia_enable,
1015 .disable = alpha_pll_fabia_disable,
1016 .is_enabled = clk_alpha_pll_is_enabled,
1017 .set_rate = alpha_pll_fabia_set_rate,
1018 .recalc_rate = alpha_pll_fabia_recalc_rate,
1019 .round_rate = clk_alpha_pll_round_rate,
1020};
1021EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1022
1023const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1024 .enable = alpha_pll_fabia_enable,
1025 .disable = alpha_pll_fabia_disable,
1026 .is_enabled = clk_alpha_pll_is_enabled,
1027 .recalc_rate = alpha_pll_fabia_recalc_rate,
1028 .round_rate = clk_alpha_pll_round_rate,
1029};
1030EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1031
1032static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1033 unsigned long parent_rate)
1034{
1035 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1036 u32 i, div = 1, val;
1037 int ret;
1038
1039 if (!pll->post_div_table) {
1040 pr_err("Missing the post_div_table for the PLL\n");
1041 return -EINVAL;
1042 }
1043
1044 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1045 if (ret)
1046 return ret;
1047
1048 val >>= pll->post_div_shift;
1049 val &= BIT(pll->width) - 1;
1050
1051 for (i = 0; i < pll->num_post_div; i++) {
1052 if (pll->post_div_table[i].val == val) {
1053 div = pll->post_div_table[i].div;
1054 break;
1055 }
1056 }
1057
1058 return (parent_rate / div);
1059}
1060
1061static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1062 unsigned long rate, unsigned long *prate)
1063{
1064 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1065
1066 if (!pll->post_div_table) {
1067 pr_err("Missing the post_div_table for the PLL\n");
1068 return -EINVAL;
1069 }
1070
1071 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1072 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1073}
1074
1075static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1076 unsigned long rate, unsigned long parent_rate)
1077{
1078 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1079 int i, val = 0, div, ret;
1080
1081
1082
1083
1084
1085 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1086 if (ret)
1087 return ret;
1088
1089 if (val & PLL_VOTE_FSM_ENA)
1090 return 0;
1091
1092 if (!pll->post_div_table) {
1093 pr_err("Missing the post_div_table for the PLL\n");
1094 return -EINVAL;
1095 }
1096
1097 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1098 for (i = 0; i < pll->num_post_div; i++) {
1099 if (pll->post_div_table[i].div == div) {
1100 val = pll->post_div_table[i].val;
1101 break;
1102 }
1103 }
1104
1105 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1106 (BIT(pll->width) - 1) << pll->post_div_shift,
1107 val << pll->post_div_shift);
1108}
1109
1110const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1111 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1112 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1113 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1114};
1115EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1116