linux/drivers/clk/qcom/gcc-msm8916.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright 2015 Linaro Limited
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/clk-provider.h>
  14#include <linux/regmap.h>
  15#include <linux/reset-controller.h>
  16
  17#include <dt-bindings/clock/qcom,gcc-msm8916.h>
  18#include <dt-bindings/reset/qcom,gcc-msm8916.h>
  19
  20#include "common.h"
  21#include "clk-regmap.h"
  22#include "clk-pll.h"
  23#include "clk-rcg.h"
  24#include "clk-branch.h"
  25#include "reset.h"
  26#include "gdsc.h"
  27
  28enum {
  29        P_XO,
  30        P_GPLL0,
  31        P_GPLL0_AUX,
  32        P_BIMC,
  33        P_GPLL1,
  34        P_GPLL1_AUX,
  35        P_GPLL2,
  36        P_GPLL2_AUX,
  37        P_SLEEP_CLK,
  38        P_DSI0_PHYPLL_BYTE,
  39        P_DSI0_PHYPLL_DSI,
  40        P_EXT_PRI_I2S,
  41        P_EXT_SEC_I2S,
  42        P_EXT_MCLK,
  43};
  44
  45static const struct parent_map gcc_xo_gpll0_map[] = {
  46        { P_XO, 0 },
  47        { P_GPLL0, 1 },
  48};
  49
  50static const char * const gcc_xo_gpll0[] = {
  51        "xo",
  52        "gpll0_vote",
  53};
  54
  55static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
  56        { P_XO, 0 },
  57        { P_GPLL0, 1 },
  58        { P_BIMC, 2 },
  59};
  60
  61static const char * const gcc_xo_gpll0_bimc[] = {
  62        "xo",
  63        "gpll0_vote",
  64        "bimc_pll_vote",
  65};
  66
  67static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
  68        { P_XO, 0 },
  69        { P_GPLL0_AUX, 3 },
  70        { P_GPLL1, 1 },
  71        { P_GPLL2_AUX, 2 },
  72};
  73
  74static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
  75        "xo",
  76        "gpll0_vote",
  77        "gpll1_vote",
  78        "gpll2_vote",
  79};
  80
  81static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
  82        { P_XO, 0 },
  83        { P_GPLL0, 1 },
  84        { P_GPLL2, 2 },
  85};
  86
  87static const char * const gcc_xo_gpll0_gpll2[] = {
  88        "xo",
  89        "gpll0_vote",
  90        "gpll2_vote",
  91};
  92
  93static const struct parent_map gcc_xo_gpll0a_map[] = {
  94        { P_XO, 0 },
  95        { P_GPLL0_AUX, 2 },
  96};
  97
  98static const char * const gcc_xo_gpll0a[] = {
  99        "xo",
 100        "gpll0_vote",
 101};
 102
 103static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 104        { P_XO, 0 },
 105        { P_GPLL0, 1 },
 106        { P_GPLL1_AUX, 2 },
 107        { P_SLEEP_CLK, 6 },
 108};
 109
 110static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
 111        "xo",
 112        "gpll0_vote",
 113        "gpll1_vote",
 114        "sleep_clk",
 115};
 116
 117static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 118        { P_XO, 0 },
 119        { P_GPLL0, 1 },
 120        { P_GPLL1_AUX, 2 },
 121};
 122
 123static const char * const gcc_xo_gpll0_gpll1a[] = {
 124        "xo",
 125        "gpll0_vote",
 126        "gpll1_vote",
 127};
 128
 129static const struct parent_map gcc_xo_dsibyte_map[] = {
 130        { P_XO, 0, },
 131        { P_DSI0_PHYPLL_BYTE, 2 },
 132};
 133
 134static const char * const gcc_xo_dsibyte[] = {
 135        "xo",
 136        "dsi0pllbyte",
 137};
 138
 139static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 140        { P_XO, 0 },
 141        { P_GPLL0_AUX, 2 },
 142        { P_DSI0_PHYPLL_BYTE, 1 },
 143};
 144
 145static const char * const gcc_xo_gpll0a_dsibyte[] = {
 146        "xo",
 147        "gpll0_vote",
 148        "dsi0pllbyte",
 149};
 150
 151static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
 152        { P_XO, 0 },
 153        { P_GPLL0, 1 },
 154        { P_DSI0_PHYPLL_DSI, 2 },
 155};
 156
 157static const char * const gcc_xo_gpll0_dsiphy[] = {
 158        "xo",
 159        "gpll0_vote",
 160        "dsi0pll",
 161};
 162
 163static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 164        { P_XO, 0 },
 165        { P_GPLL0_AUX, 2 },
 166        { P_DSI0_PHYPLL_DSI, 1 },
 167};
 168
 169static const char * const gcc_xo_gpll0a_dsiphy[] = {
 170        "xo",
 171        "gpll0_vote",
 172        "dsi0pll",
 173};
 174
 175static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
 176        { P_XO, 0 },
 177        { P_GPLL0_AUX, 1 },
 178        { P_GPLL1, 3 },
 179        { P_GPLL2, 2 },
 180};
 181
 182static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
 183        "xo",
 184        "gpll0_vote",
 185        "gpll1_vote",
 186        "gpll2_vote",
 187};
 188
 189static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 190        { P_XO, 0 },
 191        { P_GPLL0, 1 },
 192        { P_GPLL1, 2 },
 193        { P_SLEEP_CLK, 6 }
 194};
 195
 196static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
 197        "xo",
 198        "gpll0_vote",
 199        "gpll1_vote",
 200        "sleep_clk",
 201};
 202
 203static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 204        { P_XO, 0 },
 205        { P_GPLL1, 1 },
 206        { P_EXT_PRI_I2S, 2 },
 207        { P_EXT_MCLK, 3 },
 208        { P_SLEEP_CLK, 6 }
 209};
 210
 211static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
 212        "xo",
 213        "gpll1_vote",
 214        "ext_pri_i2s",
 215        "ext_mclk",
 216        "sleep_clk",
 217};
 218
 219static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 220        { P_XO, 0 },
 221        { P_GPLL1, 1 },
 222        { P_EXT_SEC_I2S, 2 },
 223        { P_EXT_MCLK, 3 },
 224        { P_SLEEP_CLK, 6 }
 225};
 226
 227static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
 228        "xo",
 229        "gpll1_vote",
 230        "ext_sec_i2s",
 231        "ext_mclk",
 232        "sleep_clk",
 233};
 234
 235static const struct parent_map gcc_xo_sleep_map[] = {
 236        { P_XO, 0 },
 237        { P_SLEEP_CLK, 6 }
 238};
 239
 240static const char * const gcc_xo_sleep[] = {
 241        "xo",
 242        "sleep_clk",
 243};
 244
 245static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 246        { P_XO, 0 },
 247        { P_GPLL1, 1 },
 248        { P_EXT_MCLK, 2 },
 249        { P_SLEEP_CLK, 6 }
 250};
 251
 252static const char * const gcc_xo_gpll1_emclk_sleep[] = {
 253        "xo",
 254        "gpll1_vote",
 255        "ext_mclk",
 256        "sleep_clk",
 257};
 258
 259static struct clk_pll gpll0 = {
 260        .l_reg = 0x21004,
 261        .m_reg = 0x21008,
 262        .n_reg = 0x2100c,
 263        .config_reg = 0x21014,
 264        .mode_reg = 0x21000,
 265        .status_reg = 0x2101c,
 266        .status_bit = 17,
 267        .clkr.hw.init = &(struct clk_init_data){
 268                .name = "gpll0",
 269                .parent_names = (const char *[]){ "xo" },
 270                .num_parents = 1,
 271                .ops = &clk_pll_ops,
 272        },
 273};
 274
 275static struct clk_regmap gpll0_vote = {
 276        .enable_reg = 0x45000,
 277        .enable_mask = BIT(0),
 278        .hw.init = &(struct clk_init_data){
 279                .name = "gpll0_vote",
 280                .parent_names = (const char *[]){ "gpll0" },
 281                .num_parents = 1,
 282                .ops = &clk_pll_vote_ops,
 283        },
 284};
 285
 286static struct clk_pll gpll1 = {
 287        .l_reg = 0x20004,
 288        .m_reg = 0x20008,
 289        .n_reg = 0x2000c,
 290        .config_reg = 0x20014,
 291        .mode_reg = 0x20000,
 292        .status_reg = 0x2001c,
 293        .status_bit = 17,
 294        .clkr.hw.init = &(struct clk_init_data){
 295                .name = "gpll1",
 296                .parent_names = (const char *[]){ "xo" },
 297                .num_parents = 1,
 298                .ops = &clk_pll_ops,
 299        },
 300};
 301
 302static struct clk_regmap gpll1_vote = {
 303        .enable_reg = 0x45000,
 304        .enable_mask = BIT(1),
 305        .hw.init = &(struct clk_init_data){
 306                .name = "gpll1_vote",
 307                .parent_names = (const char *[]){ "gpll1" },
 308                .num_parents = 1,
 309                .ops = &clk_pll_vote_ops,
 310        },
 311};
 312
 313static struct clk_pll gpll2 = {
 314        .l_reg = 0x4a004,
 315        .m_reg = 0x4a008,
 316        .n_reg = 0x4a00c,
 317        .config_reg = 0x4a014,
 318        .mode_reg = 0x4a000,
 319        .status_reg = 0x4a01c,
 320        .status_bit = 17,
 321        .clkr.hw.init = &(struct clk_init_data){
 322                .name = "gpll2",
 323                .parent_names = (const char *[]){ "xo" },
 324                .num_parents = 1,
 325                .ops = &clk_pll_ops,
 326        },
 327};
 328
 329static struct clk_regmap gpll2_vote = {
 330        .enable_reg = 0x45000,
 331        .enable_mask = BIT(2),
 332        .hw.init = &(struct clk_init_data){
 333                .name = "gpll2_vote",
 334                .parent_names = (const char *[]){ "gpll2" },
 335                .num_parents = 1,
 336                .ops = &clk_pll_vote_ops,
 337        },
 338};
 339
 340static struct clk_pll bimc_pll = {
 341        .l_reg = 0x23004,
 342        .m_reg = 0x23008,
 343        .n_reg = 0x2300c,
 344        .config_reg = 0x23014,
 345        .mode_reg = 0x23000,
 346        .status_reg = 0x2301c,
 347        .status_bit = 17,
 348        .clkr.hw.init = &(struct clk_init_data){
 349                .name = "bimc_pll",
 350                .parent_names = (const char *[]){ "xo" },
 351                .num_parents = 1,
 352                .ops = &clk_pll_ops,
 353        },
 354};
 355
 356static struct clk_regmap bimc_pll_vote = {
 357        .enable_reg = 0x45000,
 358        .enable_mask = BIT(3),
 359        .hw.init = &(struct clk_init_data){
 360                .name = "bimc_pll_vote",
 361                .parent_names = (const char *[]){ "bimc_pll" },
 362                .num_parents = 1,
 363                .ops = &clk_pll_vote_ops,
 364        },
 365};
 366
 367static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 368        .cmd_rcgr = 0x27000,
 369        .hid_width = 5,
 370        .parent_map = gcc_xo_gpll0_bimc_map,
 371        .clkr.hw.init = &(struct clk_init_data){
 372                .name = "pcnoc_bfdcd_clk_src",
 373                .parent_names = gcc_xo_gpll0_bimc,
 374                .num_parents = 3,
 375                .ops = &clk_rcg2_ops,
 376        },
 377};
 378
 379static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 380        .cmd_rcgr = 0x26004,
 381        .hid_width = 5,
 382        .parent_map = gcc_xo_gpll0_bimc_map,
 383        .clkr.hw.init = &(struct clk_init_data){
 384                .name = "system_noc_bfdcd_clk_src",
 385                .parent_names = gcc_xo_gpll0_bimc,
 386                .num_parents = 3,
 387                .ops = &clk_rcg2_ops,
 388        },
 389};
 390
 391static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 392        F(40000000, P_GPLL0, 10, 1, 2),
 393        F(80000000, P_GPLL0, 10, 0, 0),
 394        { }
 395};
 396
 397static struct clk_rcg2 camss_ahb_clk_src = {
 398        .cmd_rcgr = 0x5a000,
 399        .mnd_width = 8,
 400        .hid_width = 5,
 401        .parent_map = gcc_xo_gpll0_map,
 402        .freq_tbl = ftbl_gcc_camss_ahb_clk,
 403        .clkr.hw.init = &(struct clk_init_data){
 404                .name = "camss_ahb_clk_src",
 405                .parent_names = gcc_xo_gpll0,
 406                .num_parents = 2,
 407                .ops = &clk_rcg2_ops,
 408        },
 409};
 410
 411static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 412        F(19200000, P_XO, 1, 0, 0),
 413        F(50000000, P_GPLL0, 16, 0, 0),
 414        F(100000000, P_GPLL0, 8, 0, 0),
 415        F(133330000, P_GPLL0, 6, 0, 0),
 416        { }
 417};
 418
 419static struct clk_rcg2 apss_ahb_clk_src = {
 420        .cmd_rcgr = 0x46000,
 421        .hid_width = 5,
 422        .parent_map = gcc_xo_gpll0_map,
 423        .freq_tbl = ftbl_apss_ahb_clk,
 424        .clkr.hw.init = &(struct clk_init_data){
 425                .name = "apss_ahb_clk_src",
 426                .parent_names = gcc_xo_gpll0,
 427                .num_parents = 2,
 428                .ops = &clk_rcg2_ops,
 429        },
 430};
 431
 432static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 433        F(100000000, P_GPLL0, 8, 0,     0),
 434        F(200000000, P_GPLL0, 4, 0,     0),
 435        { }
 436};
 437
 438static struct clk_rcg2 csi0_clk_src = {
 439        .cmd_rcgr = 0x4e020,
 440        .hid_width = 5,
 441        .parent_map = gcc_xo_gpll0_map,
 442        .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 443        .clkr.hw.init = &(struct clk_init_data){
 444                .name = "csi0_clk_src",
 445                .parent_names = gcc_xo_gpll0,
 446                .num_parents = 2,
 447                .ops = &clk_rcg2_ops,
 448        },
 449};
 450
 451static struct clk_rcg2 csi1_clk_src = {
 452        .cmd_rcgr = 0x4f020,
 453        .hid_width = 5,
 454        .parent_map = gcc_xo_gpll0_map,
 455        .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 456        .clkr.hw.init = &(struct clk_init_data){
 457                .name = "csi1_clk_src",
 458                .parent_names = gcc_xo_gpll0,
 459                .num_parents = 2,
 460                .ops = &clk_rcg2_ops,
 461        },
 462};
 463
 464static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 465        F(19200000, P_XO, 1, 0, 0),
 466        F(50000000, P_GPLL0_AUX, 16, 0, 0),
 467        F(80000000, P_GPLL0_AUX, 10, 0, 0),
 468        F(100000000, P_GPLL0_AUX, 8, 0, 0),
 469        F(160000000, P_GPLL0_AUX, 5, 0, 0),
 470        F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
 471        F(200000000, P_GPLL0_AUX, 4, 0, 0),
 472        F(266670000, P_GPLL0_AUX, 3, 0, 0),
 473        F(294912000, P_GPLL1, 3, 0, 0),
 474        F(310000000, P_GPLL2, 3, 0, 0),
 475        F(400000000, P_GPLL0_AUX, 2, 0, 0),
 476        { }
 477};
 478
 479static struct clk_rcg2 gfx3d_clk_src = {
 480        .cmd_rcgr = 0x59000,
 481        .hid_width = 5,
 482        .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
 483        .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 484        .clkr.hw.init = &(struct clk_init_data){
 485                .name = "gfx3d_clk_src",
 486                .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
 487                .num_parents = 4,
 488                .ops = &clk_rcg2_ops,
 489        },
 490};
 491
 492static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 493        F(50000000, P_GPLL0, 16, 0, 0),
 494        F(80000000, P_GPLL0, 10, 0, 0),
 495        F(100000000, P_GPLL0, 8, 0, 0),
 496        F(160000000, P_GPLL0, 5, 0, 0),
 497        F(177780000, P_GPLL0, 4.5, 0, 0),
 498        F(200000000, P_GPLL0, 4, 0, 0),
 499        F(266670000, P_GPLL0, 3, 0, 0),
 500        F(320000000, P_GPLL0, 2.5, 0, 0),
 501        F(400000000, P_GPLL0, 2, 0, 0),
 502        F(465000000, P_GPLL2, 2, 0, 0),
 503        { }
 504};
 505
 506static struct clk_rcg2 vfe0_clk_src = {
 507        .cmd_rcgr = 0x58000,
 508        .hid_width = 5,
 509        .parent_map = gcc_xo_gpll0_gpll2_map,
 510        .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 511        .clkr.hw.init = &(struct clk_init_data){
 512                .name = "vfe0_clk_src",
 513                .parent_names = gcc_xo_gpll0_gpll2,
 514                .num_parents = 3,
 515                .ops = &clk_rcg2_ops,
 516        },
 517};
 518
 519static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 520        F(19200000, P_XO, 1, 0, 0),
 521        F(50000000, P_GPLL0, 16, 0, 0),
 522        { }
 523};
 524
 525static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 526        .cmd_rcgr = 0x0200c,
 527        .hid_width = 5,
 528        .parent_map = gcc_xo_gpll0_map,
 529        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 530        .clkr.hw.init = &(struct clk_init_data){
 531                .name = "blsp1_qup1_i2c_apps_clk_src",
 532                .parent_names = gcc_xo_gpll0,
 533                .num_parents = 2,
 534                .ops = &clk_rcg2_ops,
 535        },
 536};
 537
 538static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 539        F(100000, P_XO, 16, 2, 24),
 540        F(250000, P_XO, 16, 5, 24),
 541        F(500000, P_XO, 8, 5, 24),
 542        F(960000, P_XO, 10, 1, 2),
 543        F(1000000, P_XO, 4, 5, 24),
 544        F(4800000, P_XO, 4, 0, 0),
 545        F(9600000, P_XO, 2, 0, 0),
 546        F(16000000, P_GPLL0, 10, 1, 5),
 547        F(19200000, P_XO, 1, 0, 0),
 548        F(25000000, P_GPLL0, 16, 1, 2),
 549        F(50000000, P_GPLL0, 16, 0, 0),
 550        { }
 551};
 552
 553static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 554        .cmd_rcgr = 0x02024,
 555        .mnd_width = 8,
 556        .hid_width = 5,
 557        .parent_map = gcc_xo_gpll0_map,
 558        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 559        .clkr.hw.init = &(struct clk_init_data){
 560                .name = "blsp1_qup1_spi_apps_clk_src",
 561                .parent_names = gcc_xo_gpll0,
 562                .num_parents = 2,
 563                .ops = &clk_rcg2_ops,
 564        },
 565};
 566
 567static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 568        .cmd_rcgr = 0x03000,
 569        .hid_width = 5,
 570        .parent_map = gcc_xo_gpll0_map,
 571        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 572        .clkr.hw.init = &(struct clk_init_data){
 573                .name = "blsp1_qup2_i2c_apps_clk_src",
 574                .parent_names = gcc_xo_gpll0,
 575                .num_parents = 2,
 576                .ops = &clk_rcg2_ops,
 577        },
 578};
 579
 580static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 581        .cmd_rcgr = 0x03014,
 582        .mnd_width = 8,
 583        .hid_width = 5,
 584        .parent_map = gcc_xo_gpll0_map,
 585        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 586        .clkr.hw.init = &(struct clk_init_data){
 587                .name = "blsp1_qup2_spi_apps_clk_src",
 588                .parent_names = gcc_xo_gpll0,
 589                .num_parents = 2,
 590                .ops = &clk_rcg2_ops,
 591        },
 592};
 593
 594static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 595        .cmd_rcgr = 0x04000,
 596        .hid_width = 5,
 597        .parent_map = gcc_xo_gpll0_map,
 598        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 599        .clkr.hw.init = &(struct clk_init_data){
 600                .name = "blsp1_qup3_i2c_apps_clk_src",
 601                .parent_names = gcc_xo_gpll0,
 602                .num_parents = 2,
 603                .ops = &clk_rcg2_ops,
 604        },
 605};
 606
 607static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 608        .cmd_rcgr = 0x04024,
 609        .mnd_width = 8,
 610        .hid_width = 5,
 611        .parent_map = gcc_xo_gpll0_map,
 612        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 613        .clkr.hw.init = &(struct clk_init_data){
 614                .name = "blsp1_qup3_spi_apps_clk_src",
 615                .parent_names = gcc_xo_gpll0,
 616                .num_parents = 2,
 617                .ops = &clk_rcg2_ops,
 618        },
 619};
 620
 621static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 622        .cmd_rcgr = 0x05000,
 623        .hid_width = 5,
 624        .parent_map = gcc_xo_gpll0_map,
 625        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 626        .clkr.hw.init = &(struct clk_init_data){
 627                .name = "blsp1_qup4_i2c_apps_clk_src",
 628                .parent_names = gcc_xo_gpll0,
 629                .num_parents = 2,
 630                .ops = &clk_rcg2_ops,
 631        },
 632};
 633
 634static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 635        .cmd_rcgr = 0x05024,
 636        .mnd_width = 8,
 637        .hid_width = 5,
 638        .parent_map = gcc_xo_gpll0_map,
 639        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 640        .clkr.hw.init = &(struct clk_init_data){
 641                .name = "blsp1_qup4_spi_apps_clk_src",
 642                .parent_names = gcc_xo_gpll0,
 643                .num_parents = 2,
 644                .ops = &clk_rcg2_ops,
 645        },
 646};
 647
 648static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 649        .cmd_rcgr = 0x06000,
 650        .hid_width = 5,
 651        .parent_map = gcc_xo_gpll0_map,
 652        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 653        .clkr.hw.init = &(struct clk_init_data){
 654                .name = "blsp1_qup5_i2c_apps_clk_src",
 655                .parent_names = gcc_xo_gpll0,
 656                .num_parents = 2,
 657                .ops = &clk_rcg2_ops,
 658        },
 659};
 660
 661static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 662        .cmd_rcgr = 0x06024,
 663        .mnd_width = 8,
 664        .hid_width = 5,
 665        .parent_map = gcc_xo_gpll0_map,
 666        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 667        .clkr.hw.init = &(struct clk_init_data){
 668                .name = "blsp1_qup5_spi_apps_clk_src",
 669                .parent_names = gcc_xo_gpll0,
 670                .num_parents = 2,
 671                .ops = &clk_rcg2_ops,
 672        },
 673};
 674
 675static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 676        .cmd_rcgr = 0x07000,
 677        .hid_width = 5,
 678        .parent_map = gcc_xo_gpll0_map,
 679        .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 680        .clkr.hw.init = &(struct clk_init_data){
 681                .name = "blsp1_qup6_i2c_apps_clk_src",
 682                .parent_names = gcc_xo_gpll0,
 683                .num_parents = 2,
 684                .ops = &clk_rcg2_ops,
 685        },
 686};
 687
 688static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 689        .cmd_rcgr = 0x07024,
 690        .mnd_width = 8,
 691        .hid_width = 5,
 692        .parent_map = gcc_xo_gpll0_map,
 693        .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 694        .clkr.hw.init = &(struct clk_init_data){
 695                .name = "blsp1_qup6_spi_apps_clk_src",
 696                .parent_names = gcc_xo_gpll0,
 697                .num_parents = 2,
 698                .ops = &clk_rcg2_ops,
 699        },
 700};
 701
 702static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 703        F(3686400, P_GPLL0, 1, 72, 15625),
 704        F(7372800, P_GPLL0, 1, 144, 15625),
 705        F(14745600, P_GPLL0, 1, 288, 15625),
 706        F(16000000, P_GPLL0, 10, 1, 5),
 707        F(19200000, P_XO, 1, 0, 0),
 708        F(24000000, P_GPLL0, 1, 3, 100),
 709        F(25000000, P_GPLL0, 16, 1, 2),
 710        F(32000000, P_GPLL0, 1, 1, 25),
 711        F(40000000, P_GPLL0, 1, 1, 20),
 712        F(46400000, P_GPLL0, 1, 29, 500),
 713        F(48000000, P_GPLL0, 1, 3, 50),
 714        F(51200000, P_GPLL0, 1, 8, 125),
 715        F(56000000, P_GPLL0, 1, 7, 100),
 716        F(58982400, P_GPLL0, 1, 1152, 15625),
 717        F(60000000, P_GPLL0, 1, 3, 40),
 718        { }
 719};
 720
 721static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 722        .cmd_rcgr = 0x02044,
 723        .mnd_width = 16,
 724        .hid_width = 5,
 725        .parent_map = gcc_xo_gpll0_map,
 726        .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 727        .clkr.hw.init = &(struct clk_init_data){
 728                .name = "blsp1_uart1_apps_clk_src",
 729                .parent_names = gcc_xo_gpll0,
 730                .num_parents = 2,
 731                .ops = &clk_rcg2_ops,
 732        },
 733};
 734
 735static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 736        .cmd_rcgr = 0x03034,
 737        .mnd_width = 16,
 738        .hid_width = 5,
 739        .parent_map = gcc_xo_gpll0_map,
 740        .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 741        .clkr.hw.init = &(struct clk_init_data){
 742                .name = "blsp1_uart2_apps_clk_src",
 743                .parent_names = gcc_xo_gpll0,
 744                .num_parents = 2,
 745                .ops = &clk_rcg2_ops,
 746        },
 747};
 748
 749static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
 750        F(19200000,     P_XO, 1, 0,     0),
 751        { }
 752};
 753
 754static struct clk_rcg2 cci_clk_src = {
 755        .cmd_rcgr = 0x51000,
 756        .mnd_width = 8,
 757        .hid_width = 5,
 758        .parent_map = gcc_xo_gpll0a_map,
 759        .freq_tbl = ftbl_gcc_camss_cci_clk,
 760        .clkr.hw.init = &(struct clk_init_data){
 761                .name = "cci_clk_src",
 762                .parent_names = gcc_xo_gpll0a,
 763                .num_parents = 2,
 764                .ops = &clk_rcg2_ops,
 765        },
 766};
 767
 768static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
 769        F(100000000, P_GPLL0, 8, 0, 0),
 770        F(200000000, P_GPLL0, 4, 0, 0),
 771        { }
 772};
 773
 774static struct clk_rcg2 camss_gp0_clk_src = {
 775        .cmd_rcgr = 0x54000,
 776        .mnd_width = 8,
 777        .hid_width = 5,
 778        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 779        .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 780        .clkr.hw.init = &(struct clk_init_data){
 781                .name = "camss_gp0_clk_src",
 782                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 783                .num_parents = 4,
 784                .ops = &clk_rcg2_ops,
 785        },
 786};
 787
 788static struct clk_rcg2 camss_gp1_clk_src = {
 789        .cmd_rcgr = 0x55000,
 790        .mnd_width = 8,
 791        .hid_width = 5,
 792        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 793        .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 794        .clkr.hw.init = &(struct clk_init_data){
 795                .name = "camss_gp1_clk_src",
 796                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 797                .num_parents = 4,
 798                .ops = &clk_rcg2_ops,
 799        },
 800};
 801
 802static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
 803        F(133330000, P_GPLL0, 6, 0,     0),
 804        F(266670000, P_GPLL0, 3, 0,     0),
 805        F(320000000, P_GPLL0, 2.5, 0, 0),
 806        { }
 807};
 808
 809static struct clk_rcg2 jpeg0_clk_src = {
 810        .cmd_rcgr = 0x57000,
 811        .hid_width = 5,
 812        .parent_map = gcc_xo_gpll0_map,
 813        .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
 814        .clkr.hw.init = &(struct clk_init_data){
 815                .name = "jpeg0_clk_src",
 816                .parent_names = gcc_xo_gpll0,
 817                .num_parents = 2,
 818                .ops = &clk_rcg2_ops,
 819        },
 820};
 821
 822static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
 823        F(9600000, P_XO, 2, 0, 0),
 824        F(23880000, P_GPLL0, 1, 2, 67),
 825        F(66670000, P_GPLL0, 12, 0, 0),
 826        { }
 827};
 828
 829static struct clk_rcg2 mclk0_clk_src = {
 830        .cmd_rcgr = 0x52000,
 831        .mnd_width = 8,
 832        .hid_width = 5,
 833        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 834        .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 835        .clkr.hw.init = &(struct clk_init_data){
 836                .name = "mclk0_clk_src",
 837                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 838                .num_parents = 4,
 839                .ops = &clk_rcg2_ops,
 840        },
 841};
 842
 843static struct clk_rcg2 mclk1_clk_src = {
 844        .cmd_rcgr = 0x53000,
 845        .mnd_width = 8,
 846        .hid_width = 5,
 847        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 848        .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 849        .clkr.hw.init = &(struct clk_init_data){
 850                .name = "mclk1_clk_src",
 851                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 852                .num_parents = 4,
 853                .ops = &clk_rcg2_ops,
 854        },
 855};
 856
 857static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
 858        F(100000000, P_GPLL0, 8, 0,     0),
 859        F(200000000, P_GPLL0, 4, 0,     0),
 860        { }
 861};
 862
 863static struct clk_rcg2 csi0phytimer_clk_src = {
 864        .cmd_rcgr = 0x4e000,
 865        .hid_width = 5,
 866        .parent_map = gcc_xo_gpll0_gpll1a_map,
 867        .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 868        .clkr.hw.init = &(struct clk_init_data){
 869                .name = "csi0phytimer_clk_src",
 870                .parent_names = gcc_xo_gpll0_gpll1a,
 871                .num_parents = 3,
 872                .ops = &clk_rcg2_ops,
 873        },
 874};
 875
 876static struct clk_rcg2 csi1phytimer_clk_src = {
 877        .cmd_rcgr = 0x4f000,
 878        .hid_width = 5,
 879        .parent_map = gcc_xo_gpll0_gpll1a_map,
 880        .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 881        .clkr.hw.init = &(struct clk_init_data){
 882                .name = "csi1phytimer_clk_src",
 883                .parent_names = gcc_xo_gpll0_gpll1a,
 884                .num_parents = 3,
 885                .ops = &clk_rcg2_ops,
 886        },
 887};
 888
 889static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
 890        F(160000000, P_GPLL0, 5, 0, 0),
 891        F(320000000, P_GPLL0, 2.5, 0, 0),
 892        F(465000000, P_GPLL2, 2, 0, 0),
 893        { }
 894};
 895
 896static struct clk_rcg2 cpp_clk_src = {
 897        .cmd_rcgr = 0x58018,
 898        .hid_width = 5,
 899        .parent_map = gcc_xo_gpll0_gpll2_map,
 900        .freq_tbl = ftbl_gcc_camss_cpp_clk,
 901        .clkr.hw.init = &(struct clk_init_data){
 902                .name = "cpp_clk_src",
 903                .parent_names = gcc_xo_gpll0_gpll2,
 904                .num_parents = 3,
 905                .ops = &clk_rcg2_ops,
 906        },
 907};
 908
 909static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 910        F(50000000, P_GPLL0, 16, 0, 0),
 911        F(80000000, P_GPLL0, 10, 0, 0),
 912        F(100000000, P_GPLL0, 8, 0, 0),
 913        F(160000000, P_GPLL0, 5, 0, 0),
 914        { }
 915};
 916
 917static struct clk_rcg2 crypto_clk_src = {
 918        .cmd_rcgr = 0x16004,
 919        .hid_width = 5,
 920        .parent_map = gcc_xo_gpll0_map,
 921        .freq_tbl = ftbl_gcc_crypto_clk,
 922        .clkr.hw.init = &(struct clk_init_data){
 923                .name = "crypto_clk_src",
 924                .parent_names = gcc_xo_gpll0,
 925                .num_parents = 2,
 926                .ops = &clk_rcg2_ops,
 927        },
 928};
 929
 930static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 931        F(19200000, P_XO, 1, 0, 0),
 932        { }
 933};
 934
 935static struct clk_rcg2 gp1_clk_src = {
 936        .cmd_rcgr = 0x08004,
 937        .mnd_width = 8,
 938        .hid_width = 5,
 939        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 940        .freq_tbl = ftbl_gcc_gp1_3_clk,
 941        .clkr.hw.init = &(struct clk_init_data){
 942                .name = "gp1_clk_src",
 943                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 944                .num_parents = 3,
 945                .ops = &clk_rcg2_ops,
 946        },
 947};
 948
 949static struct clk_rcg2 gp2_clk_src = {
 950        .cmd_rcgr = 0x09004,
 951        .mnd_width = 8,
 952        .hid_width = 5,
 953        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 954        .freq_tbl = ftbl_gcc_gp1_3_clk,
 955        .clkr.hw.init = &(struct clk_init_data){
 956                .name = "gp2_clk_src",
 957                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 958                .num_parents = 3,
 959                .ops = &clk_rcg2_ops,
 960        },
 961};
 962
 963static struct clk_rcg2 gp3_clk_src = {
 964        .cmd_rcgr = 0x0a004,
 965        .mnd_width = 8,
 966        .hid_width = 5,
 967        .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 968        .freq_tbl = ftbl_gcc_gp1_3_clk,
 969        .clkr.hw.init = &(struct clk_init_data){
 970                .name = "gp3_clk_src",
 971                .parent_names = gcc_xo_gpll0_gpll1a_sleep,
 972                .num_parents = 3,
 973                .ops = &clk_rcg2_ops,
 974        },
 975};
 976
 977static struct clk_rcg2 byte0_clk_src = {
 978        .cmd_rcgr = 0x4d044,
 979        .hid_width = 5,
 980        .parent_map = gcc_xo_gpll0a_dsibyte_map,
 981        .clkr.hw.init = &(struct clk_init_data){
 982                .name = "byte0_clk_src",
 983                .parent_names = gcc_xo_gpll0a_dsibyte,
 984                .num_parents = 3,
 985                .ops = &clk_byte2_ops,
 986                .flags = CLK_SET_RATE_PARENT,
 987        },
 988};
 989
 990static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
 991        F(19200000, P_XO, 1, 0, 0),
 992        { }
 993};
 994
 995static struct clk_rcg2 esc0_clk_src = {
 996        .cmd_rcgr = 0x4d05c,
 997        .hid_width = 5,
 998        .parent_map = gcc_xo_dsibyte_map,
 999        .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1000        .clkr.hw.init = &(struct clk_init_data){
1001                .name = "esc0_clk_src",
1002                .parent_names = gcc_xo_dsibyte,
1003                .num_parents = 2,
1004                .ops = &clk_rcg2_ops,
1005        },
1006};
1007
1008static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1009        F(50000000, P_GPLL0, 16, 0, 0),
1010        F(80000000, P_GPLL0, 10, 0, 0),
1011        F(100000000, P_GPLL0, 8, 0, 0),
1012        F(160000000, P_GPLL0, 5, 0, 0),
1013        F(177780000, P_GPLL0, 4.5, 0, 0),
1014        F(200000000, P_GPLL0, 4, 0, 0),
1015        F(266670000, P_GPLL0, 3, 0, 0),
1016        F(320000000, P_GPLL0, 2.5, 0, 0),
1017        { }
1018};
1019
1020static struct clk_rcg2 mdp_clk_src = {
1021        .cmd_rcgr = 0x4d014,
1022        .hid_width = 5,
1023        .parent_map = gcc_xo_gpll0_dsiphy_map,
1024        .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1025        .clkr.hw.init = &(struct clk_init_data){
1026                .name = "mdp_clk_src",
1027                .parent_names = gcc_xo_gpll0_dsiphy,
1028                .num_parents = 3,
1029                .ops = &clk_rcg2_ops,
1030        },
1031};
1032
1033static struct clk_rcg2 pclk0_clk_src = {
1034        .cmd_rcgr = 0x4d000,
1035        .mnd_width = 8,
1036        .hid_width = 5,
1037        .parent_map = gcc_xo_gpll0a_dsiphy_map,
1038        .clkr.hw.init = &(struct clk_init_data){
1039                .name = "pclk0_clk_src",
1040                .parent_names = gcc_xo_gpll0a_dsiphy,
1041                .num_parents = 3,
1042                .ops = &clk_pixel_ops,
1043                .flags = CLK_SET_RATE_PARENT,
1044        },
1045};
1046
1047static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1048        F(19200000, P_XO, 1, 0, 0),
1049        { }
1050};
1051
1052static struct clk_rcg2 vsync_clk_src = {
1053        .cmd_rcgr = 0x4d02c,
1054        .hid_width = 5,
1055        .parent_map = gcc_xo_gpll0a_map,
1056        .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1057        .clkr.hw.init = &(struct clk_init_data){
1058                .name = "vsync_clk_src",
1059                .parent_names = gcc_xo_gpll0a,
1060                .num_parents = 2,
1061                .ops = &clk_rcg2_ops,
1062        },
1063};
1064
1065static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1066        F(64000000, P_GPLL0, 12.5, 0, 0),
1067        { }
1068};
1069
1070static struct clk_rcg2 pdm2_clk_src = {
1071        .cmd_rcgr = 0x44010,
1072        .hid_width = 5,
1073        .parent_map = gcc_xo_gpll0_map,
1074        .freq_tbl = ftbl_gcc_pdm2_clk,
1075        .clkr.hw.init = &(struct clk_init_data){
1076                .name = "pdm2_clk_src",
1077                .parent_names = gcc_xo_gpll0,
1078                .num_parents = 2,
1079                .ops = &clk_rcg2_ops,
1080        },
1081};
1082
1083static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1084        F(144000, P_XO, 16, 3, 25),
1085        F(400000, P_XO, 12, 1, 4),
1086        F(20000000, P_GPLL0, 10, 1, 4),
1087        F(25000000, P_GPLL0, 16, 1, 2),
1088        F(50000000, P_GPLL0, 16, 0, 0),
1089        F(100000000, P_GPLL0, 8, 0, 0),
1090        F(177770000, P_GPLL0, 4.5, 0, 0),
1091        { }
1092};
1093
1094static struct clk_rcg2 sdcc1_apps_clk_src = {
1095        .cmd_rcgr = 0x42004,
1096        .mnd_width = 8,
1097        .hid_width = 5,
1098        .parent_map = gcc_xo_gpll0_map,
1099        .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1100        .clkr.hw.init = &(struct clk_init_data){
1101                .name = "sdcc1_apps_clk_src",
1102                .parent_names = gcc_xo_gpll0,
1103                .num_parents = 2,
1104                .ops = &clk_rcg2_floor_ops,
1105        },
1106};
1107
1108static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1109        F(144000, P_XO, 16, 3, 25),
1110        F(400000, P_XO, 12, 1, 4),
1111        F(20000000, P_GPLL0, 10, 1, 4),
1112        F(25000000, P_GPLL0, 16, 1, 2),
1113        F(50000000, P_GPLL0, 16, 0, 0),
1114        F(100000000, P_GPLL0, 8, 0, 0),
1115        F(200000000, P_GPLL0, 4, 0, 0),
1116        { }
1117};
1118
1119static struct clk_rcg2 sdcc2_apps_clk_src = {
1120        .cmd_rcgr = 0x43004,
1121        .mnd_width = 8,
1122        .hid_width = 5,
1123        .parent_map = gcc_xo_gpll0_map,
1124        .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1125        .clkr.hw.init = &(struct clk_init_data){
1126                .name = "sdcc2_apps_clk_src",
1127                .parent_names = gcc_xo_gpll0,
1128                .num_parents = 2,
1129                .ops = &clk_rcg2_floor_ops,
1130        },
1131};
1132
1133static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1134        F(155000000, P_GPLL2, 6, 0, 0),
1135        F(310000000, P_GPLL2, 3, 0, 0),
1136        F(400000000, P_GPLL0, 2, 0, 0),
1137        { }
1138};
1139
1140static struct clk_rcg2 apss_tcu_clk_src = {
1141        .cmd_rcgr = 0x1207c,
1142        .hid_width = 5,
1143        .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1144        .freq_tbl = ftbl_gcc_apss_tcu_clk,
1145        .clkr.hw.init = &(struct clk_init_data){
1146                .name = "apss_tcu_clk_src",
1147                .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1148                .num_parents = 4,
1149                .ops = &clk_rcg2_ops,
1150        },
1151};
1152
1153static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1154        F(19200000, P_XO, 1, 0, 0),
1155        F(100000000, P_GPLL0, 8, 0, 0),
1156        F(200000000, P_GPLL0, 4, 0, 0),
1157        F(266500000, P_BIMC, 4, 0, 0),
1158        F(400000000, P_GPLL0, 2, 0, 0),
1159        F(533000000, P_BIMC, 2, 0, 0),
1160        { }
1161};
1162
1163static struct clk_rcg2 bimc_gpu_clk_src = {
1164        .cmd_rcgr = 0x31028,
1165        .hid_width = 5,
1166        .parent_map = gcc_xo_gpll0_bimc_map,
1167        .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1168        .clkr.hw.init = &(struct clk_init_data){
1169                .name = "bimc_gpu_clk_src",
1170                .parent_names = gcc_xo_gpll0_bimc,
1171                .num_parents = 3,
1172                .flags = CLK_GET_RATE_NOCACHE,
1173                .ops = &clk_rcg2_ops,
1174        },
1175};
1176
1177static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1178        F(80000000, P_GPLL0, 10, 0, 0),
1179        { }
1180};
1181
1182static struct clk_rcg2 usb_hs_system_clk_src = {
1183        .cmd_rcgr = 0x41010,
1184        .hid_width = 5,
1185        .parent_map = gcc_xo_gpll0_map,
1186        .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1187        .clkr.hw.init = &(struct clk_init_data){
1188                .name = "usb_hs_system_clk_src",
1189                .parent_names = gcc_xo_gpll0,
1190                .num_parents = 2,
1191                .ops = &clk_rcg2_ops,
1192        },
1193};
1194
1195static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1196        F(3200000, P_XO, 6, 0, 0),
1197        F(6400000, P_XO, 3, 0, 0),
1198        F(9600000, P_XO, 2, 0, 0),
1199        F(19200000, P_XO, 1, 0, 0),
1200        F(40000000, P_GPLL0, 10, 1, 2),
1201        F(66670000, P_GPLL0, 12, 0, 0),
1202        F(80000000, P_GPLL0, 10, 0, 0),
1203        F(100000000, P_GPLL0, 8, 0, 0),
1204        { }
1205};
1206
1207static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1208        .cmd_rcgr = 0x1c010,
1209        .hid_width = 5,
1210        .mnd_width = 8,
1211        .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1212        .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1213        .clkr.hw.init = &(struct clk_init_data){
1214                .name = "ultaudio_ahbfabric_clk_src",
1215                .parent_names = gcc_xo_gpll0_gpll1_sleep,
1216                .num_parents = 4,
1217                .ops = &clk_rcg2_ops,
1218        },
1219};
1220
1221static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1222        .halt_reg = 0x1c028,
1223        .clkr = {
1224                .enable_reg = 0x1c028,
1225                .enable_mask = BIT(0),
1226                .hw.init = &(struct clk_init_data){
1227                        .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1228                        .parent_names = (const char *[]){
1229                                "ultaudio_ahbfabric_clk_src",
1230                        },
1231                        .num_parents = 1,
1232                        .flags = CLK_SET_RATE_PARENT,
1233                        .ops = &clk_branch2_ops,
1234                },
1235        },
1236};
1237
1238static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1239        .halt_reg = 0x1c024,
1240        .clkr = {
1241                .enable_reg = 0x1c024,
1242                .enable_mask = BIT(0),
1243                .hw.init = &(struct clk_init_data){
1244                        .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1245                        .parent_names = (const char *[]){
1246                                "ultaudio_ahbfabric_clk_src",
1247                        },
1248                        .num_parents = 1,
1249                        .flags = CLK_SET_RATE_PARENT,
1250                        .ops = &clk_branch2_ops,
1251                },
1252        },
1253};
1254
1255static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1256        F(128000, P_XO, 10, 1, 15),
1257        F(256000, P_XO, 5, 1, 15),
1258        F(384000, P_XO, 5, 1, 10),
1259        F(512000, P_XO, 5, 2, 15),
1260        F(576000, P_XO, 5, 3, 20),
1261        F(705600, P_GPLL1, 16, 1, 80),
1262        F(768000, P_XO, 5, 1, 5),
1263        F(800000, P_XO, 5, 5, 24),
1264        F(1024000, P_XO, 5, 4, 15),
1265        F(1152000, P_XO, 1, 3, 50),
1266        F(1411200, P_GPLL1, 16, 1, 40),
1267        F(1536000, P_XO, 1, 2, 25),
1268        F(1600000, P_XO, 12, 0, 0),
1269        F(1728000, P_XO, 5, 9, 20),
1270        F(2048000, P_XO, 5, 8, 15),
1271        F(2304000, P_XO, 5, 3, 5),
1272        F(2400000, P_XO, 8, 0, 0),
1273        F(2822400, P_GPLL1, 16, 1, 20),
1274        F(3072000, P_XO, 5, 4, 5),
1275        F(4096000, P_GPLL1, 9, 2, 49),
1276        F(4800000, P_XO, 4, 0, 0),
1277        F(5644800, P_GPLL1, 16, 1, 10),
1278        F(6144000, P_GPLL1, 7, 1, 21),
1279        F(8192000, P_GPLL1, 9, 4, 49),
1280        F(9600000, P_XO, 2, 0, 0),
1281        F(11289600, P_GPLL1, 16, 1, 5),
1282        F(12288000, P_GPLL1, 7, 2, 21),
1283        { }
1284};
1285
1286static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1287        .cmd_rcgr = 0x1c054,
1288        .hid_width = 5,
1289        .mnd_width = 8,
1290        .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1291        .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1292        .clkr.hw.init = &(struct clk_init_data){
1293                .name = "ultaudio_lpaif_pri_i2s_clk_src",
1294                .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
1295                .num_parents = 5,
1296                .ops = &clk_rcg2_ops,
1297        },
1298};
1299
1300static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1301        .halt_reg = 0x1c068,
1302        .clkr = {
1303                .enable_reg = 0x1c068,
1304                .enable_mask = BIT(0),
1305                .hw.init = &(struct clk_init_data){
1306                        .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1307                        .parent_names = (const char *[]){
1308                                "ultaudio_lpaif_pri_i2s_clk_src",
1309                        },
1310                        .num_parents = 1,
1311                        .flags = CLK_SET_RATE_PARENT,
1312                        .ops = &clk_branch2_ops,
1313                },
1314        },
1315};
1316
1317static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1318        .cmd_rcgr = 0x1c06c,
1319        .hid_width = 5,
1320        .mnd_width = 8,
1321        .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1322        .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1323        .clkr.hw.init = &(struct clk_init_data){
1324                .name = "ultaudio_lpaif_sec_i2s_clk_src",
1325                .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1326                .num_parents = 5,
1327                .ops = &clk_rcg2_ops,
1328        },
1329};
1330
1331static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1332        .halt_reg = 0x1c080,
1333        .clkr = {
1334                .enable_reg = 0x1c080,
1335                .enable_mask = BIT(0),
1336                .hw.init = &(struct clk_init_data){
1337                        .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1338                        .parent_names = (const char *[]){
1339                                "ultaudio_lpaif_sec_i2s_clk_src",
1340                        },
1341                        .num_parents = 1,
1342                        .flags = CLK_SET_RATE_PARENT,
1343                        .ops = &clk_branch2_ops,
1344                },
1345        },
1346};
1347
1348static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1349        .cmd_rcgr = 0x1c084,
1350        .hid_width = 5,
1351        .mnd_width = 8,
1352        .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1353        .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1354        .clkr.hw.init = &(struct clk_init_data){
1355                .name = "ultaudio_lpaif_aux_i2s_clk_src",
1356                .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1357                .num_parents = 5,
1358                .ops = &clk_rcg2_ops,
1359        },
1360};
1361
1362static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1363        .halt_reg = 0x1c098,
1364        .clkr = {
1365                .enable_reg = 0x1c098,
1366                .enable_mask = BIT(0),
1367                .hw.init = &(struct clk_init_data){
1368                        .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1369                        .parent_names = (const char *[]){
1370                                "ultaudio_lpaif_aux_i2s_clk_src",
1371                        },
1372                        .num_parents = 1,
1373                        .flags = CLK_SET_RATE_PARENT,
1374                        .ops = &clk_branch2_ops,
1375                },
1376        },
1377};
1378
1379static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1380        F(19200000, P_XO, 1, 0, 0),
1381        { }
1382};
1383
1384static struct clk_rcg2 ultaudio_xo_clk_src = {
1385        .cmd_rcgr = 0x1c034,
1386        .hid_width = 5,
1387        .parent_map = gcc_xo_sleep_map,
1388        .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1389        .clkr.hw.init = &(struct clk_init_data){
1390                .name = "ultaudio_xo_clk_src",
1391                .parent_names = gcc_xo_sleep,
1392                .num_parents = 2,
1393                .ops = &clk_rcg2_ops,
1394        },
1395};
1396
1397static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1398        .halt_reg = 0x1c04c,
1399        .clkr = {
1400                .enable_reg = 0x1c04c,
1401                .enable_mask = BIT(0),
1402                .hw.init = &(struct clk_init_data){
1403                        .name = "gcc_ultaudio_avsync_xo_clk",
1404                        .parent_names = (const char *[]){
1405                                "ultaudio_xo_clk_src",
1406                        },
1407                        .num_parents = 1,
1408                        .flags = CLK_SET_RATE_PARENT,
1409                        .ops = &clk_branch2_ops,
1410                },
1411        },
1412};
1413
1414static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1415        .halt_reg = 0x1c050,
1416        .clkr = {
1417                .enable_reg = 0x1c050,
1418                .enable_mask = BIT(0),
1419                .hw.init = &(struct clk_init_data){
1420                        .name = "gcc_ultaudio_stc_xo_clk",
1421                        .parent_names = (const char *[]){
1422                                "ultaudio_xo_clk_src",
1423                        },
1424                        .num_parents = 1,
1425                        .flags = CLK_SET_RATE_PARENT,
1426                        .ops = &clk_branch2_ops,
1427                },
1428        },
1429};
1430
1431static const struct freq_tbl ftbl_codec_clk[] = {
1432        F(9600000, P_XO, 2, 0, 0),
1433        F(12288000, P_XO, 1, 16, 25),
1434        F(19200000, P_XO, 1, 0, 0),
1435        F(11289600, P_EXT_MCLK, 1, 0, 0),
1436        { }
1437};
1438
1439static struct clk_rcg2 codec_digcodec_clk_src = {
1440        .cmd_rcgr = 0x1c09c,
1441        .mnd_width = 8,
1442        .hid_width = 5,
1443        .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1444        .freq_tbl = ftbl_codec_clk,
1445        .clkr.hw.init = &(struct clk_init_data){
1446                .name = "codec_digcodec_clk_src",
1447                .parent_names = gcc_xo_gpll1_emclk_sleep,
1448                .num_parents = 4,
1449                .ops = &clk_rcg2_ops,
1450        },
1451};
1452
1453static struct clk_branch gcc_codec_digcodec_clk = {
1454        .halt_reg = 0x1c0b0,
1455        .clkr = {
1456                .enable_reg = 0x1c0b0,
1457                .enable_mask = BIT(0),
1458                .hw.init = &(struct clk_init_data){
1459                        .name = "gcc_ultaudio_codec_digcodec_clk",
1460                        .parent_names = (const char *[]){
1461                                "codec_digcodec_clk_src",
1462                        },
1463                        .num_parents = 1,
1464                        .flags = CLK_SET_RATE_PARENT,
1465                        .ops = &clk_branch2_ops,
1466                },
1467        },
1468};
1469
1470static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1471        .halt_reg = 0x1c000,
1472        .clkr = {
1473                .enable_reg = 0x1c000,
1474                .enable_mask = BIT(0),
1475                .hw.init = &(struct clk_init_data){
1476                        .name = "gcc_ultaudio_pcnoc_mport_clk",
1477                        .parent_names = (const char *[]){
1478                                "pcnoc_bfdcd_clk_src",
1479                        },
1480                        .num_parents = 1,
1481                        .ops = &clk_branch2_ops,
1482                },
1483        },
1484};
1485
1486static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1487        .halt_reg = 0x1c004,
1488        .clkr = {
1489                .enable_reg = 0x1c004,
1490                .enable_mask = BIT(0),
1491                .hw.init = &(struct clk_init_data){
1492                        .name = "gcc_ultaudio_pcnoc_sway_clk",
1493                        .parent_names = (const char *[]){
1494                                "pcnoc_bfdcd_clk_src",
1495                        },
1496                        .num_parents = 1,
1497                        .ops = &clk_branch2_ops,
1498                },
1499        },
1500};
1501
1502static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1503        F(100000000, P_GPLL0, 8, 0, 0),
1504        F(160000000, P_GPLL0, 5, 0, 0),
1505        F(228570000, P_GPLL0, 3.5, 0, 0),
1506        { }
1507};
1508
1509static struct clk_rcg2 vcodec0_clk_src = {
1510        .cmd_rcgr = 0x4C000,
1511        .mnd_width = 8,
1512        .hid_width = 5,
1513        .parent_map = gcc_xo_gpll0_map,
1514        .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1515        .clkr.hw.init = &(struct clk_init_data){
1516                .name = "vcodec0_clk_src",
1517                .parent_names = gcc_xo_gpll0,
1518                .num_parents = 2,
1519                .ops = &clk_rcg2_ops,
1520        },
1521};
1522
1523static struct clk_branch gcc_blsp1_ahb_clk = {
1524        .halt_reg = 0x01008,
1525        .halt_check = BRANCH_HALT_VOTED,
1526        .clkr = {
1527                .enable_reg = 0x45004,
1528                .enable_mask = BIT(10),
1529                .hw.init = &(struct clk_init_data){
1530                        .name = "gcc_blsp1_ahb_clk",
1531                        .parent_names = (const char *[]){
1532                                "pcnoc_bfdcd_clk_src",
1533                        },
1534                        .num_parents = 1,
1535                        .ops = &clk_branch2_ops,
1536                },
1537        },
1538};
1539
1540static struct clk_branch gcc_blsp1_sleep_clk = {
1541        .halt_reg = 0x01004,
1542        .clkr = {
1543                .enable_reg = 0x01004,
1544                .enable_mask = BIT(0),
1545                .hw.init = &(struct clk_init_data){
1546                        .name = "gcc_blsp1_sleep_clk",
1547                        .parent_names = (const char *[]){
1548                                "sleep_clk_src",
1549                        },
1550                        .num_parents = 1,
1551                        .flags = CLK_SET_RATE_PARENT,
1552                        .ops = &clk_branch2_ops,
1553                },
1554        },
1555};
1556
1557static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1558        .halt_reg = 0x02008,
1559        .clkr = {
1560                .enable_reg = 0x02008,
1561                .enable_mask = BIT(0),
1562                .hw.init = &(struct clk_init_data){
1563                        .name = "gcc_blsp1_qup1_i2c_apps_clk",
1564                        .parent_names = (const char *[]){
1565                                "blsp1_qup1_i2c_apps_clk_src",
1566                        },
1567                        .num_parents = 1,
1568                        .flags = CLK_SET_RATE_PARENT,
1569                        .ops = &clk_branch2_ops,
1570                },
1571        },
1572};
1573
1574static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1575        .halt_reg = 0x02004,
1576        .clkr = {
1577                .enable_reg = 0x02004,
1578                .enable_mask = BIT(0),
1579                .hw.init = &(struct clk_init_data){
1580                        .name = "gcc_blsp1_qup1_spi_apps_clk",
1581                        .parent_names = (const char *[]){
1582                                "blsp1_qup1_spi_apps_clk_src",
1583                        },
1584                        .num_parents = 1,
1585                        .flags = CLK_SET_RATE_PARENT,
1586                        .ops = &clk_branch2_ops,
1587                },
1588        },
1589};
1590
1591static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1592        .halt_reg = 0x03010,
1593        .clkr = {
1594                .enable_reg = 0x03010,
1595                .enable_mask = BIT(0),
1596                .hw.init = &(struct clk_init_data){
1597                        .name = "gcc_blsp1_qup2_i2c_apps_clk",
1598                        .parent_names = (const char *[]){
1599                                "blsp1_qup2_i2c_apps_clk_src",
1600                        },
1601                        .num_parents = 1,
1602                        .flags = CLK_SET_RATE_PARENT,
1603                        .ops = &clk_branch2_ops,
1604                },
1605        },
1606};
1607
1608static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1609        .halt_reg = 0x0300c,
1610        .clkr = {
1611                .enable_reg = 0x0300c,
1612                .enable_mask = BIT(0),
1613                .hw.init = &(struct clk_init_data){
1614                        .name = "gcc_blsp1_qup2_spi_apps_clk",
1615                        .parent_names = (const char *[]){
1616                                "blsp1_qup2_spi_apps_clk_src",
1617                        },
1618                        .num_parents = 1,
1619                        .flags = CLK_SET_RATE_PARENT,
1620                        .ops = &clk_branch2_ops,
1621                },
1622        },
1623};
1624
1625static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1626        .halt_reg = 0x04020,
1627        .clkr = {
1628                .enable_reg = 0x04020,
1629                .enable_mask = BIT(0),
1630                .hw.init = &(struct clk_init_data){
1631                        .name = "gcc_blsp1_qup3_i2c_apps_clk",
1632                        .parent_names = (const char *[]){
1633                                "blsp1_qup3_i2c_apps_clk_src",
1634                        },
1635                        .num_parents = 1,
1636                        .flags = CLK_SET_RATE_PARENT,
1637                        .ops = &clk_branch2_ops,
1638                },
1639        },
1640};
1641
1642static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1643        .halt_reg = 0x0401c,
1644        .clkr = {
1645                .enable_reg = 0x0401c,
1646                .enable_mask = BIT(0),
1647                .hw.init = &(struct clk_init_data){
1648                        .name = "gcc_blsp1_qup3_spi_apps_clk",
1649                        .parent_names = (const char *[]){
1650                                "blsp1_qup3_spi_apps_clk_src",
1651                        },
1652                        .num_parents = 1,
1653                        .flags = CLK_SET_RATE_PARENT,
1654                        .ops = &clk_branch2_ops,
1655                },
1656        },
1657};
1658
1659static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1660        .halt_reg = 0x05020,
1661        .clkr = {
1662                .enable_reg = 0x05020,
1663                .enable_mask = BIT(0),
1664                .hw.init = &(struct clk_init_data){
1665                        .name = "gcc_blsp1_qup4_i2c_apps_clk",
1666                        .parent_names = (const char *[]){
1667                                "blsp1_qup4_i2c_apps_clk_src",
1668                        },
1669                        .num_parents = 1,
1670                        .flags = CLK_SET_RATE_PARENT,
1671                        .ops = &clk_branch2_ops,
1672                },
1673        },
1674};
1675
1676static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1677        .halt_reg = 0x0501c,
1678        .clkr = {
1679                .enable_reg = 0x0501c,
1680                .enable_mask = BIT(0),
1681                .hw.init = &(struct clk_init_data){
1682                        .name = "gcc_blsp1_qup4_spi_apps_clk",
1683                        .parent_names = (const char *[]){
1684                                "blsp1_qup4_spi_apps_clk_src",
1685                        },
1686                        .num_parents = 1,
1687                        .flags = CLK_SET_RATE_PARENT,
1688                        .ops = &clk_branch2_ops,
1689                },
1690        },
1691};
1692
1693static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1694        .halt_reg = 0x06020,
1695        .clkr = {
1696                .enable_reg = 0x06020,
1697                .enable_mask = BIT(0),
1698                .hw.init = &(struct clk_init_data){
1699                        .name = "gcc_blsp1_qup5_i2c_apps_clk",
1700                        .parent_names = (const char *[]){
1701                                "blsp1_qup5_i2c_apps_clk_src",
1702                        },
1703                        .num_parents = 1,
1704                        .flags = CLK_SET_RATE_PARENT,
1705                        .ops = &clk_branch2_ops,
1706                },
1707        },
1708};
1709
1710static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1711        .halt_reg = 0x0601c,
1712        .clkr = {
1713                .enable_reg = 0x0601c,
1714                .enable_mask = BIT(0),
1715                .hw.init = &(struct clk_init_data){
1716                        .name = "gcc_blsp1_qup5_spi_apps_clk",
1717                        .parent_names = (const char *[]){
1718                                "blsp1_qup5_spi_apps_clk_src",
1719                        },
1720                        .num_parents = 1,
1721                        .flags = CLK_SET_RATE_PARENT,
1722                        .ops = &clk_branch2_ops,
1723                },
1724        },
1725};
1726
1727static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1728        .halt_reg = 0x07020,
1729        .clkr = {
1730                .enable_reg = 0x07020,
1731                .enable_mask = BIT(0),
1732                .hw.init = &(struct clk_init_data){
1733                        .name = "gcc_blsp1_qup6_i2c_apps_clk",
1734                        .parent_names = (const char *[]){
1735                                "blsp1_qup6_i2c_apps_clk_src",
1736                        },
1737                        .num_parents = 1,
1738                        .flags = CLK_SET_RATE_PARENT,
1739                        .ops = &clk_branch2_ops,
1740                },
1741        },
1742};
1743
1744static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1745        .halt_reg = 0x0701c,
1746        .clkr = {
1747                .enable_reg = 0x0701c,
1748                .enable_mask = BIT(0),
1749                .hw.init = &(struct clk_init_data){
1750                        .name = "gcc_blsp1_qup6_spi_apps_clk",
1751                        .parent_names = (const char *[]){
1752                                "blsp1_qup6_spi_apps_clk_src",
1753                        },
1754                        .num_parents = 1,
1755                        .flags = CLK_SET_RATE_PARENT,
1756                        .ops = &clk_branch2_ops,
1757                },
1758        },
1759};
1760
1761static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1762        .halt_reg = 0x0203c,
1763        .clkr = {
1764                .enable_reg = 0x0203c,
1765                .enable_mask = BIT(0),
1766                .hw.init = &(struct clk_init_data){
1767                        .name = "gcc_blsp1_uart1_apps_clk",
1768                        .parent_names = (const char *[]){
1769                                "blsp1_uart1_apps_clk_src",
1770                        },
1771                        .num_parents = 1,
1772                        .flags = CLK_SET_RATE_PARENT,
1773                        .ops = &clk_branch2_ops,
1774                },
1775        },
1776};
1777
1778static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1779        .halt_reg = 0x0302c,
1780        .clkr = {
1781                .enable_reg = 0x0302c,
1782                .enable_mask = BIT(0),
1783                .hw.init = &(struct clk_init_data){
1784                        .name = "gcc_blsp1_uart2_apps_clk",
1785                        .parent_names = (const char *[]){
1786                                "blsp1_uart2_apps_clk_src",
1787                        },
1788                        .num_parents = 1,
1789                        .flags = CLK_SET_RATE_PARENT,
1790                        .ops = &clk_branch2_ops,
1791                },
1792        },
1793};
1794
1795static struct clk_branch gcc_boot_rom_ahb_clk = {
1796        .halt_reg = 0x1300c,
1797        .halt_check = BRANCH_HALT_VOTED,
1798        .clkr = {
1799                .enable_reg = 0x45004,
1800                .enable_mask = BIT(7),
1801                .hw.init = &(struct clk_init_data){
1802                        .name = "gcc_boot_rom_ahb_clk",
1803                        .parent_names = (const char *[]){
1804                                "pcnoc_bfdcd_clk_src",
1805                        },
1806                        .num_parents = 1,
1807                        .ops = &clk_branch2_ops,
1808                },
1809        },
1810};
1811
1812static struct clk_branch gcc_camss_cci_ahb_clk = {
1813        .halt_reg = 0x5101c,
1814        .clkr = {
1815                .enable_reg = 0x5101c,
1816                .enable_mask = BIT(0),
1817                .hw.init = &(struct clk_init_data){
1818                        .name = "gcc_camss_cci_ahb_clk",
1819                        .parent_names = (const char *[]){
1820                                "camss_ahb_clk_src",
1821                        },
1822                        .num_parents = 1,
1823                        .flags = CLK_SET_RATE_PARENT,
1824                        .ops = &clk_branch2_ops,
1825                },
1826        },
1827};
1828
1829static struct clk_branch gcc_camss_cci_clk = {
1830        .halt_reg = 0x51018,
1831        .clkr = {
1832                .enable_reg = 0x51018,
1833                .enable_mask = BIT(0),
1834                .hw.init = &(struct clk_init_data){
1835                        .name = "gcc_camss_cci_clk",
1836                        .parent_names = (const char *[]){
1837                                "cci_clk_src",
1838                        },
1839                        .num_parents = 1,
1840                        .flags = CLK_SET_RATE_PARENT,
1841                        .ops = &clk_branch2_ops,
1842                },
1843        },
1844};
1845
1846static struct clk_branch gcc_camss_csi0_ahb_clk = {
1847        .halt_reg = 0x4e040,
1848        .clkr = {
1849                .enable_reg = 0x4e040,
1850                .enable_mask = BIT(0),
1851                .hw.init = &(struct clk_init_data){
1852                        .name = "gcc_camss_csi0_ahb_clk",
1853                        .parent_names = (const char *[]){
1854                                "camss_ahb_clk_src",
1855                        },
1856                        .num_parents = 1,
1857                        .flags = CLK_SET_RATE_PARENT,
1858                        .ops = &clk_branch2_ops,
1859                },
1860        },
1861};
1862
1863static struct clk_branch gcc_camss_csi0_clk = {
1864        .halt_reg = 0x4e03c,
1865        .clkr = {
1866                .enable_reg = 0x4e03c,
1867                .enable_mask = BIT(0),
1868                .hw.init = &(struct clk_init_data){
1869                        .name = "gcc_camss_csi0_clk",
1870                        .parent_names = (const char *[]){
1871                                "csi0_clk_src",
1872                        },
1873                        .num_parents = 1,
1874                        .flags = CLK_SET_RATE_PARENT,
1875                        .ops = &clk_branch2_ops,
1876                },
1877        },
1878};
1879
1880static struct clk_branch gcc_camss_csi0phy_clk = {
1881        .halt_reg = 0x4e048,
1882        .clkr = {
1883                .enable_reg = 0x4e048,
1884                .enable_mask = BIT(0),
1885                .hw.init = &(struct clk_init_data){
1886                        .name = "gcc_camss_csi0phy_clk",
1887                        .parent_names = (const char *[]){
1888                                "csi0_clk_src",
1889                        },
1890                        .num_parents = 1,
1891                        .flags = CLK_SET_RATE_PARENT,
1892                        .ops = &clk_branch2_ops,
1893                },
1894        },
1895};
1896
1897static struct clk_branch gcc_camss_csi0pix_clk = {
1898        .halt_reg = 0x4e058,
1899        .clkr = {
1900                .enable_reg = 0x4e058,
1901                .enable_mask = BIT(0),
1902                .hw.init = &(struct clk_init_data){
1903                        .name = "gcc_camss_csi0pix_clk",
1904                        .parent_names = (const char *[]){
1905                                "csi0_clk_src",
1906                        },
1907                        .num_parents = 1,
1908                        .flags = CLK_SET_RATE_PARENT,
1909                        .ops = &clk_branch2_ops,
1910                },
1911        },
1912};
1913
1914static struct clk_branch gcc_camss_csi0rdi_clk = {
1915        .halt_reg = 0x4e050,
1916        .clkr = {
1917                .enable_reg = 0x4e050,
1918                .enable_mask = BIT(0),
1919                .hw.init = &(struct clk_init_data){
1920                        .name = "gcc_camss_csi0rdi_clk",
1921                        .parent_names = (const char *[]){
1922                                "csi0_clk_src",
1923                        },
1924                        .num_parents = 1,
1925                        .flags = CLK_SET_RATE_PARENT,
1926                        .ops = &clk_branch2_ops,
1927                },
1928        },
1929};
1930
1931static struct clk_branch gcc_camss_csi1_ahb_clk = {
1932        .halt_reg = 0x4f040,
1933        .clkr = {
1934                .enable_reg = 0x4f040,
1935                .enable_mask = BIT(0),
1936                .hw.init = &(struct clk_init_data){
1937                        .name = "gcc_camss_csi1_ahb_clk",
1938                        .parent_names = (const char *[]){
1939                                "camss_ahb_clk_src",
1940                        },
1941                        .num_parents = 1,
1942                        .flags = CLK_SET_RATE_PARENT,
1943                        .ops = &clk_branch2_ops,
1944                },
1945        },
1946};
1947
1948static struct clk_branch gcc_camss_csi1_clk = {
1949        .halt_reg = 0x4f03c,
1950        .clkr = {
1951                .enable_reg = 0x4f03c,
1952                .enable_mask = BIT(0),
1953                .hw.init = &(struct clk_init_data){
1954                        .name = "gcc_camss_csi1_clk",
1955                        .parent_names = (const char *[]){
1956                                "csi1_clk_src",
1957                        },
1958                        .num_parents = 1,
1959                        .flags = CLK_SET_RATE_PARENT,
1960                        .ops = &clk_branch2_ops,
1961                },
1962        },
1963};
1964
1965static struct clk_branch gcc_camss_csi1phy_clk = {
1966        .halt_reg = 0x4f048,
1967        .clkr = {
1968                .enable_reg = 0x4f048,
1969                .enable_mask = BIT(0),
1970                .hw.init = &(struct clk_init_data){
1971                        .name = "gcc_camss_csi1phy_clk",
1972                        .parent_names = (const char *[]){
1973                                "csi1_clk_src",
1974                        },
1975                        .num_parents = 1,
1976                        .flags = CLK_SET_RATE_PARENT,
1977                        .ops = &clk_branch2_ops,
1978                },
1979        },
1980};
1981
1982static struct clk_branch gcc_camss_csi1pix_clk = {
1983        .halt_reg = 0x4f058,
1984        .clkr = {
1985                .enable_reg = 0x4f058,
1986                .enable_mask = BIT(0),
1987                .hw.init = &(struct clk_init_data){
1988                        .name = "gcc_camss_csi1pix_clk",
1989                        .parent_names = (const char *[]){
1990                                "csi1_clk_src",
1991                        },
1992                        .num_parents = 1,
1993                        .flags = CLK_SET_RATE_PARENT,
1994                        .ops = &clk_branch2_ops,
1995                },
1996        },
1997};
1998
1999static struct clk_branch gcc_camss_csi1rdi_clk = {
2000        .halt_reg = 0x4f050,
2001        .clkr = {
2002                .enable_reg = 0x4f050,
2003                .enable_mask = BIT(0),
2004                .hw.init = &(struct clk_init_data){
2005                        .name = "gcc_camss_csi1rdi_clk",
2006                        .parent_names = (const char *[]){
2007                                "csi1_clk_src",
2008                        },
2009                        .num_parents = 1,
2010                        .flags = CLK_SET_RATE_PARENT,
2011                        .ops = &clk_branch2_ops,
2012                },
2013        },
2014};
2015
2016static struct clk_branch gcc_camss_csi_vfe0_clk = {
2017        .halt_reg = 0x58050,
2018        .clkr = {
2019                .enable_reg = 0x58050,
2020                .enable_mask = BIT(0),
2021                .hw.init = &(struct clk_init_data){
2022                        .name = "gcc_camss_csi_vfe0_clk",
2023                        .parent_names = (const char *[]){
2024                                "vfe0_clk_src",
2025                        },
2026                        .num_parents = 1,
2027                        .flags = CLK_SET_RATE_PARENT,
2028                        .ops = &clk_branch2_ops,
2029                },
2030        },
2031};
2032
2033static struct clk_branch gcc_camss_gp0_clk = {
2034        .halt_reg = 0x54018,
2035        .clkr = {
2036                .enable_reg = 0x54018,
2037                .enable_mask = BIT(0),
2038                .hw.init = &(struct clk_init_data){
2039                        .name = "gcc_camss_gp0_clk",
2040                        .parent_names = (const char *[]){
2041                                "camss_gp0_clk_src",
2042                        },
2043                        .num_parents = 1,
2044                        .flags = CLK_SET_RATE_PARENT,
2045                        .ops = &clk_branch2_ops,
2046                },
2047        },
2048};
2049
2050static struct clk_branch gcc_camss_gp1_clk = {
2051        .halt_reg = 0x55018,
2052        .clkr = {
2053                .enable_reg = 0x55018,
2054                .enable_mask = BIT(0),
2055                .hw.init = &(struct clk_init_data){
2056                        .name = "gcc_camss_gp1_clk",
2057                        .parent_names = (const char *[]){
2058                                "camss_gp1_clk_src",
2059                        },
2060                        .num_parents = 1,
2061                        .flags = CLK_SET_RATE_PARENT,
2062                        .ops = &clk_branch2_ops,
2063                },
2064        },
2065};
2066
2067static struct clk_branch gcc_camss_ispif_ahb_clk = {
2068        .halt_reg = 0x50004,
2069        .clkr = {
2070                .enable_reg = 0x50004,
2071                .enable_mask = BIT(0),
2072                .hw.init = &(struct clk_init_data){
2073                        .name = "gcc_camss_ispif_ahb_clk",
2074                        .parent_names = (const char *[]){
2075                                "camss_ahb_clk_src",
2076                        },
2077                        .num_parents = 1,
2078                        .flags = CLK_SET_RATE_PARENT,
2079                        .ops = &clk_branch2_ops,
2080                },
2081        },
2082};
2083
2084static struct clk_branch gcc_camss_jpeg0_clk = {
2085        .halt_reg = 0x57020,
2086        .clkr = {
2087                .enable_reg = 0x57020,
2088                .enable_mask = BIT(0),
2089                .hw.init = &(struct clk_init_data){
2090                        .name = "gcc_camss_jpeg0_clk",
2091                        .parent_names = (const char *[]){
2092                                "jpeg0_clk_src",
2093                        },
2094                        .num_parents = 1,
2095                        .flags = CLK_SET_RATE_PARENT,
2096                        .ops = &clk_branch2_ops,
2097                },
2098        },
2099};
2100
2101static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2102        .halt_reg = 0x57024,
2103        .clkr = {
2104                .enable_reg = 0x57024,
2105                .enable_mask = BIT(0),
2106                .hw.init = &(struct clk_init_data){
2107                        .name = "gcc_camss_jpeg_ahb_clk",
2108                        .parent_names = (const char *[]){
2109                                "camss_ahb_clk_src",
2110                        },
2111                        .num_parents = 1,
2112                        .flags = CLK_SET_RATE_PARENT,
2113                        .ops = &clk_branch2_ops,
2114                },
2115        },
2116};
2117
2118static struct clk_branch gcc_camss_jpeg_axi_clk = {
2119        .halt_reg = 0x57028,
2120        .clkr = {
2121                .enable_reg = 0x57028,
2122                .enable_mask = BIT(0),
2123                .hw.init = &(struct clk_init_data){
2124                        .name = "gcc_camss_jpeg_axi_clk",
2125                        .parent_names = (const char *[]){
2126                                "system_noc_bfdcd_clk_src",
2127                        },
2128                        .num_parents = 1,
2129                        .flags = CLK_SET_RATE_PARENT,
2130                        .ops = &clk_branch2_ops,
2131                },
2132        },
2133};
2134
2135static struct clk_branch gcc_camss_mclk0_clk = {
2136        .halt_reg = 0x52018,
2137        .clkr = {
2138                .enable_reg = 0x52018,
2139                .enable_mask = BIT(0),
2140                .hw.init = &(struct clk_init_data){
2141                        .name = "gcc_camss_mclk0_clk",
2142                        .parent_names = (const char *[]){
2143                                "mclk0_clk_src",
2144                        },
2145                        .num_parents = 1,
2146                        .flags = CLK_SET_RATE_PARENT,
2147                        .ops = &clk_branch2_ops,
2148                },
2149        },
2150};
2151
2152static struct clk_branch gcc_camss_mclk1_clk = {
2153        .halt_reg = 0x53018,
2154        .clkr = {
2155                .enable_reg = 0x53018,
2156                .enable_mask = BIT(0),
2157                .hw.init = &(struct clk_init_data){
2158                        .name = "gcc_camss_mclk1_clk",
2159                        .parent_names = (const char *[]){
2160                                "mclk1_clk_src",
2161                        },
2162                        .num_parents = 1,
2163                        .flags = CLK_SET_RATE_PARENT,
2164                        .ops = &clk_branch2_ops,
2165                },
2166        },
2167};
2168
2169static struct clk_branch gcc_camss_micro_ahb_clk = {
2170        .halt_reg = 0x5600c,
2171        .clkr = {
2172                .enable_reg = 0x5600c,
2173                .enable_mask = BIT(0),
2174                .hw.init = &(struct clk_init_data){
2175                        .name = "gcc_camss_micro_ahb_clk",
2176                        .parent_names = (const char *[]){
2177                                "camss_ahb_clk_src",
2178                        },
2179                        .num_parents = 1,
2180                        .flags = CLK_SET_RATE_PARENT,
2181                        .ops = &clk_branch2_ops,
2182                },
2183        },
2184};
2185
2186static struct clk_branch gcc_camss_csi0phytimer_clk = {
2187        .halt_reg = 0x4e01c,
2188        .clkr = {
2189                .enable_reg = 0x4e01c,
2190                .enable_mask = BIT(0),
2191                .hw.init = &(struct clk_init_data){
2192                        .name = "gcc_camss_csi0phytimer_clk",
2193                        .parent_names = (const char *[]){
2194                                "csi0phytimer_clk_src",
2195                        },
2196                        .num_parents = 1,
2197                        .flags = CLK_SET_RATE_PARENT,
2198                        .ops = &clk_branch2_ops,
2199                },
2200        },
2201};
2202
2203static struct clk_branch gcc_camss_csi1phytimer_clk = {
2204        .halt_reg = 0x4f01c,
2205        .clkr = {
2206                .enable_reg = 0x4f01c,
2207                .enable_mask = BIT(0),
2208                .hw.init = &(struct clk_init_data){
2209                        .name = "gcc_camss_csi1phytimer_clk",
2210                        .parent_names = (const char *[]){
2211                                "csi1phytimer_clk_src",
2212                        },
2213                        .num_parents = 1,
2214                        .flags = CLK_SET_RATE_PARENT,
2215                        .ops = &clk_branch2_ops,
2216                },
2217        },
2218};
2219
2220static struct clk_branch gcc_camss_ahb_clk = {
2221        .halt_reg = 0x5a014,
2222        .clkr = {
2223                .enable_reg = 0x5a014,
2224                .enable_mask = BIT(0),
2225                .hw.init = &(struct clk_init_data){
2226                        .name = "gcc_camss_ahb_clk",
2227                        .parent_names = (const char *[]){
2228                                "camss_ahb_clk_src",
2229                        },
2230                        .num_parents = 1,
2231                        .flags = CLK_SET_RATE_PARENT,
2232                        .ops = &clk_branch2_ops,
2233                },
2234        },
2235};
2236
2237static struct clk_branch gcc_camss_top_ahb_clk = {
2238        .halt_reg = 0x56004,
2239        .clkr = {
2240                .enable_reg = 0x56004,
2241                .enable_mask = BIT(0),
2242                .hw.init = &(struct clk_init_data){
2243                        .name = "gcc_camss_top_ahb_clk",
2244                        .parent_names = (const char *[]){
2245                                "pcnoc_bfdcd_clk_src",
2246                        },
2247                        .num_parents = 1,
2248                        .flags = CLK_SET_RATE_PARENT,
2249                        .ops = &clk_branch2_ops,
2250                },
2251        },
2252};
2253
2254static struct clk_branch gcc_camss_cpp_ahb_clk = {
2255        .halt_reg = 0x58040,
2256        .clkr = {
2257                .enable_reg = 0x58040,
2258                .enable_mask = BIT(0),
2259                .hw.init = &(struct clk_init_data){
2260                        .name = "gcc_camss_cpp_ahb_clk",
2261                        .parent_names = (const char *[]){
2262                                "camss_ahb_clk_src",
2263                        },
2264                        .num_parents = 1,
2265                        .flags = CLK_SET_RATE_PARENT,
2266                        .ops = &clk_branch2_ops,
2267                },
2268        },
2269};
2270
2271static struct clk_branch gcc_camss_cpp_clk = {
2272        .halt_reg = 0x5803c,
2273        .clkr = {
2274                .enable_reg = 0x5803c,
2275                .enable_mask = BIT(0),
2276                .hw.init = &(struct clk_init_data){
2277                        .name = "gcc_camss_cpp_clk",
2278                        .parent_names = (const char *[]){
2279                                "cpp_clk_src",
2280                        },
2281                        .num_parents = 1,
2282                        .flags = CLK_SET_RATE_PARENT,
2283                        .ops = &clk_branch2_ops,
2284                },
2285        },
2286};
2287
2288static struct clk_branch gcc_camss_vfe0_clk = {
2289        .halt_reg = 0x58038,
2290        .clkr = {
2291                .enable_reg = 0x58038,
2292                .enable_mask = BIT(0),
2293                .hw.init = &(struct clk_init_data){
2294                        .name = "gcc_camss_vfe0_clk",
2295                        .parent_names = (const char *[]){
2296                                "vfe0_clk_src",
2297                        },
2298                        .num_parents = 1,
2299                        .flags = CLK_SET_RATE_PARENT,
2300                        .ops = &clk_branch2_ops,
2301                },
2302        },
2303};
2304
2305static struct clk_branch gcc_camss_vfe_ahb_clk = {
2306        .halt_reg = 0x58044,
2307        .clkr = {
2308                .enable_reg = 0x58044,
2309                .enable_mask = BIT(0),
2310                .hw.init = &(struct clk_init_data){
2311                        .name = "gcc_camss_vfe_ahb_clk",
2312                        .parent_names = (const char *[]){
2313                                "camss_ahb_clk_src",
2314                        },
2315                        .num_parents = 1,
2316                        .flags = CLK_SET_RATE_PARENT,
2317                        .ops = &clk_branch2_ops,
2318                },
2319        },
2320};
2321
2322static struct clk_branch gcc_camss_vfe_axi_clk = {
2323        .halt_reg = 0x58048,
2324        .clkr = {
2325                .enable_reg = 0x58048,
2326                .enable_mask = BIT(0),
2327                .hw.init = &(struct clk_init_data){
2328                        .name = "gcc_camss_vfe_axi_clk",
2329                        .parent_names = (const char *[]){
2330                                "system_noc_bfdcd_clk_src",
2331                        },
2332                        .num_parents = 1,
2333                        .flags = CLK_SET_RATE_PARENT,
2334                        .ops = &clk_branch2_ops,
2335                },
2336        },
2337};
2338
2339static struct clk_branch gcc_crypto_ahb_clk = {
2340        .halt_reg = 0x16024,
2341        .halt_check = BRANCH_HALT_VOTED,
2342        .clkr = {
2343                .enable_reg = 0x45004,
2344                .enable_mask = BIT(0),
2345                .hw.init = &(struct clk_init_data){
2346                        .name = "gcc_crypto_ahb_clk",
2347                        .parent_names = (const char *[]){
2348                                "pcnoc_bfdcd_clk_src",
2349                        },
2350                        .num_parents = 1,
2351                        .flags = CLK_SET_RATE_PARENT,
2352                        .ops = &clk_branch2_ops,
2353                },
2354        },
2355};
2356
2357static struct clk_branch gcc_crypto_axi_clk = {
2358        .halt_reg = 0x16020,
2359        .halt_check = BRANCH_HALT_VOTED,
2360        .clkr = {
2361                .enable_reg = 0x45004,
2362                .enable_mask = BIT(1),
2363                .hw.init = &(struct clk_init_data){
2364                        .name = "gcc_crypto_axi_clk",
2365                        .parent_names = (const char *[]){
2366                                "pcnoc_bfdcd_clk_src",
2367                        },
2368                        .num_parents = 1,
2369                        .flags = CLK_SET_RATE_PARENT,
2370                        .ops = &clk_branch2_ops,
2371                },
2372        },
2373};
2374
2375static struct clk_branch gcc_crypto_clk = {
2376        .halt_reg = 0x1601c,
2377        .halt_check = BRANCH_HALT_VOTED,
2378        .clkr = {
2379                .enable_reg = 0x45004,
2380                .enable_mask = BIT(2),
2381                .hw.init = &(struct clk_init_data){
2382                        .name = "gcc_crypto_clk",
2383                        .parent_names = (const char *[]){
2384                                "crypto_clk_src",
2385                        },
2386                        .num_parents = 1,
2387                        .flags = CLK_SET_RATE_PARENT,
2388                        .ops = &clk_branch2_ops,
2389                },
2390        },
2391};
2392
2393static struct clk_branch gcc_oxili_gmem_clk = {
2394        .halt_reg = 0x59024,
2395        .clkr = {
2396                .enable_reg = 0x59024,
2397                .enable_mask = BIT(0),
2398                .hw.init = &(struct clk_init_data){
2399                        .name = "gcc_oxili_gmem_clk",
2400                        .parent_names = (const char *[]){
2401                                "gfx3d_clk_src",
2402                        },
2403                        .num_parents = 1,
2404                        .flags = CLK_SET_RATE_PARENT,
2405                        .ops = &clk_branch2_ops,
2406                },
2407        },
2408};
2409
2410static struct clk_branch gcc_gp1_clk = {
2411        .halt_reg = 0x08000,
2412        .clkr = {
2413                .enable_reg = 0x08000,
2414                .enable_mask = BIT(0),
2415                .hw.init = &(struct clk_init_data){
2416                        .name = "gcc_gp1_clk",
2417                        .parent_names = (const char *[]){
2418                                "gp1_clk_src",
2419                        },
2420                        .num_parents = 1,
2421                        .flags = CLK_SET_RATE_PARENT,
2422                        .ops = &clk_branch2_ops,
2423                },
2424        },
2425};
2426
2427static struct clk_branch gcc_gp2_clk = {
2428        .halt_reg = 0x09000,
2429        .clkr = {
2430                .enable_reg = 0x09000,
2431                .enable_mask = BIT(0),
2432                .hw.init = &(struct clk_init_data){
2433                        .name = "gcc_gp2_clk",
2434                        .parent_names = (const char *[]){
2435                                "gp2_clk_src",
2436                        },
2437                        .num_parents = 1,
2438                        .flags = CLK_SET_RATE_PARENT,
2439                        .ops = &clk_branch2_ops,
2440                },
2441        },
2442};
2443
2444static struct clk_branch gcc_gp3_clk = {
2445        .halt_reg = 0x0a000,
2446        .clkr = {
2447                .enable_reg = 0x0a000,
2448                .enable_mask = BIT(0),
2449                .hw.init = &(struct clk_init_data){
2450                        .name = "gcc_gp3_clk",
2451                        .parent_names = (const char *[]){
2452                                "gp3_clk_src",
2453                        },
2454                        .num_parents = 1,
2455                        .flags = CLK_SET_RATE_PARENT,
2456                        .ops = &clk_branch2_ops,
2457                },
2458        },
2459};
2460
2461static struct clk_branch gcc_mdss_ahb_clk = {
2462        .halt_reg = 0x4d07c,
2463        .clkr = {
2464                .enable_reg = 0x4d07c,
2465                .enable_mask = BIT(0),
2466                .hw.init = &(struct clk_init_data){
2467                        .name = "gcc_mdss_ahb_clk",
2468                        .parent_names = (const char *[]){
2469                                "pcnoc_bfdcd_clk_src",
2470                        },
2471                        .num_parents = 1,
2472                        .flags = CLK_SET_RATE_PARENT,
2473                        .ops = &clk_branch2_ops,
2474                },
2475        },
2476};
2477
2478static struct clk_branch gcc_mdss_axi_clk = {
2479        .halt_reg = 0x4d080,
2480        .clkr = {
2481                .enable_reg = 0x4d080,
2482                .enable_mask = BIT(0),
2483                .hw.init = &(struct clk_init_data){
2484                        .name = "gcc_mdss_axi_clk",
2485                        .parent_names = (const char *[]){
2486                                "system_noc_bfdcd_clk_src",
2487                        },
2488                        .num_parents = 1,
2489                        .flags = CLK_SET_RATE_PARENT,
2490                        .ops = &clk_branch2_ops,
2491                },
2492        },
2493};
2494
2495static struct clk_branch gcc_mdss_byte0_clk = {
2496        .halt_reg = 0x4d094,
2497        .clkr = {
2498                .enable_reg = 0x4d094,
2499                .enable_mask = BIT(0),
2500                .hw.init = &(struct clk_init_data){
2501                        .name = "gcc_mdss_byte0_clk",
2502                        .parent_names = (const char *[]){
2503                                "byte0_clk_src",
2504                        },
2505                        .num_parents = 1,
2506                        .flags = CLK_SET_RATE_PARENT,
2507                        .ops = &clk_branch2_ops,
2508                },
2509        },
2510};
2511
2512static struct clk_branch gcc_mdss_esc0_clk = {
2513        .halt_reg = 0x4d098,
2514        .clkr = {
2515                .enable_reg = 0x4d098,
2516                .enable_mask = BIT(0),
2517                .hw.init = &(struct clk_init_data){
2518                        .name = "gcc_mdss_esc0_clk",
2519                        .parent_names = (const char *[]){
2520                                "esc0_clk_src",
2521                        },
2522                        .num_parents = 1,
2523                        .flags = CLK_SET_RATE_PARENT,
2524                        .ops = &clk_branch2_ops,
2525                },
2526        },
2527};
2528
2529static struct clk_branch gcc_mdss_mdp_clk = {
2530        .halt_reg = 0x4D088,
2531        .clkr = {
2532                .enable_reg = 0x4D088,
2533                .enable_mask = BIT(0),
2534                .hw.init = &(struct clk_init_data){
2535                        .name = "gcc_mdss_mdp_clk",
2536                        .parent_names = (const char *[]){
2537                                "mdp_clk_src",
2538                        },
2539                        .num_parents = 1,
2540                        .flags = CLK_SET_RATE_PARENT,
2541                        .ops = &clk_branch2_ops,
2542                },
2543        },
2544};
2545
2546static struct clk_branch gcc_mdss_pclk0_clk = {
2547        .halt_reg = 0x4d084,
2548        .clkr = {
2549                .enable_reg = 0x4d084,
2550                .enable_mask = BIT(0),
2551                .hw.init = &(struct clk_init_data){
2552                        .name = "gcc_mdss_pclk0_clk",
2553                        .parent_names = (const char *[]){
2554                                "pclk0_clk_src",
2555                        },
2556                        .num_parents = 1,
2557                        .flags = CLK_SET_RATE_PARENT,
2558                        .ops = &clk_branch2_ops,
2559                },
2560        },
2561};
2562
2563static struct clk_branch gcc_mdss_vsync_clk = {
2564        .halt_reg = 0x4d090,
2565        .clkr = {
2566                .enable_reg = 0x4d090,
2567                .enable_mask = BIT(0),
2568                .hw.init = &(struct clk_init_data){
2569                        .name = "gcc_mdss_vsync_clk",
2570                        .parent_names = (const char *[]){
2571                                "vsync_clk_src",
2572                        },
2573                        .num_parents = 1,
2574                        .flags = CLK_SET_RATE_PARENT,
2575                        .ops = &clk_branch2_ops,
2576                },
2577        },
2578};
2579
2580static struct clk_branch gcc_mss_cfg_ahb_clk = {
2581        .halt_reg = 0x49000,
2582        .clkr = {
2583                .enable_reg = 0x49000,
2584                .enable_mask = BIT(0),
2585                .hw.init = &(struct clk_init_data){
2586                        .name = "gcc_mss_cfg_ahb_clk",
2587                        .parent_names = (const char *[]){
2588                                "pcnoc_bfdcd_clk_src",
2589                        },
2590                        .num_parents = 1,
2591                        .flags = CLK_SET_RATE_PARENT,
2592                        .ops = &clk_branch2_ops,
2593                },
2594        },
2595};
2596
2597static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2598        .halt_reg = 0x49004,
2599        .clkr = {
2600                .enable_reg = 0x49004,
2601                .enable_mask = BIT(0),
2602                .hw.init = &(struct clk_init_data){
2603                        .name = "gcc_mss_q6_bimc_axi_clk",
2604                        .parent_names = (const char *[]){
2605                                "bimc_ddr_clk_src",
2606                        },
2607                        .num_parents = 1,
2608                        .flags = CLK_SET_RATE_PARENT,
2609                        .ops = &clk_branch2_ops,
2610                },
2611        },
2612};
2613
2614static struct clk_branch gcc_oxili_ahb_clk = {
2615        .halt_reg = 0x59028,
2616        .clkr = {
2617                .enable_reg = 0x59028,
2618                .enable_mask = BIT(0),
2619                .hw.init = &(struct clk_init_data){
2620                        .name = "gcc_oxili_ahb_clk",
2621                        .parent_names = (const char *[]){
2622                                "pcnoc_bfdcd_clk_src",
2623                        },
2624                        .num_parents = 1,
2625                        .flags = CLK_SET_RATE_PARENT,
2626                        .ops = &clk_branch2_ops,
2627                },
2628        },
2629};
2630
2631static struct clk_branch gcc_oxili_gfx3d_clk = {
2632        .halt_reg = 0x59020,
2633        .clkr = {
2634                .enable_reg = 0x59020,
2635                .enable_mask = BIT(0),
2636                .hw.init = &(struct clk_init_data){
2637                        .name = "gcc_oxili_gfx3d_clk",
2638                        .parent_names = (const char *[]){
2639                                "gfx3d_clk_src",
2640                        },
2641                        .num_parents = 1,
2642                        .flags = CLK_SET_RATE_PARENT,
2643                        .ops = &clk_branch2_ops,
2644                },
2645        },
2646};
2647
2648static struct clk_branch gcc_pdm2_clk = {
2649        .halt_reg = 0x4400c,
2650        .clkr = {
2651                .enable_reg = 0x4400c,
2652                .enable_mask = BIT(0),
2653                .hw.init = &(struct clk_init_data){
2654                        .name = "gcc_pdm2_clk",
2655                        .parent_names = (const char *[]){
2656                                "pdm2_clk_src",
2657                        },
2658                        .num_parents = 1,
2659                        .flags = CLK_SET_RATE_PARENT,
2660                        .ops = &clk_branch2_ops,
2661                },
2662        },
2663};
2664
2665static struct clk_branch gcc_pdm_ahb_clk = {
2666        .halt_reg = 0x44004,
2667        .clkr = {
2668                .enable_reg = 0x44004,
2669                .enable_mask = BIT(0),
2670                .hw.init = &(struct clk_init_data){
2671                        .name = "gcc_pdm_ahb_clk",
2672                        .parent_names = (const char *[]){
2673                                "pcnoc_bfdcd_clk_src",
2674                        },
2675                        .num_parents = 1,
2676                        .flags = CLK_SET_RATE_PARENT,
2677                        .ops = &clk_branch2_ops,
2678                },
2679        },
2680};
2681
2682static struct clk_branch gcc_prng_ahb_clk = {
2683        .halt_reg = 0x13004,
2684        .halt_check = BRANCH_HALT_VOTED,
2685        .clkr = {
2686                .enable_reg = 0x45004,
2687                .enable_mask = BIT(8),
2688                .hw.init = &(struct clk_init_data){
2689                        .name = "gcc_prng_ahb_clk",
2690                        .parent_names = (const char *[]){
2691                                "pcnoc_bfdcd_clk_src",
2692                        },
2693                        .num_parents = 1,
2694                        .ops = &clk_branch2_ops,
2695                },
2696        },
2697};
2698
2699static struct clk_branch gcc_sdcc1_ahb_clk = {
2700        .halt_reg = 0x4201c,
2701        .clkr = {
2702                .enable_reg = 0x4201c,
2703                .enable_mask = BIT(0),
2704                .hw.init = &(struct clk_init_data){
2705                        .name = "gcc_sdcc1_ahb_clk",
2706                        .parent_names = (const char *[]){
2707                                "pcnoc_bfdcd_clk_src",
2708                        },
2709                        .num_parents = 1,
2710                        .flags = CLK_SET_RATE_PARENT,
2711                        .ops = &clk_branch2_ops,
2712                },
2713        },
2714};
2715
2716static struct clk_branch gcc_sdcc1_apps_clk = {
2717        .halt_reg = 0x42018,
2718        .clkr = {
2719                .enable_reg = 0x42018,
2720                .enable_mask = BIT(0),
2721                .hw.init = &(struct clk_init_data){
2722                        .name = "gcc_sdcc1_apps_clk",
2723                        .parent_names = (const char *[]){
2724                                "sdcc1_apps_clk_src",
2725                        },
2726                        .num_parents = 1,
2727                        .flags = CLK_SET_RATE_PARENT,
2728                        .ops = &clk_branch2_ops,
2729                },
2730        },
2731};
2732
2733static struct clk_branch gcc_sdcc2_ahb_clk = {
2734        .halt_reg = 0x4301c,
2735        .clkr = {
2736                .enable_reg = 0x4301c,
2737                .enable_mask = BIT(0),
2738                .hw.init = &(struct clk_init_data){
2739                        .name = "gcc_sdcc2_ahb_clk",
2740                        .parent_names = (const char *[]){
2741                                "pcnoc_bfdcd_clk_src",
2742                        },
2743                        .num_parents = 1,
2744                        .flags = CLK_SET_RATE_PARENT,
2745                        .ops = &clk_branch2_ops,
2746                },
2747        },
2748};
2749
2750static struct clk_branch gcc_sdcc2_apps_clk = {
2751        .halt_reg = 0x43018,
2752        .clkr = {
2753                .enable_reg = 0x43018,
2754                .enable_mask = BIT(0),
2755                .hw.init = &(struct clk_init_data){
2756                        .name = "gcc_sdcc2_apps_clk",
2757                        .parent_names = (const char *[]){
2758                                "sdcc2_apps_clk_src",
2759                        },
2760                        .num_parents = 1,
2761                        .flags = CLK_SET_RATE_PARENT,
2762                        .ops = &clk_branch2_ops,
2763                },
2764        },
2765};
2766
2767static struct clk_rcg2 bimc_ddr_clk_src = {
2768        .cmd_rcgr = 0x32004,
2769        .hid_width = 5,
2770        .parent_map = gcc_xo_gpll0_bimc_map,
2771        .clkr.hw.init = &(struct clk_init_data){
2772                .name = "bimc_ddr_clk_src",
2773                .parent_names = gcc_xo_gpll0_bimc,
2774                .num_parents = 3,
2775                .ops = &clk_rcg2_ops,
2776                .flags = CLK_GET_RATE_NOCACHE,
2777        },
2778};
2779
2780static struct clk_branch gcc_apss_tcu_clk = {
2781        .halt_reg = 0x12018,
2782        .clkr = {
2783                .enable_reg = 0x4500c,
2784                .enable_mask = BIT(1),
2785                .hw.init = &(struct clk_init_data){
2786                        .name = "gcc_apss_tcu_clk",
2787                        .parent_names = (const char *[]){
2788                                "bimc_ddr_clk_src",
2789                        },
2790                        .num_parents = 1,
2791                        .ops = &clk_branch2_ops,
2792                },
2793        },
2794};
2795
2796static struct clk_branch gcc_gfx_tcu_clk = {
2797        .halt_reg = 0x12020,
2798        .clkr = {
2799                .enable_reg = 0x4500c,
2800                .enable_mask = BIT(2),
2801                .hw.init = &(struct clk_init_data){
2802                        .name = "gcc_gfx_tcu_clk",
2803                        .parent_names = (const char *[]){
2804                                "bimc_ddr_clk_src",
2805                        },
2806                        .num_parents = 1,
2807                        .ops = &clk_branch2_ops,
2808                },
2809        },
2810};
2811
2812static struct clk_branch gcc_gtcu_ahb_clk = {
2813        .halt_reg = 0x12044,
2814        .clkr = {
2815                .enable_reg = 0x4500c,
2816                .enable_mask = BIT(13),
2817                .hw.init = &(struct clk_init_data){
2818                        .name = "gcc_gtcu_ahb_clk",
2819                        .parent_names = (const char *[]){
2820                                "pcnoc_bfdcd_clk_src",
2821                        },
2822                        .num_parents = 1,
2823                        .flags = CLK_SET_RATE_PARENT,
2824                        .ops = &clk_branch2_ops,
2825                },
2826        },
2827};
2828
2829static struct clk_branch gcc_bimc_gfx_clk = {
2830        .halt_reg = 0x31024,
2831        .clkr = {
2832                .enable_reg = 0x31024,
2833                .enable_mask = BIT(0),
2834                .hw.init = &(struct clk_init_data){
2835                        .name = "gcc_bimc_gfx_clk",
2836                        .parent_names = (const char *[]){
2837                                "bimc_gpu_clk_src",
2838                        },
2839                        .num_parents = 1,
2840                        .flags = CLK_SET_RATE_PARENT,
2841                        .ops = &clk_branch2_ops,
2842                },
2843        },
2844};
2845
2846static struct clk_branch gcc_bimc_gpu_clk = {
2847        .halt_reg = 0x31040,
2848        .clkr = {
2849                .enable_reg = 0x31040,
2850                .enable_mask = BIT(0),
2851                .hw.init = &(struct clk_init_data){
2852                        .name = "gcc_bimc_gpu_clk",
2853                        .parent_names = (const char *[]){
2854                                "bimc_gpu_clk_src",
2855                        },
2856                        .num_parents = 1,
2857                        .flags = CLK_SET_RATE_PARENT,
2858                        .ops = &clk_branch2_ops,
2859                },
2860        },
2861};
2862
2863static struct clk_branch gcc_jpeg_tbu_clk = {
2864        .halt_reg = 0x12034,
2865        .clkr = {
2866                .enable_reg = 0x4500c,
2867                .enable_mask = BIT(10),
2868                .hw.init = &(struct clk_init_data){
2869                        .name = "gcc_jpeg_tbu_clk",
2870                        .parent_names = (const char *[]){
2871                                "system_noc_bfdcd_clk_src",
2872                        },
2873                        .num_parents = 1,
2874                        .flags = CLK_SET_RATE_PARENT,
2875                        .ops = &clk_branch2_ops,
2876                },
2877        },
2878};
2879
2880static struct clk_branch gcc_mdp_tbu_clk = {
2881        .halt_reg = 0x1201c,
2882        .clkr = {
2883                .enable_reg = 0x4500c,
2884                .enable_mask = BIT(4),
2885                .hw.init = &(struct clk_init_data){
2886                        .name = "gcc_mdp_tbu_clk",
2887                        .parent_names = (const char *[]){
2888                                "system_noc_bfdcd_clk_src",
2889                        },
2890                        .num_parents = 1,
2891                        .flags = CLK_SET_RATE_PARENT,
2892                        .ops = &clk_branch2_ops,
2893                },
2894        },
2895};
2896
2897static struct clk_branch gcc_smmu_cfg_clk = {
2898        .halt_reg = 0x12038,
2899        .clkr = {
2900                .enable_reg = 0x4500c,
2901                .enable_mask = BIT(12),
2902                .hw.init = &(struct clk_init_data){
2903                        .name = "gcc_smmu_cfg_clk",
2904                        .parent_names = (const char *[]){
2905                                "pcnoc_bfdcd_clk_src",
2906                        },
2907                        .num_parents = 1,
2908                        .flags = CLK_SET_RATE_PARENT,
2909                        .ops = &clk_branch2_ops,
2910                },
2911        },
2912};
2913
2914static struct clk_branch gcc_venus_tbu_clk = {
2915        .halt_reg = 0x12014,
2916        .clkr = {
2917                .enable_reg = 0x4500c,
2918                .enable_mask = BIT(5),
2919                .hw.init = &(struct clk_init_data){
2920                        .name = "gcc_venus_tbu_clk",
2921                        .parent_names = (const char *[]){
2922                                "system_noc_bfdcd_clk_src",
2923                        },
2924                        .num_parents = 1,
2925                        .flags = CLK_SET_RATE_PARENT,
2926                        .ops = &clk_branch2_ops,
2927                },
2928        },
2929};
2930
2931static struct clk_branch gcc_vfe_tbu_clk = {
2932        .halt_reg = 0x1203c,
2933        .clkr = {
2934                .enable_reg = 0x4500c,
2935                .enable_mask = BIT(9),
2936                .hw.init = &(struct clk_init_data){
2937                        .name = "gcc_vfe_tbu_clk",
2938                        .parent_names = (const char *[]){
2939                                "system_noc_bfdcd_clk_src",
2940                        },
2941                        .num_parents = 1,
2942                        .flags = CLK_SET_RATE_PARENT,
2943                        .ops = &clk_branch2_ops,
2944                },
2945        },
2946};
2947
2948static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2949        .halt_reg = 0x4102c,
2950        .clkr = {
2951                .enable_reg = 0x4102c,
2952                .enable_mask = BIT(0),
2953                .hw.init = &(struct clk_init_data){
2954                        .name = "gcc_usb2a_phy_sleep_clk",
2955                        .parent_names = (const char *[]){
2956                                "sleep_clk_src",
2957                        },
2958                        .num_parents = 1,
2959                        .flags = CLK_SET_RATE_PARENT,
2960                        .ops = &clk_branch2_ops,
2961                },
2962        },
2963};
2964
2965static struct clk_branch gcc_usb_hs_ahb_clk = {
2966        .halt_reg = 0x41008,
2967        .clkr = {
2968                .enable_reg = 0x41008,
2969                .enable_mask = BIT(0),
2970                .hw.init = &(struct clk_init_data){
2971                        .name = "gcc_usb_hs_ahb_clk",
2972                        .parent_names = (const char *[]){
2973                                "pcnoc_bfdcd_clk_src",
2974                        },
2975                        .num_parents = 1,
2976                        .flags = CLK_SET_RATE_PARENT,
2977                        .ops = &clk_branch2_ops,
2978                },
2979        },
2980};
2981
2982static struct clk_branch gcc_usb_hs_system_clk = {
2983        .halt_reg = 0x41004,
2984        .clkr = {
2985                .enable_reg = 0x41004,
2986                .enable_mask = BIT(0),
2987                .hw.init = &(struct clk_init_data){
2988                        .name = "gcc_usb_hs_system_clk",
2989                        .parent_names = (const char *[]){
2990                                "usb_hs_system_clk_src",
2991                        },
2992                        .num_parents = 1,
2993                        .flags = CLK_SET_RATE_PARENT,
2994                        .ops = &clk_branch2_ops,
2995                },
2996        },
2997};
2998
2999static struct clk_branch gcc_venus0_ahb_clk = {
3000        .halt_reg = 0x4c020,
3001        .clkr = {
3002                .enable_reg = 0x4c020,
3003                .enable_mask = BIT(0),
3004                .hw.init = &(struct clk_init_data){
3005                        .name = "gcc_venus0_ahb_clk",
3006                        .parent_names = (const char *[]){
3007                                "pcnoc_bfdcd_clk_src",
3008                        },
3009                        .num_parents = 1,
3010                        .flags = CLK_SET_RATE_PARENT,
3011                        .ops = &clk_branch2_ops,
3012                },
3013        },
3014};
3015
3016static struct clk_branch gcc_venus0_axi_clk = {
3017        .halt_reg = 0x4c024,
3018        .clkr = {
3019                .enable_reg = 0x4c024,
3020                .enable_mask = BIT(0),
3021                .hw.init = &(struct clk_init_data){
3022                        .name = "gcc_venus0_axi_clk",
3023                        .parent_names = (const char *[]){
3024                                "system_noc_bfdcd_clk_src",
3025                        },
3026                        .num_parents = 1,
3027                        .flags = CLK_SET_RATE_PARENT,
3028                        .ops = &clk_branch2_ops,
3029                },
3030        },
3031};
3032
3033static struct clk_branch gcc_venus0_vcodec0_clk = {
3034        .halt_reg = 0x4c01c,
3035        .clkr = {
3036                .enable_reg = 0x4c01c,
3037                .enable_mask = BIT(0),
3038                .hw.init = &(struct clk_init_data){
3039                        .name = "gcc_venus0_vcodec0_clk",
3040                        .parent_names = (const char *[]){
3041                                "vcodec0_clk_src",
3042                        },
3043                        .num_parents = 1,
3044                        .flags = CLK_SET_RATE_PARENT,
3045                        .ops = &clk_branch2_ops,
3046                },
3047        },
3048};
3049
3050static struct gdsc venus_gdsc = {
3051        .gdscr = 0x4c018,
3052        .pd = {
3053                .name = "venus",
3054        },
3055        .pwrsts = PWRSTS_OFF_ON,
3056};
3057
3058static struct gdsc mdss_gdsc = {
3059        .gdscr = 0x4d078,
3060        .pd = {
3061                .name = "mdss",
3062        },
3063        .pwrsts = PWRSTS_OFF_ON,
3064};
3065
3066static struct gdsc jpeg_gdsc = {
3067        .gdscr = 0x5701c,
3068        .pd = {
3069                .name = "jpeg",
3070        },
3071        .pwrsts = PWRSTS_OFF_ON,
3072};
3073
3074static struct gdsc vfe_gdsc = {
3075        .gdscr = 0x58034,
3076        .pd = {
3077                .name = "vfe",
3078        },
3079        .pwrsts = PWRSTS_OFF_ON,
3080};
3081
3082static struct gdsc oxili_gdsc = {
3083        .gdscr = 0x5901c,
3084        .pd = {
3085                .name = "oxili",
3086        },
3087        .pwrsts = PWRSTS_OFF_ON,
3088};
3089
3090static struct clk_regmap *gcc_msm8916_clocks[] = {
3091        [GPLL0] = &gpll0.clkr,
3092        [GPLL0_VOTE] = &gpll0_vote,
3093        [BIMC_PLL] = &bimc_pll.clkr,
3094        [BIMC_PLL_VOTE] = &bimc_pll_vote,
3095        [GPLL1] = &gpll1.clkr,
3096        [GPLL1_VOTE] = &gpll1_vote,
3097        [GPLL2] = &gpll2.clkr,
3098        [GPLL2_VOTE] = &gpll2_vote,
3099        [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3100        [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3101        [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3102        [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3103        [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3104        [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3105        [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3106        [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3107        [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3108        [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3109        [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3110        [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3111        [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3112        [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3113        [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3114        [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3115        [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3116        [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3117        [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3118        [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3119        [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3120        [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3121        [CCI_CLK_SRC] = &cci_clk_src.clkr,
3122        [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3123        [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3124        [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3125        [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3126        [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3127        [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3128        [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3129        [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3130        [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3131        [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3132        [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3133        [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3134        [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3135        [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3136        [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3137        [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3138        [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3139        [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3140        [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3141        [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3142        [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3143        [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3144        [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3145        [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3146        [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3147        [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3148        [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3149        [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3150        [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3151        [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3152        [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3153        [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3154        [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3155        [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3156        [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3157        [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3158        [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3159        [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3160        [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3161        [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3162        [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3163        [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3164        [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3165        [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3166        [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3167        [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3168        [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3169        [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3170        [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3171        [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3172        [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3173        [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3174        [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3175        [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3176        [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3177        [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3178        [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3179        [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3180        [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3181        [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3182        [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3183        [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3184        [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3185        [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3186        [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3187        [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3188        [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3189        [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3190        [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3191        [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3192        [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3193        [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3194        [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3195        [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3196        [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3197        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3198        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3199        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3200        [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3201        [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3202        [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3203        [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3204        [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3205        [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3206        [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3207        [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3208        [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3209        [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3210        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3211        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3212        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3213        [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3214        [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3215        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3216        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3217        [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3218        [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3219        [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3220        [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3221        [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3222        [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3223        [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3224        [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3225        [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3226        [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3227        [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3228        [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3229        [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3230        [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3231        [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3232        [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3233        [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3234        [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3235        [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3236        [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3237        [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3238        [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3239        [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3240        [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3241        [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3242        [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3243        [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3244        [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3245        [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3246        [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3247        [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3248        [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3249        [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3250        [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3251        [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3252};
3253
3254static struct gdsc *gcc_msm8916_gdscs[] = {
3255        [VENUS_GDSC] = &venus_gdsc,
3256        [MDSS_GDSC] = &mdss_gdsc,
3257        [JPEG_GDSC] = &jpeg_gdsc,
3258        [VFE_GDSC] = &vfe_gdsc,
3259        [OXILI_GDSC] = &oxili_gdsc,
3260};
3261
3262static const struct qcom_reset_map gcc_msm8916_resets[] = {
3263        [GCC_BLSP1_BCR] = { 0x01000 },
3264        [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3265        [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3266        [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3267        [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3268        [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3269        [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3270        [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3271        [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3272        [GCC_IMEM_BCR] = { 0x0e000 },
3273        [GCC_SMMU_BCR] = { 0x12000 },
3274        [GCC_APSS_TCU_BCR] = { 0x12050 },
3275        [GCC_SMMU_XPU_BCR] = { 0x12054 },
3276        [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3277        [GCC_PRNG_BCR] = { 0x13000 },
3278        [GCC_BOOT_ROM_BCR] = { 0x13008 },
3279        [GCC_CRYPTO_BCR] = { 0x16000 },
3280        [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3281        [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3282        [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3283        [GCC_DEHR_BCR] = { 0x1f000 },
3284        [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3285        [GCC_PCNOC_BCR] = { 0x27018 },
3286        [GCC_TCSR_BCR] = { 0x28000 },
3287        [GCC_QDSS_BCR] = { 0x29000 },
3288        [GCC_DCD_BCR] = { 0x2a000 },
3289        [GCC_MSG_RAM_BCR] = { 0x2b000 },
3290        [GCC_MPM_BCR] = { 0x2c000 },
3291        [GCC_SPMI_BCR] = { 0x2e000 },
3292        [GCC_SPDM_BCR] = { 0x2f000 },
3293        [GCC_MM_SPDM_BCR] = { 0x2f024 },
3294        [GCC_BIMC_BCR] = { 0x31000 },
3295        [GCC_RBCPR_BCR] = { 0x33000 },
3296        [GCC_TLMM_BCR] = { 0x34000 },
3297        [GCC_USB_HS_BCR] = { 0x41000 },
3298        [GCC_USB2A_PHY_BCR] = { 0x41028 },
3299        [GCC_SDCC1_BCR] = { 0x42000 },
3300        [GCC_SDCC2_BCR] = { 0x43000 },
3301        [GCC_PDM_BCR] = { 0x44000 },
3302        [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3303        [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3304        [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3305        [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3306        [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3307        [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3308        [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3309        [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3310        [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3311        [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3312        [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3313        [GCC_MMSS_BCR] = { 0x4b000 },
3314        [GCC_VENUS0_BCR] = { 0x4c014 },
3315        [GCC_MDSS_BCR] = { 0x4d074 },
3316        [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3317        [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3318        [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3319        [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3320        [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3321        [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3322        [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3323        [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3324        [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3325        [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3326        [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3327        [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3328        [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3329        [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3330        [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3331        [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3332        [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3333        [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3334        [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3335        [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3336        [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3337        [GCC_OXILI_BCR] = { 0x59018 },
3338        [GCC_GMEM_BCR] = { 0x5902c },
3339        [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3340        [GCC_MDP_TBU_BCR] = { 0x62000 },
3341        [GCC_GFX_TBU_BCR] = { 0x63000 },
3342        [GCC_GFX_TCU_BCR] = { 0x64000 },
3343        [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3344        [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3345        [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3346        [GCC_GTCU_AHB_BCR] = { 0x68000 },
3347        [GCC_SMMU_CFG_BCR] = { 0x69000 },
3348        [GCC_VFE_TBU_BCR] = { 0x6a000 },
3349        [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3350        [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3351        [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3352        [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3353};
3354
3355static const struct regmap_config gcc_msm8916_regmap_config = {
3356        .reg_bits       = 32,
3357        .reg_stride     = 4,
3358        .val_bits       = 32,
3359        .max_register   = 0x80000,
3360        .fast_io        = true,
3361};
3362
3363static const struct qcom_cc_desc gcc_msm8916_desc = {
3364        .config = &gcc_msm8916_regmap_config,
3365        .clks = gcc_msm8916_clocks,
3366        .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3367        .resets = gcc_msm8916_resets,
3368        .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3369        .gdscs = gcc_msm8916_gdscs,
3370        .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3371};
3372
3373static const struct of_device_id gcc_msm8916_match_table[] = {
3374        { .compatible = "qcom,gcc-msm8916" },
3375        { }
3376};
3377MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3378
3379static int gcc_msm8916_probe(struct platform_device *pdev)
3380{
3381        int ret;
3382        struct device *dev = &pdev->dev;
3383
3384        ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3385        if (ret)
3386                return ret;
3387
3388        ret = qcom_cc_register_sleep_clk(dev);
3389        if (ret)
3390                return ret;
3391
3392        return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3393}
3394
3395static struct platform_driver gcc_msm8916_driver = {
3396        .probe          = gcc_msm8916_probe,
3397        .driver         = {
3398                .name   = "gcc-msm8916",
3399                .of_match_table = gcc_msm8916_match_table,
3400        },
3401};
3402
3403static int __init gcc_msm8916_init(void)
3404{
3405        return platform_driver_register(&gcc_msm8916_driver);
3406}
3407core_initcall(gcc_msm8916_init);
3408
3409static void __exit gcc_msm8916_exit(void)
3410{
3411        platform_driver_unregister(&gcc_msm8916_driver);
3412}
3413module_exit(gcc_msm8916_exit);
3414
3415MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3416MODULE_LICENSE("GPL v2");
3417MODULE_ALIAS("platform:gcc-msm8916");
3418