LXR linux/drivers/clk/tegra/clk-periph-gate.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/slab.h>
   8#include <linux/io.h>
   9#include <linux/delay.h>
  10#include <linux/err.h>
  11
  12#include <soc/tegra/fuse.h>
  13
  14#include "clk.h"
  15
  16static DEFINE_SPINLOCK(periph_ref_lock);
  17
  18/* Macros to assist peripheral gate clock */
  19#define read_enb(gate) \
  20        readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
  21#define write_enb_set(val, gate) \
  22        writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
  23#define write_enb_clr(val, gate) \
  24        writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
  25
  26#define read_rst(gate) \
  27        readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
  28#define write_rst_clr(val, gate) \
  29        writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
  30
  31#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
  32
  33#define LVL2_CLK_GATE_OVRE 0x554
  34
  35/* Peripheral gate clock ops */
  36static int clk_periph_is_enabled(struct clk_hw *hw)
  37{
  38        struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
  39        int state = 1;
  40
  41        if (!(read_enb(gate) & periph_clk_to_bit(gate)))
  42                state = 0;
  43
  44        if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
  45                if (read_rst(gate) & periph_clk_to_bit(gate))
  46                        state = 0;
  47
  48        return state;
  49}
  50
  51static int clk_periph_enable(struct clk_hw *hw)
  52{
  53        struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
  54        unsigned long flags = 0;
  55
  56        spin_lock_irqsave(&periph_ref_lock, flags);
  57
  58        gate->enable_refcnt[gate->clk_num]++;
  59        if (gate->enable_refcnt[gate->clk_num] > 1) {
  60                spin_unlock_irqrestore(&periph_ref_lock, flags);
  61                return 0;
  62        }
  63
  64        write_enb_set(periph_clk_to_bit(gate), gate);
  65        udelay(2);
  66
  67        if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
  68            !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
  69                if (read_rst(gate) & periph_clk_to_bit(gate)) {
  70                        udelay(5); /* reset propogation delay */
  71                        write_rst_clr(periph_clk_to_bit(gate), gate);
  72                }
  73        }
  74
  75        if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
  76                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
  77                writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
  78                udelay(1);
  79                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
  80        }
  81
  82        spin_unlock_irqrestore(&periph_ref_lock, flags);
  83
  84        return 0;
  85}
  86
  87static void clk_periph_disable(struct clk_hw *hw)
  88{
  89        struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
  90        unsigned long flags = 0;
  91
  92        spin_lock_irqsave(&periph_ref_lock, flags);
  93
  94        gate->enable_refcnt[gate->clk_num]--;
  95        if (gate->enable_refcnt[gate->clk_num] > 0) {
  96                spin_unlock_irqrestore(&periph_ref_lock, flags);
  97                return;
  98        }
  99
 100        /*
 101         * If peripheral is in the APB bus then read the APB bus to
 102         * flush the write operation in apb bus. This will avoid the
 103         * peripheral access after disabling clock
 104         */
 105        if (gate->flags & TEGRA_PERIPH_ON_APB)
 106                tegra_read_chipid();
 107
 108        write_enb_clr(periph_clk_to_bit(gate), gate);
 109
 110        spin_unlock_irqrestore(&periph_ref_lock, flags);
 111}
 112
 113const struct clk_ops tegra_clk_periph_gate_ops = {
 114        .is_enabled = clk_periph_is_enabled,
 115        .enable = clk_periph_enable,
 116        .disable = clk_periph_disable,
 117};
 118
 119struct clk *tegra_clk_register_periph_gate(const char *name,
 120                const char *parent_name, u8 gate_flags, void __iomem *clk_base,
 121                unsigned long flags, int clk_num, int *enable_refcnt)
 122{
 123        struct tegra_clk_periph_gate *gate;
 124        struct clk *clk;
 125        struct clk_init_data init;
 126        const struct tegra_clk_periph_regs *pregs;
 127
 128        pregs = get_reg_bank(clk_num);
 129        if (!pregs)
 130                return ERR_PTR(-EINVAL);
 131
 132        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 133        if (!gate) {
 134                pr_err("%s: could not allocate periph gate clk\n", __func__);
 135                return ERR_PTR(-ENOMEM);
 136        }
 137
 138        init.name = name;
 139        init.flags = flags;
 140        init.parent_names = parent_name ? &parent_name : NULL;
 141        init.num_parents = parent_name ? 1 : 0;
 142        init.ops = &tegra_clk_periph_gate_ops;
 143
 144        gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
 145        gate->clk_base = clk_base;
 146        gate->clk_num = clk_num;
 147        gate->flags = gate_flags;
 148        gate->enable_refcnt = enable_refcnt;
 149        gate->regs = pregs;
 150
 151        if (read_enb(gate) & periph_clk_to_bit(gate))
 152                enable_refcnt[clk_num]++;
 153
 154        /* Data in .init is copied by clk_register(), so stack variable OK */
 155        gate->hw.init = &init;
 156
 157        clk = clk_register(NULL, &gate->hw);
 158        if (IS_ERR(clk))
 159                kfree(gate);
 160
 161        return clk;
 162}
 163