LXR linux/drivers/cpufreq/imx-cpufreq-dt.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2019 NXP
   4 */
   5
   6#include <linux/cpu.h>
   7#include <linux/err.h>
   8#include <linux/init.h>
   9#include <linux/kernel.h>
  10#include <linux/module.h>
  11#include <linux/nvmem-consumer.h>
  12#include <linux/of.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_opp.h>
  15#include <linux/slab.h>
  16
  17#define OCOTP_CFG3_SPEED_GRADE_SHIFT    8
  18#define OCOTP_CFG3_SPEED_GRADE_MASK     (0x3 << 8)
  19#define OCOTP_CFG3_MKT_SEGMENT_SHIFT    6
  20#define OCOTP_CFG3_MKT_SEGMENT_MASK     (0x3 << 6)
  21
  22/* cpufreq-dt device registered by imx-cpufreq-dt */
  23static struct platform_device *cpufreq_dt_pdev;
  24static struct opp_table *cpufreq_opp_table;
  25
  26static int imx_cpufreq_dt_probe(struct platform_device *pdev)
  27{
  28        struct device *cpu_dev = get_cpu_device(0);
  29        u32 cell_value, supported_hw[2];
  30        int speed_grade, mkt_segment;
  31        int ret;
  32
  33        ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
  34        if (ret)
  35                return ret;
  36
  37        speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
  38        mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
  39
  40        /*
  41         * Early samples without fuses written report "0 0" which means
  42         * consumer segment and minimum speed grading.
  43         *
  44         * According to datasheet minimum speed grading is not supported for
  45         * consumer parts so clamp to 1 to avoid warning for "no OPPs"
  46         *
  47         * Applies to i.MX8M series SoCs.
  48         */
  49        if (mkt_segment == 0 && speed_grade == 0 && (
  50                        of_machine_is_compatible("fsl,imx8mm") ||
  51                        of_machine_is_compatible("fsl,imx8mn") ||
  52                        of_machine_is_compatible("fsl,imx8mq")))
  53                speed_grade = 1;
  54
  55        supported_hw[0] = BIT(speed_grade);
  56        supported_hw[1] = BIT(mkt_segment);
  57        dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
  58                        speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
  59
  60        cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
  61        if (IS_ERR(cpufreq_opp_table)) {
  62                ret = PTR_ERR(cpufreq_opp_table);
  63                dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
  64                return ret;
  65        }
  66
  67        cpufreq_dt_pdev = platform_device_register_data(
  68                        &pdev->dev, "cpufreq-dt", -1, NULL, 0);
  69        if (IS_ERR(cpufreq_dt_pdev)) {
  70                dev_pm_opp_put_supported_hw(cpufreq_opp_table);
  71                ret = PTR_ERR(cpufreq_dt_pdev);
  72                dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
  73                return ret;
  74        }
  75
  76        return 0;
  77}
  78
  79static int imx_cpufreq_dt_remove(struct platform_device *pdev)
  80{
  81        platform_device_unregister(cpufreq_dt_pdev);
  82        dev_pm_opp_put_supported_hw(cpufreq_opp_table);
  83
  84        return 0;
  85}
  86
  87static struct platform_driver imx_cpufreq_dt_driver = {
  88        .probe = imx_cpufreq_dt_probe,
  89        .remove = imx_cpufreq_dt_remove,
  90        .driver = {
  91                .name = "imx-cpufreq-dt",
  92        },
  93};
  94module_platform_driver(imx_cpufreq_dt_driver);
  95
  96MODULE_ALIAS("platform:imx-cpufreq-dt");
  97MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
  98MODULE_LICENSE("GPL v2");
  99