1
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7
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/sys_soc.h>
13
14#include "compat.h"
15#include "regs.h"
16#include "intern.h"
17#include "jr.h"
18#include "desc_constr.h"
19#include "ctrl.h"
20
21bool caam_dpaa2;
22EXPORT_SYMBOL(caam_dpaa2);
23
24#ifdef CONFIG_CAAM_QI
25#include "qi.h"
26#endif
27
28
29
30
31
32static inline struct clk *caam_drv_identify_clk(struct device *dev,
33 char *clk_name)
34{
35 return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
36}
37
38
39
40
41
42static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
43{
44 u32 *jump_cmd, op_flags;
45
46 init_job_desc(desc, 0);
47
48 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
49 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
50
51
52 append_operation(desc, op_flags);
53
54 if (!handle && do_sk) {
55
56
57
58
59
60 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
61 set_jump_tgt_here(desc, jump_cmd);
62
63
64
65
66
67 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
68
69
70 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
71 OP_ALG_AAI_RNG4_SK);
72 }
73
74 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
75}
76
77
78static void build_deinstantiation_desc(u32 *desc, int handle)
79{
80 init_job_desc(desc, 0);
81
82
83 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
84 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
85
86 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
87}
88
89
90
91
92
93
94
95
96
97
98
99static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
100 u32 *status)
101{
102 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
103 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
104 struct caam_deco __iomem *deco = ctrlpriv->deco;
105 unsigned int timeout = 100000;
106 u32 deco_dbg_reg, deco_state, flags;
107 int i;
108
109
110 if (ctrlpriv->virt_en == 1) {
111 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
112
113 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
114 --timeout)
115 cpu_relax();
116
117 timeout = 100000;
118 }
119
120 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
121
122 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
123 --timeout)
124 cpu_relax();
125
126 if (!timeout) {
127 dev_err(ctrldev, "failed to acquire DECO 0\n");
128 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
129 return -ENODEV;
130 }
131
132 for (i = 0; i < desc_len(desc); i++)
133 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
134
135 flags = DECO_JQCR_WHL;
136
137
138
139
140 if (desc_len(desc) >= 4)
141 flags |= DECO_JQCR_FOUR;
142
143
144 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
145
146 timeout = 10000000;
147 do {
148 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
149
150 if (ctrlpriv->era < 10)
151 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
152 DESC_DBG_DECO_STAT_SHIFT;
153 else
154 deco_state = (rd_reg32(&deco->dbg_exec) &
155 DESC_DER_DECO_STAT_MASK) >>
156 DESC_DER_DECO_STAT_SHIFT;
157
158
159
160
161
162 if (deco_state == DECO_STAT_HOST_ERR)
163 break;
164
165 cpu_relax();
166 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
167
168 *status = rd_reg32(&deco->op_status_hi) &
169 DECO_OP_STATUS_HI_ERR_MASK;
170
171 if (ctrlpriv->virt_en == 1)
172 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
173
174
175 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
176
177 if (!timeout)
178 return -EAGAIN;
179
180 return 0;
181}
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
203 int gen_sk)
204{
205 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
206 struct caam_ctrl __iomem *ctrl;
207 u32 *desc, status = 0, rdsta_val;
208 int ret = 0, sh_idx;
209
210 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
211 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
212 if (!desc)
213 return -ENOMEM;
214
215 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
216
217
218
219
220 if ((1 << sh_idx) & state_handle_mask)
221 continue;
222
223
224 build_instantiation_desc(desc, sh_idx, gen_sk);
225
226
227 ret = run_descriptor_deco0(ctrldev, desc, &status);
228
229
230
231
232
233
234
235
236
237
238 if (ret)
239 break;
240
241 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
242 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
243 !(rdsta_val & (1 << sh_idx))) {
244 ret = -EAGAIN;
245 break;
246 }
247
248 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
249
250 memset(desc, 0x00, CAAM_CMD_SZ * 7);
251 }
252
253 kfree(desc);
254
255 return ret;
256}
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
272{
273 u32 *desc, status;
274 int sh_idx, ret = 0;
275
276 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
277 if (!desc)
278 return -ENOMEM;
279
280 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
281
282
283
284
285
286 if ((1 << sh_idx) & state_handle_mask) {
287
288
289
290
291 build_deinstantiation_desc(desc, sh_idx);
292
293
294 ret = run_descriptor_deco0(ctrldev, desc, &status);
295
296 if (ret ||
297 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
298 dev_err(ctrldev,
299 "Failed to deinstantiate RNG4 SH%d\n",
300 sh_idx);
301 break;
302 }
303 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
304 }
305 }
306
307 kfree(desc);
308
309 return ret;
310}
311
312static int caam_remove(struct platform_device *pdev)
313{
314 struct device *ctrldev;
315 struct caam_drv_private *ctrlpriv;
316 struct caam_ctrl __iomem *ctrl;
317
318 ctrldev = &pdev->dev;
319 ctrlpriv = dev_get_drvdata(ctrldev);
320 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
321
322
323 of_platform_depopulate(ctrldev);
324
325#ifdef CONFIG_CAAM_QI
326 if (ctrlpriv->qi_init)
327 caam_qi_shutdown(ctrldev);
328#endif
329
330
331
332
333
334 if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init)
335 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
336
337
338#ifdef CONFIG_DEBUG_FS
339 debugfs_remove_recursive(ctrlpriv->dfs_root);
340#endif
341
342
343 iounmap(ctrl);
344
345
346 clk_disable_unprepare(ctrlpriv->caam_ipg);
347 if (ctrlpriv->caam_mem)
348 clk_disable_unprepare(ctrlpriv->caam_mem);
349 clk_disable_unprepare(ctrlpriv->caam_aclk);
350 if (ctrlpriv->caam_emi_slow)
351 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
352 return 0;
353}
354
355
356
357
358
359
360
361static void kick_trng(struct platform_device *pdev, int ent_delay)
362{
363 struct device *ctrldev = &pdev->dev;
364 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
365 struct caam_ctrl __iomem *ctrl;
366 struct rng4tst __iomem *r4tst;
367 u32 val;
368
369 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
370 r4tst = &ctrl->r4tst[0];
371
372
373 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
374
375
376
377
378
379
380
381
382
383 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
384 >> RTSDCTL_ENT_DLY_SHIFT;
385 if (ent_delay <= val)
386 goto start_rng;
387
388 val = rd_reg32(&r4tst->rtsdctl);
389 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
390 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
391 wr_reg32(&r4tst->rtsdctl, val);
392
393 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
394
395 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
396
397 val = rd_reg32(&r4tst->rtmctl);
398start_rng:
399
400
401
402
403 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
404}
405
406static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
407{
408 static const struct {
409 u16 ip_id;
410 u8 maj_rev;
411 u8 era;
412 } id[] = {
413 {0x0A10, 1, 1},
414 {0x0A10, 2, 2},
415 {0x0A12, 1, 3},
416 {0x0A14, 1, 3},
417 {0x0A14, 2, 4},
418 {0x0A16, 1, 4},
419 {0x0A10, 3, 4},
420 {0x0A11, 1, 4},
421 {0x0A18, 1, 4},
422 {0x0A11, 2, 5},
423 {0x0A12, 2, 5},
424 {0x0A13, 1, 5},
425 {0x0A1C, 1, 5}
426 };
427 u32 ccbvid, id_ms;
428 u8 maj_rev, era;
429 u16 ip_id;
430 int i;
431
432 ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
433 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
434 if (era)
435 return era;
436
437 id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
438 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
439 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
440
441 for (i = 0; i < ARRAY_SIZE(id); i++)
442 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
443 return id[i].era;
444
445 return -ENOTSUPP;
446}
447
448
449
450
451
452
453
454
455static int caam_get_era(struct caam_ctrl __iomem *ctrl)
456{
457 struct device_node *caam_node;
458 int ret;
459 u32 prop;
460
461 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
462 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
463 of_node_put(caam_node);
464
465 if (!ret)
466 return prop;
467 else
468 return caam_get_era_from_hw(ctrl);
469}
470
471
472
473
474
475
476
477
478
479
480static void handle_imx6_err005766(u32 *mcr)
481{
482 if (of_machine_is_compatible("fsl,imx6q") ||
483 of_machine_is_compatible("fsl,imx6dl") ||
484 of_machine_is_compatible("fsl,imx6qp"))
485 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
486 1 << MCFGR_AXIPIPE_SHIFT);
487}
488
489static const struct of_device_id caam_match[] = {
490 {
491 .compatible = "fsl,sec-v4.0",
492 },
493 {
494 .compatible = "fsl,sec4.0",
495 },
496 {},
497};
498MODULE_DEVICE_TABLE(of, caam_match);
499
500
501static int caam_probe(struct platform_device *pdev)
502{
503 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
504 u64 caam_id;
505 static const struct soc_device_attribute imx_soc[] = {
506 {.family = "Freescale i.MX"},
507 {},
508 };
509 struct device *dev;
510 struct device_node *nprop, *np;
511 struct caam_ctrl __iomem *ctrl;
512 struct caam_drv_private *ctrlpriv;
513 struct clk *clk;
514#ifdef CONFIG_DEBUG_FS
515 struct caam_perfmon *perfmon;
516#endif
517 u32 scfgr, comp_params;
518 u8 rng_vid;
519 int pg_size;
520 int BLOCK_OFFSET = 0;
521
522 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
523 if (!ctrlpriv)
524 return -ENOMEM;
525
526 dev = &pdev->dev;
527 dev_set_drvdata(dev, ctrlpriv);
528 nprop = pdev->dev.of_node;
529
530 caam_imx = (bool)soc_device_match(imx_soc);
531
532
533 clk = caam_drv_identify_clk(&pdev->dev, "ipg");
534 if (IS_ERR(clk)) {
535 ret = PTR_ERR(clk);
536 dev_err(&pdev->dev,
537 "can't identify CAAM ipg clk: %d\n", ret);
538 return ret;
539 }
540 ctrlpriv->caam_ipg = clk;
541
542 if (!of_machine_is_compatible("fsl,imx7d") &&
543 !of_machine_is_compatible("fsl,imx7s") &&
544 !of_machine_is_compatible("fsl,imx7ulp")) {
545 clk = caam_drv_identify_clk(&pdev->dev, "mem");
546 if (IS_ERR(clk)) {
547 ret = PTR_ERR(clk);
548 dev_err(&pdev->dev,
549 "can't identify CAAM mem clk: %d\n", ret);
550 return ret;
551 }
552 ctrlpriv->caam_mem = clk;
553 }
554
555 clk = caam_drv_identify_clk(&pdev->dev, "aclk");
556 if (IS_ERR(clk)) {
557 ret = PTR_ERR(clk);
558 dev_err(&pdev->dev,
559 "can't identify CAAM aclk clk: %d\n", ret);
560 return ret;
561 }
562 ctrlpriv->caam_aclk = clk;
563
564 if (!of_machine_is_compatible("fsl,imx6ul") &&
565 !of_machine_is_compatible("fsl,imx7d") &&
566 !of_machine_is_compatible("fsl,imx7s") &&
567 !of_machine_is_compatible("fsl,imx7ulp")) {
568 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
569 if (IS_ERR(clk)) {
570 ret = PTR_ERR(clk);
571 dev_err(&pdev->dev,
572 "can't identify CAAM emi_slow clk: %d\n", ret);
573 return ret;
574 }
575 ctrlpriv->caam_emi_slow = clk;
576 }
577
578 ret = clk_prepare_enable(ctrlpriv->caam_ipg);
579 if (ret < 0) {
580 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
581 return ret;
582 }
583
584 if (ctrlpriv->caam_mem) {
585 ret = clk_prepare_enable(ctrlpriv->caam_mem);
586 if (ret < 0) {
587 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
588 ret);
589 goto disable_caam_ipg;
590 }
591 }
592
593 ret = clk_prepare_enable(ctrlpriv->caam_aclk);
594 if (ret < 0) {
595 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
596 goto disable_caam_mem;
597 }
598
599 if (ctrlpriv->caam_emi_slow) {
600 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
601 if (ret < 0) {
602 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
603 ret);
604 goto disable_caam_aclk;
605 }
606 }
607
608
609
610 ctrl = of_iomap(nprop, 0);
611 if (ctrl == NULL) {
612 dev_err(dev, "caam: of_iomap() failed\n");
613 ret = -ENOMEM;
614 goto disable_caam_emi_slow;
615 }
616
617 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
618 (CSTA_PLEND | CSTA_ALT_PLEND));
619
620
621 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
622 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
623
624
625
626
627 if (pg_size == 0)
628 BLOCK_OFFSET = PG_SIZE_4K;
629 else
630 BLOCK_OFFSET = PG_SIZE_64K;
631
632 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
633 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
634 ((__force uint8_t *)ctrl +
635 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
636 );
637 ctrlpriv->deco = (struct caam_deco __iomem __force *)
638 ((__force uint8_t *)ctrl +
639 BLOCK_OFFSET * DECO_BLOCK_NUMBER
640 );
641
642
643 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
644
645
646
647
648
649
650
651 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
652 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
653 ctrlpriv->mc_en = !!np;
654 of_node_put(np);
655
656 if (!ctrlpriv->mc_en)
657 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
658 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
659 MCFGR_WDENABLE | MCFGR_LARGE_BURST |
660 (sizeof(dma_addr_t) == sizeof(u64) ?
661 MCFGR_LONG_PTR : 0));
662
663 handle_imx6_err005766(&ctrl->mcr);
664
665
666
667
668
669 scfgr = rd_reg32(&ctrl->scfgr);
670
671 ctrlpriv->virt_en = 0;
672 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
673
674
675
676 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
677 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
678 (scfgr & SCFGR_VIRT_EN)))
679 ctrlpriv->virt_en = 1;
680 } else {
681
682 if (comp_params & CTPR_MS_VIRT_EN_POR)
683 ctrlpriv->virt_en = 1;
684 }
685
686 if (ctrlpriv->virt_en == 1)
687 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
688 JRSTART_JR1_START | JRSTART_JR2_START |
689 JRSTART_JR3_START);
690
691 if (sizeof(dma_addr_t) == sizeof(u64)) {
692 if (caam_dpaa2)
693 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
694 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
695 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
696 else
697 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
698 } else {
699 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
700 }
701 if (ret) {
702 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
703 goto iounmap_ctrl;
704 }
705
706 ctrlpriv->era = caam_get_era(ctrl);
707 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
708
709#ifdef CONFIG_DEBUG_FS
710
711
712
713
714
715 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
716
717 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
718 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
719#endif
720
721
722 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
723 if (ctrlpriv->qi_present && !caam_dpaa2) {
724 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
725 ((__force uint8_t *)ctrl +
726 BLOCK_OFFSET * QI_BLOCK_NUMBER
727 );
728
729 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
730
731
732#ifdef CONFIG_CAAM_QI
733 ret = caam_qi_init(pdev);
734 if (ret)
735 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
736#endif
737 }
738
739 ret = of_platform_populate(nprop, caam_match, NULL, dev);
740 if (ret) {
741 dev_err(dev, "JR platform devices creation error\n");
742 goto shutdown_qi;
743 }
744
745 ring = 0;
746 for_each_available_child_of_node(nprop, np)
747 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
748 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
749 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
750 ((__force uint8_t *)ctrl +
751 (ring + JR_BLOCK_NUMBER) *
752 BLOCK_OFFSET
753 );
754 ctrlpriv->total_jobrs++;
755 ring++;
756 }
757
758
759 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
760 dev_err(dev, "no queues configured, terminating\n");
761 ret = -ENOMEM;
762 goto caam_remove;
763 }
764
765 if (ctrlpriv->era < 10)
766 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
767 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
768 else
769 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
770 CHA_VER_VID_SHIFT;
771
772
773
774
775
776
777 if (!ctrlpriv->mc_en && rng_vid >= 4) {
778 ctrlpriv->rng4_sh_init =
779 rd_reg32(&ctrl->r4tst[0].rdsta);
780
781
782
783
784
785
786 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
787 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
788 do {
789 int inst_handles =
790 rd_reg32(&ctrl->r4tst[0].rdsta) &
791 RDSTA_IFMASK;
792
793
794
795
796
797
798
799
800 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
801 dev_info(dev,
802 "Entropy delay = %u\n",
803 ent_delay);
804 kick_trng(pdev, ent_delay);
805 ent_delay += 400;
806 }
807
808
809
810
811
812
813
814 ret = instantiate_rng(dev, inst_handles,
815 gen_sk);
816 if (ret == -EAGAIN)
817
818
819
820
821 cpu_relax();
822 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
823 if (ret) {
824 dev_err(dev, "failed to instantiate RNG");
825 goto caam_remove;
826 }
827
828
829
830
831 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
832
833
834 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
835 }
836
837
838
839 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
840 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
841
842
843 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
844 ctrlpriv->era);
845 dev_info(dev, "job rings = %d, qi = %d\n",
846 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
847
848#ifdef CONFIG_DEBUG_FS
849 debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
850 ctrlpriv->ctl, &perfmon->req_dequeued,
851 &caam_fops_u64_ro);
852 debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
853 ctrlpriv->ctl, &perfmon->ob_enc_req,
854 &caam_fops_u64_ro);
855 debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
856 ctrlpriv->ctl, &perfmon->ib_dec_req,
857 &caam_fops_u64_ro);
858 debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
859 ctrlpriv->ctl, &perfmon->ob_enc_bytes,
860 &caam_fops_u64_ro);
861 debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
862 ctrlpriv->ctl, &perfmon->ob_prot_bytes,
863 &caam_fops_u64_ro);
864 debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
865 ctrlpriv->ctl, &perfmon->ib_dec_bytes,
866 &caam_fops_u64_ro);
867 debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
868 ctrlpriv->ctl, &perfmon->ib_valid_bytes,
869 &caam_fops_u64_ro);
870
871
872 debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
873 ctrlpriv->ctl, &perfmon->faultaddr,
874 &caam_fops_u32_ro);
875 debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
876 ctrlpriv->ctl, &perfmon->faultdetail,
877 &caam_fops_u32_ro);
878 debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
879 ctrlpriv->ctl, &perfmon->status,
880 &caam_fops_u32_ro);
881
882
883 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
884 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
885 debugfs_create_blob("kek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
886 &ctrlpriv->ctl_kek_wrap);
887
888 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
889 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
890 debugfs_create_blob("tkek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
891 &ctrlpriv->ctl_tkek_wrap);
892
893 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
894 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
895 debugfs_create_blob("tdsk", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
896 &ctrlpriv->ctl_tdsk_wrap);
897#endif
898 return 0;
899
900caam_remove:
901 caam_remove(pdev);
902 return ret;
903
904shutdown_qi:
905#ifdef CONFIG_CAAM_QI
906 if (ctrlpriv->qi_init)
907 caam_qi_shutdown(dev);
908#endif
909iounmap_ctrl:
910 iounmap(ctrl);
911disable_caam_emi_slow:
912 if (ctrlpriv->caam_emi_slow)
913 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
914disable_caam_aclk:
915 clk_disable_unprepare(ctrlpriv->caam_aclk);
916disable_caam_mem:
917 if (ctrlpriv->caam_mem)
918 clk_disable_unprepare(ctrlpriv->caam_mem);
919disable_caam_ipg:
920 clk_disable_unprepare(ctrlpriv->caam_ipg);
921 return ret;
922}
923
924static struct platform_driver caam_driver = {
925 .driver = {
926 .name = "caam",
927 .of_match_table = caam_match,
928 },
929 .probe = caam_probe,
930 .remove = caam_remove,
931};
932
933module_platform_driver(caam_driver);
934
935MODULE_LICENSE("GPL");
936MODULE_DESCRIPTION("FSL CAAM request backend");
937MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
938