LXR linux/drivers/crypto/cavium/nitrox/nitrox

   1// SPDX-License-Identifier: GPL-2.0
   2#include <linux/delay.h>
   3
   4#include "nitrox_dev.h"
   5#include "nitrox_csr.h"
   6
   7#define PLL_REF_CLK 50
   8#define MAX_CSR_RETRIES 10
   9
  10/**
  11 * emu_enable_cores - Enable EMU cluster cores.
  12 * @ndev: NITROX device
  13 */
  14static void emu_enable_cores(struct nitrox_device *ndev)
  15{
  16        union emu_se_enable emu_se;
  17        union emu_ae_enable emu_ae;
  18        int i;
  19
  20        /* AE cores 20 per cluster */
  21        emu_ae.value = 0;
  22        emu_ae.s.enable = 0xfffff;
  23
  24        /* SE cores 16 per cluster */
  25        emu_se.value = 0;
  26        emu_se.s.enable = 0xffff;
  27
  28        /* enable per cluster cores */
  29        for (i = 0; i < NR_CLUSTERS; i++) {
  30                nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
  31                nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
  32        }
  33}
  34
  35/**
  36 * nitrox_config_emu_unit - configure EMU unit.
  37 * @ndev: NITROX device
  38 */
  39void nitrox_config_emu_unit(struct nitrox_device *ndev)
  40{
  41        union emu_wd_int_ena_w1s emu_wd_int;
  42        union emu_ge_int_ena_w1s emu_ge_int;
  43        u64 offset;
  44        int i;
  45
  46        /* enable cores */
  47        emu_enable_cores(ndev);
  48
  49        /* enable general error and watch dog interrupts */
  50        emu_ge_int.value = 0;
  51        emu_ge_int.s.se_ge = 0xffff;
  52        emu_ge_int.s.ae_ge = 0xfffff;
  53        emu_wd_int.value = 0;
  54        emu_wd_int.s.se_wd = 1;
  55
  56        for (i = 0; i < NR_CLUSTERS; i++) {
  57                offset = EMU_WD_INT_ENA_W1SX(i);
  58                nitrox_write_csr(ndev, offset, emu_wd_int.value);
  59                offset = EMU_GE_INT_ENA_W1SX(i);
  60                nitrox_write_csr(ndev, offset, emu_ge_int.value);
  61        }
  62}
  63
  64static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
  65{
  66        union nps_pkt_in_instr_ctl pkt_in_ctl;
  67        union nps_pkt_in_done_cnts pkt_in_cnts;
  68        int max_retries = MAX_CSR_RETRIES;
  69        u64 offset;
  70
  71        /* step 1: disable the ring, clear enable bit */
  72        offset = NPS_PKT_IN_INSTR_CTLX(ring);
  73        pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
  74        pkt_in_ctl.s.enb = 0;
  75        nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
  76
  77        /* step 2: wait to clear [ENB] */
  78        usleep_range(100, 150);
  79        do {
  80                pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
  81                if (!pkt_in_ctl.s.enb)
  82                        break;
  83                udelay(50);
  84        } while (max_retries--);
  85
  86        /* step 3: clear done counts */
  87        offset = NPS_PKT_IN_DONE_CNTSX(ring);
  88        pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
  89        nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
  90        usleep_range(50, 100);
  91}
  92
  93void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
  94{
  95        union nps_pkt_in_instr_ctl pkt_in_ctl;
  96        int max_retries = MAX_CSR_RETRIES;
  97        u64 offset;
  98
  99        /* 64-byte instruction size */
 100        offset = NPS_PKT_IN_INSTR_CTLX(ring);
 101        pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
 102        pkt_in_ctl.s.is64b = 1;
 103        pkt_in_ctl.s.enb = 1;
 104        nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
 105
 106        /* wait for set [ENB] */
 107        do {
 108                pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
 109                if (pkt_in_ctl.s.enb)
 110                        break;
 111                udelay(50);
 112        } while (max_retries--);
 113}
 114
 115/**
 116 * nitrox_config_pkt_input_rings - configure Packet Input Rings
 117 * @ndev: NITROX device
 118 */
 119void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
 120{
 121        int i;
 122
 123        for (i = 0; i < ndev->nr_queues; i++) {
 124                struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
 125                union nps_pkt_in_instr_rsize pkt_in_rsize;
 126                union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
 127                u64 offset;
 128
 129                reset_pkt_input_ring(ndev, i);
 130
 131                /**
 132                 * step 4:
 133                 * configure ring base address 16-byte aligned,
 134                 * size and interrupt threshold.
 135                 */
 136                offset = NPS_PKT_IN_INSTR_BADDRX(i);
 137                nitrox_write_csr(ndev, offset, cmdq->dma);
 138
 139                /* configure ring size */
 140                offset = NPS_PKT_IN_INSTR_RSIZEX(i);
 141                pkt_in_rsize.value = 0;
 142                pkt_in_rsize.s.rsize = ndev->qlen;
 143                nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
 144
 145                /* set high threshold for pkt input ring interrupts */
 146                offset = NPS_PKT_IN_INT_LEVELSX(i);
 147                nitrox_write_csr(ndev, offset, 0xffffffff);
 148
 149                /* step 5: clear off door bell counts */
 150                offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
 151                pkt_in_dbell.value = 0;
 152                pkt_in_dbell.s.dbell = 0xffffffff;
 153                nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
 154
 155                /* enable the ring */
 156                enable_pkt_input_ring(ndev, i);
 157        }
 158}
 159
 160static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
 161{
 162        union nps_pkt_slc_ctl pkt_slc_ctl;
 163        union nps_pkt_slc_cnts pkt_slc_cnts;
 164        int max_retries = MAX_CSR_RETRIES;
 165        u64 offset;
 166
 167        /* step 1: disable slc port */
 168        offset = NPS_PKT_SLC_CTLX(port);
 169        pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
 170        pkt_slc_ctl.s.enb = 0;
 171        nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
 172
 173        /* step 2 */
 174        usleep_range(100, 150);
 175        /* wait to clear [ENB] */
 176        do {
 177                pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
 178                if (!pkt_slc_ctl.s.enb)
 179                        break;
 180                udelay(50);
 181        } while (max_retries--);
 182
 183        /* step 3: clear slc counters */
 184        offset = NPS_PKT_SLC_CNTSX(port);
 185        pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
 186        nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
 187        usleep_range(50, 100);
 188}
 189
 190void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
 191{
 192        union nps_pkt_slc_ctl pkt_slc_ctl;
 193        int max_retries = MAX_CSR_RETRIES;
 194        u64 offset;
 195
 196        offset = NPS_PKT_SLC_CTLX(port);
 197        pkt_slc_ctl.value = 0;
 198        pkt_slc_ctl.s.enb = 1;
 199        /*
 200         * 8 trailing 0x00 bytes will be added
 201         * to the end of the outgoing packet.
 202         */
 203        pkt_slc_ctl.s.z = 1;
 204        /* enable response header */
 205        pkt_slc_ctl.s.rh = 1;
 206        nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
 207
 208        /* wait to set [ENB] */
 209        do {
 210                pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
 211                if (pkt_slc_ctl.s.enb)
 212                        break;
 213                udelay(50);
 214        } while (max_retries--);
 215}
 216
 217static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
 218{
 219        union nps_pkt_slc_int_levels pkt_slc_int;
 220        u64 offset;
 221
 222        reset_pkt_solicit_port(ndev, port);
 223
 224        /* step 4: configure interrupt levels */
 225        offset = NPS_PKT_SLC_INT_LEVELSX(port);
 226        pkt_slc_int.value = 0;
 227        /* time interrupt threshold */
 228        pkt_slc_int.s.timet = 0x3fffff;
 229        nitrox_write_csr(ndev, offset, pkt_slc_int.value);
 230
 231        /* enable the solicit port */
 232        enable_pkt_solicit_port(ndev, port);
 233}
 234
 235void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
 236{
 237        int i;
 238
 239        for (i = 0; i < ndev->nr_queues; i++)
 240                config_pkt_solicit_port(ndev, i);
 241}
 242
 243/**
 244 * enable_nps_interrupts - enable NPS interrutps
 245 * @ndev: NITROX device.
 246 *
 247 * This includes NPS core, packet in and slc interrupts.
 248 */
 249static void enable_nps_interrupts(struct nitrox_device *ndev)
 250{
 251        union nps_core_int_ena_w1s core_int;
 252
 253        /* NPS core interrutps */
 254        core_int.value = 0;
 255        core_int.s.host_wr_err = 1;
 256        core_int.s.host_wr_timeout = 1;
 257        core_int.s.exec_wr_timeout = 1;
 258        core_int.s.npco_dma_malform = 1;
 259        core_int.s.host_nps_wr_err = 1;
 260        nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
 261
 262        /* NPS packet in ring interrupts */
 263        nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
 264        nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
 265        nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
 266        /* NPS packet slc port interrupts */
 267        nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
 268        nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
 269        nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
 270}
 271
 272void nitrox_config_nps_unit(struct nitrox_device *ndev)
 273{
 274        union nps_core_gbl_vfcfg core_gbl_vfcfg;
 275
 276        /* endian control information */
 277        nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
 278
 279        /* disable ILK interface */
 280        core_gbl_vfcfg.value = 0;
 281        core_gbl_vfcfg.s.ilk_disable = 1;
 282        core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
 283        nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
 284        /* config input and solicit ports */
 285        nitrox_config_pkt_input_rings(ndev);
 286        nitrox_config_pkt_solicit_ports(ndev);
 287
 288        /* enable interrupts */
 289        enable_nps_interrupts(ndev);
 290}
 291
 292void nitrox_config_pom_unit(struct nitrox_device *ndev)
 293{
 294        union pom_int_ena_w1s pom_int;
 295        int i;
 296
 297        /* enable pom interrupts */
 298        pom_int.value = 0;
 299        pom_int.s.illegal_dport = 1;
 300        nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
 301
 302        /* enable perf counters */
 303        for (i = 0; i < ndev->hw.se_cores; i++)
 304                nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
 305}
 306
 307/**
 308 * nitrox_config_rand_unit - enable NITROX random number unit
 309 * @ndev: NITROX device
 310 */
 311void nitrox_config_rand_unit(struct nitrox_device *ndev)
 312{
 313        union efl_rnm_ctl_status efl_rnm_ctl;
 314        u64 offset;
 315
 316        offset = EFL_RNM_CTL_STATUS;
 317        efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
 318        efl_rnm_ctl.s.ent_en = 1;
 319        efl_rnm_ctl.s.rng_en = 1;
 320        nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
 321}
 322
 323void nitrox_config_efl_unit(struct nitrox_device *ndev)
 324{
 325        int i;
 326
 327        for (i = 0; i < NR_CLUSTERS; i++) {
 328                union efl_core_int_ena_w1s efl_core_int;
 329                u64 offset;
 330
 331                /* EFL core interrupts */
 332                offset = EFL_CORE_INT_ENA_W1SX(i);
 333                efl_core_int.value = 0;
 334                efl_core_int.s.len_ovr = 1;
 335                efl_core_int.s.d_left = 1;
 336                efl_core_int.s.epci_decode_err = 1;
 337                nitrox_write_csr(ndev, offset, efl_core_int.value);
 338
 339                offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
 340                nitrox_write_csr(ndev, offset, (~0ULL));
 341                offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
 342                nitrox_write_csr(ndev, offset, (~0ULL));
 343        }
 344}
 345
 346void nitrox_config_bmi_unit(struct nitrox_device *ndev)
 347{
 348        union bmi_ctl bmi_ctl;
 349        union bmi_int_ena_w1s bmi_int_ena;
 350        u64 offset;
 351
 352        /* no threshold limits for PCIe */
 353        offset = BMI_CTL;
 354        bmi_ctl.value = nitrox_read_csr(ndev, offset);
 355        bmi_ctl.s.max_pkt_len = 0xff;
 356        bmi_ctl.s.nps_free_thrsh = 0xff;
 357        bmi_ctl.s.nps_hdrq_thrsh = 0x7a;
 358        nitrox_write_csr(ndev, offset, bmi_ctl.value);
 359
 360        /* enable interrupts */
 361        offset = BMI_INT_ENA_W1S;
 362        bmi_int_ena.value = 0;
 363        bmi_int_ena.s.max_len_err_nps = 1;
 364        bmi_int_ena.s.pkt_rcv_err_nps = 1;
 365        bmi_int_ena.s.fpf_undrrn = 1;
 366        nitrox_write_csr(ndev, offset, bmi_int_ena.value);
 367}
 368
 369void nitrox_config_bmo_unit(struct nitrox_device *ndev)
 370{
 371        union bmo_ctl2 bmo_ctl2;
 372        u64 offset;
 373
 374        /* no threshold limits for PCIe */
 375        offset = BMO_CTL2;
 376        bmo_ctl2.value = nitrox_read_csr(ndev, offset);
 377        bmo_ctl2.s.nps_slc_buf_thrsh = 0xff;
 378        nitrox_write_csr(ndev, offset, bmo_ctl2.value);
 379}
 380
 381void invalidate_lbc(struct nitrox_device *ndev)
 382{
 383        union lbc_inval_ctl lbc_ctl;
 384        union lbc_inval_status lbc_stat;
 385        int max_retries = MAX_CSR_RETRIES;
 386        u64 offset;
 387
 388        /* invalidate LBC */
 389        offset = LBC_INVAL_CTL;
 390        lbc_ctl.value = nitrox_read_csr(ndev, offset);
 391        lbc_ctl.s.cam_inval_start = 1;
 392        nitrox_write_csr(ndev, offset, lbc_ctl.value);
 393
 394        offset = LBC_INVAL_STATUS;
 395        do {
 396                lbc_stat.value = nitrox_read_csr(ndev, offset);
 397                if (lbc_stat.s.done)
 398                        break;
 399                udelay(50);
 400        } while (max_retries--);
 401}
 402
 403void nitrox_config_lbc_unit(struct nitrox_device *ndev)
 404{
 405        union lbc_int_ena_w1s lbc_int_ena;
 406        u64 offset;
 407
 408        invalidate_lbc(ndev);
 409
 410        /* enable interrupts */
 411        offset = LBC_INT_ENA_W1S;
 412        lbc_int_ena.value = 0;
 413        lbc_int_ena.s.dma_rd_err = 1;
 414        lbc_int_ena.s.over_fetch_err = 1;
 415        lbc_int_ena.s.cam_inval_abort = 1;
 416        lbc_int_ena.s.cam_hard_err = 1;
 417        nitrox_write_csr(ndev, offset, lbc_int_ena.value);
 418
 419        offset = LBC_PLM_VF1_64_INT_ENA_W1S;
 420        nitrox_write_csr(ndev, offset, (~0ULL));
 421        offset = LBC_PLM_VF65_128_INT_ENA_W1S;
 422        nitrox_write_csr(ndev, offset, (~0ULL));
 423
 424        offset = LBC_ELM_VF1_64_INT_ENA_W1S;
 425        nitrox_write_csr(ndev, offset, (~0ULL));
 426        offset = LBC_ELM_VF65_128_INT_ENA_W1S;
 427        nitrox_write_csr(ndev, offset, (~0ULL));
 428}
 429
 430void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
 431{
 432        union nps_core_gbl_vfcfg vfcfg;
 433
 434        vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
 435        vfcfg.s.cfg = mode & 0x7;
 436
 437        nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
 438}
 439
 440static const char *get_core_option(u8 se_cores, u8 ae_cores)
 441{
 442        const char *option = "";
 443
 444        if (ae_cores == AE_MAX_CORES) {
 445                switch (se_cores) {
 446                case SE_MAX_CORES:
 447                        option = "60";
 448                        break;
 449                case 40:
 450                        option = "60s";
 451                        break;
 452                }
 453        } else if (ae_cores == (AE_MAX_CORES / 2)) {
 454                option = "30";
 455        } else {
 456                option = "60i";
 457        }
 458
 459        return option;
 460}
 461
 462static const char *get_feature_option(u8 zip_cores, int core_freq)
 463{
 464        if (zip_cores == 0)
 465                return "";
 466        else if (zip_cores < ZIP_MAX_CORES)
 467                return "-C15";
 468
 469        if (core_freq >= 850)
 470                return "-C45";
 471        else if (core_freq >= 750)
 472                return "-C35";
 473        else if (core_freq >= 550)
 474                return "-C25";
 475
 476        return "";
 477}
 478
 479void nitrox_get_hwinfo(struct nitrox_device *ndev)
 480{
 481        union emu_fuse_map emu_fuse;
 482        union rst_boot rst_boot;
 483        union fus_dat1 fus_dat1;
 484        unsigned char name[IFNAMSIZ * 2] = {};
 485        int i, dead_cores;
 486        u64 offset;
 487
 488        /* get core frequency */
 489        offset = RST_BOOT;
 490        rst_boot.value = nitrox_read_csr(ndev, offset);
 491        ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
 492
 493        for (i = 0; i < NR_CLUSTERS; i++) {
 494                offset = EMU_FUSE_MAPX(i);
 495                emu_fuse.value = nitrox_read_csr(ndev, offset);
 496                if (emu_fuse.s.valid) {
 497                        dead_cores = hweight32(emu_fuse.s.ae_fuse);
 498                        ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
 499                        dead_cores = hweight16(emu_fuse.s.se_fuse);
 500                        ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
 501                }
 502        }
 503        /* find zip hardware availability */
 504        offset = FUS_DAT1;
 505        fus_dat1.value = nitrox_read_csr(ndev, offset);
 506        if (!fus_dat1.nozip) {
 507                dead_cores = hweight8(fus_dat1.zip_info);
 508                ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
 509        }
 510
 511        /* determine the partname
 512         * CNN55<core option>-<freq><pincount>-<feature option>-<rev>
 513         */
 514        snprintf(name, sizeof(name), "CNN55%s-%3dBG676%s-1.%u",
 515                 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
 516                 ndev->hw.freq,
 517                 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
 518                 ndev->hw.revision_id);
 519
 520        /* copy partname */
 521        strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
 522}
 523
 524void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
 525{
 526        u64 value = ~0ULL;
 527        u64 reg_addr;
 528
 529        /* Mailbox interrupt low enable set register */
 530        reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1S;
 531        nitrox_write_csr(ndev, reg_addr, value);
 532
 533        /* Mailbox interrupt high enable set register */
 534        reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1S;
 535        nitrox_write_csr(ndev, reg_addr, value);
 536}
 537
 538void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
 539{
 540        u64 value = ~0ULL;
 541        u64 reg_addr;
 542
 543        /* Mailbox interrupt low enable clear register */
 544        reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1C;
 545        nitrox_write_csr(ndev, reg_addr, value);
 546
 547        /* Mailbox interrupt high enable clear register */
 548        reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1C;
 549        nitrox_write_csr(ndev, reg_addr, value);
 550}
 551