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11#ifndef __CCP_DEV_H__
12#define __CCP_DEV_H__
13
14#include <linux/device.h>
15#include <linux/pci.h>
16#include <linux/spinlock.h>
17#include <linux/mutex.h>
18#include <linux/list.h>
19#include <linux/wait.h>
20#include <linux/dmapool.h>
21#include <linux/hw_random.h>
22#include <linux/bitops.h>
23#include <linux/interrupt.h>
24#include <linux/irqreturn.h>
25#include <linux/dmaengine.h>
26
27#include "sp-dev.h"
28
29#define MAX_CCP_NAME_LEN 16
30#define MAX_DMAPOOL_NAME_LEN 32
31
32#define MAX_HW_QUEUES 5
33#define MAX_CMD_QLEN 100
34
35#define TRNG_RETRIES 10
36
37#define CACHE_NONE 0x00
38#define CACHE_WB_NO_ALLOC 0xb7
39
40
41#define Q_MASK_REG 0x000
42#define TRNG_OUT_REG 0x00c
43#define IRQ_MASK_REG 0x040
44#define IRQ_STATUS_REG 0x200
45
46#define DEL_CMD_Q_JOB 0x124
47#define DEL_Q_ACTIVE 0x00000200
48#define DEL_Q_ID_SHIFT 6
49
50#define CMD_REQ0 0x180
51#define CMD_REQ_INCR 0x04
52
53#define CMD_Q_STATUS_BASE 0x210
54#define CMD_Q_INT_STATUS_BASE 0x214
55#define CMD_Q_STATUS_INCR 0x20
56
57#define CMD_Q_CACHE_BASE 0x228
58#define CMD_Q_CACHE_INC 0x20
59
60#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
61#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
62
63
64#define CMD5_QUEUE_MASK_OFFSET 0x00
65#define CMD5_QUEUE_PRIO_OFFSET 0x04
66#define CMD5_REQID_CONFIG_OFFSET 0x08
67#define CMD5_CMD_TIMEOUT_OFFSET 0x10
68#define LSB_PUBLIC_MASK_LO_OFFSET 0x18
69#define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
70#define LSB_PRIVATE_MASK_LO_OFFSET 0x20
71#define LSB_PRIVATE_MASK_HI_OFFSET 0x24
72#define CMD5_PSP_CCP_VERSION 0x100
73
74#define CMD5_Q_CONTROL_BASE 0x0000
75#define CMD5_Q_TAIL_LO_BASE 0x0004
76#define CMD5_Q_HEAD_LO_BASE 0x0008
77#define CMD5_Q_INT_ENABLE_BASE 0x000C
78#define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
79
80#define CMD5_Q_STATUS_BASE 0x0100
81#define CMD5_Q_INT_STATUS_BASE 0x0104
82#define CMD5_Q_DMA_STATUS_BASE 0x0108
83#define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
84#define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
85#define CMD5_Q_ABORT_BASE 0x0114
86#define CMD5_Q_AX_CACHE_BASE 0x0118
87
88#define CMD5_CONFIG_0_OFFSET 0x6000
89#define CMD5_TRNG_CTL_OFFSET 0x6008
90#define CMD5_AES_MASK_OFFSET 0x6010
91#define CMD5_CLK_GATE_CTL_OFFSET 0x603C
92
93
94#define CMD5_Q_STATUS_INCR 0x1000
95
96
97#define CMD5_Q_RUN 0x1
98#define CMD5_Q_HALT 0x2
99#define CMD5_Q_MEM_LOCATION 0x4
100#define CMD5_Q_SIZE 0x1F
101#define CMD5_Q_SHIFT 3
102#define COMMANDS_PER_QUEUE 16
103#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
104 CMD5_Q_SIZE)
105#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
106#define Q_DESC_SIZE sizeof(struct ccp5_desc)
107#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
108
109#define INT_COMPLETION 0x1
110#define INT_ERROR 0x2
111#define INT_QUEUE_STOPPED 0x4
112#define INT_EMPTY_QUEUE 0x8
113#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
114
115#define LSB_REGION_WIDTH 5
116#define MAX_LSB_CNT 8
117
118#define LSB_SIZE 16
119#define LSB_ITEM_SIZE 32
120#define PLSB_MAP_SIZE (LSB_SIZE)
121#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
122
123#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
124
125
126#define REQ0_WAIT_FOR_WRITE 0x00000004
127#define REQ0_INT_ON_COMPLETE 0x00000002
128#define REQ0_STOP_ON_COMPLETE 0x00000001
129
130#define REQ0_CMD_Q_SHIFT 9
131#define REQ0_JOBID_SHIFT 3
132
133
134#define REQ1_PROTECT_SHIFT 27
135#define REQ1_ENGINE_SHIFT 23
136#define REQ1_KEY_KSB_SHIFT 2
137
138#define REQ1_EOM 0x00000002
139#define REQ1_INIT 0x00000001
140
141
142#define REQ1_AES_TYPE_SHIFT 21
143#define REQ1_AES_MODE_SHIFT 18
144#define REQ1_AES_ACTION_SHIFT 17
145#define REQ1_AES_CFB_SIZE_SHIFT 10
146
147
148#define REQ1_XTS_AES_SIZE_SHIFT 10
149
150
151#define REQ1_SHA_TYPE_SHIFT 21
152
153
154#define REQ1_RSA_MOD_SIZE_SHIFT 10
155
156
157#define REQ1_PT_BW_SHIFT 12
158#define REQ1_PT_BS_SHIFT 10
159
160
161#define REQ1_ECC_AFFINE_CONVERT 0x00200000
162#define REQ1_ECC_FUNCTION_SHIFT 18
163
164
165#define REQ4_KSB_SHIFT 18
166#define REQ4_MEMTYPE_SHIFT 16
167
168
169#define REQ6_MEMTYPE_SHIFT 16
170
171
172#define KSB_START 77
173#define KSB_END 127
174#define KSB_COUNT (KSB_END - KSB_START + 1)
175#define CCP_SB_BITS 256
176
177#define CCP_JOBID_MASK 0x0000003f
178
179
180
181#define CCP_DMA_DFLT 0x0
182#define CCP_DMA_PRIV 0x1
183#define CCP_DMA_PUB 0x2
184
185#define CCP_DMAPOOL_MAX_SIZE 64
186#define CCP_DMAPOOL_ALIGN BIT(5)
187
188#define CCP_REVERSE_BUF_SIZE 64
189
190#define CCP_AES_KEY_SB_COUNT 1
191#define CCP_AES_CTX_SB_COUNT 1
192
193#define CCP_XTS_AES_KEY_SB_COUNT 1
194#define CCP5_XTS_AES_KEY_SB_COUNT 2
195#define CCP_XTS_AES_CTX_SB_COUNT 1
196
197#define CCP_DES3_KEY_SB_COUNT 1
198#define CCP_DES3_CTX_SB_COUNT 1
199
200#define CCP_SHA_SB_COUNT 1
201
202#define CCP_RSA_MAX_WIDTH 4096
203#define CCP5_RSA_MAX_WIDTH 16384
204
205#define CCP_PASSTHRU_BLOCKSIZE 256
206#define CCP_PASSTHRU_MASKSIZE 32
207#define CCP_PASSTHRU_SB_COUNT 1
208
209#define CCP_ECC_MODULUS_BYTES 48
210#define CCP_ECC_MAX_OPERANDS 6
211#define CCP_ECC_MAX_OUTPUTS 3
212#define CCP_ECC_SRC_BUF_SIZE 448
213#define CCP_ECC_DST_BUF_SIZE 192
214#define CCP_ECC_OPERAND_SIZE 64
215#define CCP_ECC_OUTPUT_SIZE 64
216#define CCP_ECC_RESULT_OFFSET 60
217#define CCP_ECC_RESULT_SUCCESS 0x0001
218
219#define CCP_SB_BYTES 32
220
221struct ccp_op;
222struct ccp_device;
223struct ccp_cmd;
224struct ccp_fns;
225
226struct ccp_dma_cmd {
227 struct list_head entry;
228
229 struct ccp_cmd ccp_cmd;
230};
231
232struct ccp_dma_desc {
233 struct list_head entry;
234
235 struct ccp_device *ccp;
236
237 struct list_head pending;
238 struct list_head active;
239
240 enum dma_status status;
241 struct dma_async_tx_descriptor tx_desc;
242 size_t len;
243};
244
245struct ccp_dma_chan {
246 struct ccp_device *ccp;
247
248 spinlock_t lock;
249 struct list_head created;
250 struct list_head pending;
251 struct list_head active;
252 struct list_head complete;
253
254 struct tasklet_struct cleanup_tasklet;
255
256 enum dma_status status;
257 struct dma_chan dma_chan;
258};
259
260struct ccp_cmd_queue {
261 struct ccp_device *ccp;
262
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264 u32 id;
265
266
267 struct dma_pool *dma_pool;
268
269
270 struct ccp5_desc *qbase;
271
272
273 struct mutex q_mutex ____cacheline_aligned;
274 unsigned int qidx;
275
276
277 unsigned int qsize;
278 dma_addr_t qbase_dma;
279 dma_addr_t qdma_tail;
280
281
282 u32 sb_key;
283 u32 sb_ctx;
284
285
286 DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
287
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290 int lsb;
291 DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
292
293
294 struct task_struct *kthread;
295 unsigned int active;
296 unsigned int suspended;
297
298
299 unsigned int free_slots;
300
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302 u32 int_ok;
303 u32 int_err;
304
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306 void __iomem *reg_control;
307 void __iomem *reg_tail_lo;
308 void __iomem *reg_head_lo;
309 void __iomem *reg_int_enable;
310 void __iomem *reg_interrupt_status;
311 void __iomem *reg_status;
312 void __iomem *reg_int_status;
313 void __iomem *reg_dma_status;
314 void __iomem *reg_dma_read_status;
315 void __iomem *reg_dma_write_status;
316 u32 qcontrol;
317
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319 u32 int_status;
320 u32 q_status;
321 u32 q_int_status;
322 u32 cmd_error;
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325 wait_queue_head_t int_queue;
326 unsigned int int_rcvd;
327
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329 unsigned long total_ops;
330 unsigned long total_aes_ops;
331 unsigned long total_xts_aes_ops;
332 unsigned long total_3des_ops;
333 unsigned long total_sha_ops;
334 unsigned long total_rsa_ops;
335 unsigned long total_pt_ops;
336 unsigned long total_ecc_ops;
337} ____cacheline_aligned;
338
339struct ccp_device {
340 struct list_head entry;
341
342 struct ccp_vdata *vdata;
343 unsigned int ord;
344 char name[MAX_CCP_NAME_LEN];
345 char rngname[MAX_CCP_NAME_LEN];
346
347 struct device *dev;
348 struct sp_device *sp;
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352 void *dev_specific;
353 unsigned int qim;
354 unsigned int irq;
355 bool use_tasklet;
356 struct tasklet_struct irq_tasklet;
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364 struct mutex req_mutex ____cacheline_aligned;
365 void __iomem *io_regs;
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372 spinlock_t cmd_lock ____cacheline_aligned;
373 unsigned int cmd_count;
374 struct list_head cmd;
375 struct list_head backlog;
376
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380 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
381 unsigned int cmd_q_count;
382
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385 struct hwrng hwrng;
386 unsigned int hwrng_retries;
387
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390 struct dma_device dma_dev;
391 struct ccp_dma_chan *ccp_dma_chan;
392 struct kmem_cache *dma_cmd_cache;
393 struct kmem_cache *dma_desc_cache;
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397 atomic_t current_id ____cacheline_aligned;
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416 struct mutex sb_mutex ____cacheline_aligned;
417 DECLARE_BITMAP(sb, KSB_COUNT);
418 wait_queue_head_t sb_queue;
419 unsigned int sb_avail;
420 unsigned int sb_count;
421 u32 sb_start;
422
423
424 DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
425
426
427 unsigned int suspending;
428 wait_queue_head_t suspend_queue;
429
430
431 unsigned int axcache;
432
433
434 unsigned long total_interrupts;
435
436
437 struct dentry *debugfs_instance;
438};
439
440enum ccp_memtype {
441 CCP_MEMTYPE_SYSTEM = 0,
442 CCP_MEMTYPE_SB,
443 CCP_MEMTYPE_LOCAL,
444 CCP_MEMTYPE__LAST,
445};
446#define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
447
448
449struct ccp_dma_info {
450 dma_addr_t address;
451 unsigned int offset;
452 unsigned int length;
453 enum dma_data_direction dir;
454} __packed __aligned(4);
455
456struct ccp_dm_workarea {
457 struct device *dev;
458 struct dma_pool *dma_pool;
459
460 u8 *address;
461 struct ccp_dma_info dma;
462 unsigned int length;
463};
464
465struct ccp_sg_workarea {
466 struct scatterlist *sg;
467 int nents;
468 unsigned int sg_used;
469
470 struct scatterlist *dma_sg;
471 struct device *dma_dev;
472 unsigned int dma_count;
473 enum dma_data_direction dma_dir;
474
475 u64 bytes_left;
476};
477
478struct ccp_data {
479 struct ccp_sg_workarea sg_wa;
480 struct ccp_dm_workarea dm_wa;
481};
482
483struct ccp_mem {
484 enum ccp_memtype type;
485 union {
486 struct ccp_dma_info dma;
487 u32 sb;
488 } u;
489};
490
491struct ccp_aes_op {
492 enum ccp_aes_type type;
493 enum ccp_aes_mode mode;
494 enum ccp_aes_action action;
495 unsigned int size;
496};
497
498struct ccp_xts_aes_op {
499 enum ccp_aes_type type;
500 enum ccp_aes_action action;
501 enum ccp_xts_aes_unit_size unit_size;
502};
503
504struct ccp_des3_op {
505 enum ccp_des3_type type;
506 enum ccp_des3_mode mode;
507 enum ccp_des3_action action;
508};
509
510struct ccp_sha_op {
511 enum ccp_sha_type type;
512 u64 msg_bits;
513};
514
515struct ccp_rsa_op {
516 u32 mod_size;
517 u32 input_len;
518};
519
520struct ccp_passthru_op {
521 enum ccp_passthru_bitwise bit_mod;
522 enum ccp_passthru_byteswap byte_swap;
523};
524
525struct ccp_ecc_op {
526 enum ccp_ecc_function function;
527};
528
529struct ccp_op {
530 struct ccp_cmd_queue *cmd_q;
531
532 u32 jobid;
533 u32 ioc;
534 u32 soc;
535 u32 sb_key;
536 u32 sb_ctx;
537 u32 init;
538 u32 eom;
539
540 struct ccp_mem src;
541 struct ccp_mem dst;
542 struct ccp_mem exp;
543
544 union {
545 struct ccp_aes_op aes;
546 struct ccp_xts_aes_op xts;
547 struct ccp_des3_op des3;
548 struct ccp_sha_op sha;
549 struct ccp_rsa_op rsa;
550 struct ccp_passthru_op passthru;
551 struct ccp_ecc_op ecc;
552 } u;
553};
554
555static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
556{
557 return lower_32_bits(info->address + info->offset);
558}
559
560static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
561{
562 return upper_32_bits(info->address + info->offset) & 0x0000ffff;
563}
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577struct dword0 {
578 unsigned int soc:1;
579 unsigned int ioc:1;
580 unsigned int rsvd1:1;
581 unsigned int init:1;
582 unsigned int eom:1;
583 unsigned int function:15;
584 unsigned int engine:4;
585 unsigned int prot:1;
586 unsigned int rsvd2:7;
587};
588
589struct dword3 {
590 unsigned int src_hi:16;
591 unsigned int src_mem:2;
592 unsigned int lsb_cxt_id:8;
593 unsigned int rsvd1:5;
594 unsigned int fixed:1;
595};
596
597union dword4 {
598 __le32 dst_lo;
599 __le32 sha_len_lo;
600};
601
602union dword5 {
603 struct {
604 unsigned int dst_hi:16;
605 unsigned int dst_mem:2;
606 unsigned int rsvd1:13;
607 unsigned int fixed:1;
608 } fields;
609 __le32 sha_len_hi;
610};
611
612struct dword7 {
613 unsigned int key_hi:16;
614 unsigned int key_mem:2;
615 unsigned int rsvd1:14;
616};
617
618struct ccp5_desc {
619 struct dword0 dw0;
620 __le32 length;
621 __le32 src_lo;
622 struct dword3 dw3;
623 union dword4 dw4;
624 union dword5 dw5;
625 __le32 key_lo;
626 struct dword7 dw7;
627};
628
629void ccp_add_device(struct ccp_device *ccp);
630void ccp_del_device(struct ccp_device *ccp);
631
632extern void ccp_log_error(struct ccp_device *, unsigned int);
633
634struct ccp_device *ccp_alloc_struct(struct sp_device *sp);
635bool ccp_queues_suspended(struct ccp_device *ccp);
636int ccp_cmd_queue_thread(void *data);
637int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
638
639int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
640
641int ccp_register_rng(struct ccp_device *ccp);
642void ccp_unregister_rng(struct ccp_device *ccp);
643int ccp_dmaengine_register(struct ccp_device *ccp);
644void ccp_dmaengine_unregister(struct ccp_device *ccp);
645
646void ccp5_debugfs_setup(struct ccp_device *ccp);
647void ccp5_debugfs_destroy(void);
648
649
650struct ccp_actions {
651 int (*aes)(struct ccp_op *);
652 int (*xts_aes)(struct ccp_op *);
653 int (*des3)(struct ccp_op *);
654 int (*sha)(struct ccp_op *);
655 int (*rsa)(struct ccp_op *);
656 int (*passthru)(struct ccp_op *);
657 int (*ecc)(struct ccp_op *);
658 u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
659 void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
660 unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
661 int (*init)(struct ccp_device *);
662 void (*destroy)(struct ccp_device *);
663 irqreturn_t (*irqhandler)(int, void *);
664};
665
666extern const struct ccp_vdata ccpv3_platform;
667extern const struct ccp_vdata ccpv3;
668extern const struct ccp_vdata ccpv5a;
669extern const struct ccp_vdata ccpv5b;
670
671#endif
672