1
2
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6
7#include <linux/crypto.h>
8#include <linux/moduleparam.h>
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/of.h>
15#include <linux/clk.h>
16#include <linux/of_address.h>
17
18#include "cc_driver.h"
19#include "cc_request_mgr.h"
20#include "cc_buffer_mgr.h"
21#include "cc_debugfs.h"
22#include "cc_cipher.h"
23#include "cc_aead.h"
24#include "cc_hash.h"
25#include "cc_ivgen.h"
26#include "cc_sram_mgr.h"
27#include "cc_pm.h"
28#include "cc_fips.h"
29
30bool cc_dump_desc;
31module_param_named(dump_desc, cc_dump_desc, bool, 0600);
32MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid");
33bool cc_dump_bytes;
34module_param_named(dump_bytes, cc_dump_bytes, bool, 0600);
35MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid");
36
37static bool cc_sec_disable;
38module_param_named(sec_disable, cc_sec_disable, bool, 0600);
39MODULE_PARM_DESC(cc_sec_disable, "Disable security functions");
40
41struct cc_hw_data {
42 char *name;
43 enum cc_hw_rev rev;
44 u32 sig;
45 u32 cidr_0123;
46 u32 pidr_0124;
47 int std_bodies;
48};
49
50#define CC_NUM_IDRS 4
51#define CC_HW_RESET_LOOP_COUNT 10
52
53
54static const u32 pidr_0124_offsets[CC_NUM_IDRS] = {
55 CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1),
56 CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4)
57};
58
59static const u32 cidr_0123_offsets[CC_NUM_IDRS] = {
60 CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1),
61 CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3)
62};
63
64
65
66
67static const struct cc_hw_data cc703_hw = {
68 .name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
69 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA
70};
71
72static const struct cc_hw_data cc713_hw = {
73 .name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
74 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL
75};
76
77static const struct cc_hw_data cc712_hw = {
78 .name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U,
79 .std_bodies = CC_STD_ALL
80};
81
82static const struct cc_hw_data cc710_hw = {
83 .name = "710", .rev = CC_HW_REV_710, .sig = 0xDCC63200U,
84 .std_bodies = CC_STD_ALL
85};
86
87static const struct cc_hw_data cc630p_hw = {
88 .name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U,
89 .std_bodies = CC_STD_ALL
90};
91
92static const struct of_device_id arm_ccree_dev_of_match[] = {
93 { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw },
94 { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw },
95 { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },
96 { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },
97 { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },
98 {}
99};
100MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);
101
102static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets)
103{
104 int i;
105 union {
106 u8 regs[CC_NUM_IDRS];
107 __le32 val;
108 } idr;
109
110 for (i = 0; i < CC_NUM_IDRS; ++i)
111 idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]);
112
113 return le32_to_cpu(idr.val);
114}
115
116void __dump_byte_array(const char *name, const u8 *buf, size_t len)
117{
118 char prefix[64];
119
120 if (!buf)
121 return;
122
123 snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len);
124
125 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf,
126 len, false);
127}
128
129static irqreturn_t cc_isr(int irq, void *dev_id)
130{
131 struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id;
132 struct device *dev = drvdata_to_dev(drvdata);
133 u32 irr;
134 u32 imr;
135
136
137
138 if (cc_pm_is_dev_suspended(dev))
139 return IRQ_NONE;
140
141
142 irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
143 dev_dbg(dev, "Got IRR=0x%08X\n", irr);
144
145 if (irr == 0)
146 return IRQ_NONE;
147
148 imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
149
150
151 cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);
152
153 drvdata->irq = irr;
154
155 if (irr & drvdata->comp_mask) {
156
157
158
159 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);
160 irr &= ~drvdata->comp_mask;
161 complete_request(drvdata);
162 }
163#ifdef CONFIG_CRYPTO_FIPS
164
165 if (irr & CC_GPR0_IRQ_MASK) {
166
167
168
169 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);
170 irr &= ~CC_GPR0_IRQ_MASK;
171 fips_handler(drvdata);
172 }
173#endif
174
175 if (irr & CC_AXI_ERR_IRQ_MASK) {
176 u32 axi_err;
177
178
179 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
180 dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",
181 axi_err);
182
183 irr &= ~CC_AXI_ERR_IRQ_MASK;
184 }
185
186 if (irr) {
187 dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n",
188 irr);
189
190 }
191
192 return IRQ_HANDLED;
193}
194
195bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata)
196{
197 unsigned int val;
198 unsigned int i;
199
200
201 if (drvdata->hw_rev <= CC_HW_REV_712)
202 return true;
203
204 for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
205
206
207
208 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));
209 if (val & CC_NVM_IS_IDLE_MASK) {
210
211 return true;
212 }
213
214 schedule();
215 }
216
217 return false;
218}
219
220int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
221{
222 unsigned int val, cache_params;
223 struct device *dev = drvdata_to_dev(drvdata);
224
225
226
227 if (drvdata->hw_rev <= CC_HW_REV_712) {
228 val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
229 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
230 dev_dbg(dev, "AXIM_CFG=0x%08X\n",
231 cc_ioread(drvdata, CC_REG(AXIM_CFG)));
232 }
233
234
235 val = cc_ioread(drvdata, CC_REG(HOST_IRR));
236 dev_dbg(dev, "IRR=0x%08X\n", val);
237 cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
238
239
240 val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK;
241
242 if (drvdata->hw_rev >= CC_HW_REV_712)
243 val |= CC_GPR0_IRQ_MASK;
244
245 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
246
247 cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
248
249 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
250
251 if (is_probe)
252 dev_dbg(dev, "Cache params previous: 0x%08X\n", val);
253
254 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
255 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
256
257 if (is_probe)
258 dev_dbg(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",
259 val, cache_params);
260
261 return 0;
262}
263
264static int init_cc_resources(struct platform_device *plat_dev)
265{
266 struct resource *req_mem_cc_regs = NULL;
267 struct cc_drvdata *new_drvdata;
268 struct device *dev = &plat_dev->dev;
269 struct device_node *np = dev->of_node;
270 u32 val, hw_rev_pidr, sig_cidr;
271 u64 dma_mask;
272 const struct cc_hw_data *hw_rev;
273 const struct of_device_id *dev_id;
274 struct clk *clk;
275 int rc = 0;
276
277 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
278 if (!new_drvdata)
279 return -ENOMEM;
280
281 dev_id = of_match_node(arm_ccree_dev_of_match, np);
282 if (!dev_id)
283 return -ENODEV;
284
285 hw_rev = (struct cc_hw_data *)dev_id->data;
286 new_drvdata->hw_rev_name = hw_rev->name;
287 new_drvdata->hw_rev = hw_rev->rev;
288 new_drvdata->std_bodies = hw_rev->std_bodies;
289
290 if (hw_rev->rev >= CC_HW_REV_712) {
291 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
292 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
293 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
294 } else {
295 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
296 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
297 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
298 }
299
300 new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
301
302 platform_set_drvdata(plat_dev, new_drvdata);
303 new_drvdata->plat_dev = plat_dev;
304
305 clk = devm_clk_get(dev, NULL);
306 if (IS_ERR(clk))
307 switch (PTR_ERR(clk)) {
308
309 case -ENOENT:
310 break;
311
312
313 case -EPROBE_DEFER:
314 return -EPROBE_DEFER;
315
316 default:
317 dev_err(dev, "Error getting clock: %ld\n",
318 PTR_ERR(clk));
319 return PTR_ERR(clk);
320 }
321 new_drvdata->clk = clk;
322
323 new_drvdata->coherent = of_dma_is_coherent(np);
324
325
326
327 req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
328
329 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
330 if (IS_ERR(new_drvdata->cc_base)) {
331 dev_err(dev, "Failed to ioremap registers");
332 return PTR_ERR(new_drvdata->cc_base);
333 }
334
335 dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
336 req_mem_cc_regs);
337 dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
338 &req_mem_cc_regs->start, new_drvdata->cc_base);
339
340
341 new_drvdata->irq = platform_get_irq(plat_dev, 0);
342 if (new_drvdata->irq < 0) {
343 dev_err(dev, "Failed getting IRQ resource\n");
344 return new_drvdata->irq;
345 }
346
347 init_completion(&new_drvdata->hw_queue_avail);
348
349 if (!plat_dev->dev.dma_mask)
350 plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask;
351
352 dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
353 while (dma_mask > 0x7fffffffUL) {
354 if (dma_supported(&plat_dev->dev, dma_mask)) {
355 rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask);
356 if (!rc)
357 break;
358 }
359 dma_mask >>= 1;
360 }
361
362 if (rc) {
363 dev_err(dev, "Failed in dma_set_mask, mask=%llx\n", dma_mask);
364 return rc;
365 }
366
367 rc = cc_clk_on(new_drvdata);
368 if (rc) {
369 dev_err(dev, "Failed to enable clock");
370 return rc;
371 }
372
373 new_drvdata->sec_disabled = cc_sec_disable;
374
375
376 if (!cc_wait_for_reset_completion(new_drvdata)) {
377 dev_err(dev, "Cryptocell reset not completed");
378 }
379
380 if (hw_rev->rev <= CC_HW_REV_712) {
381
382 val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
383 if (val != hw_rev->sig) {
384 dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
385 val, hw_rev->sig);
386 rc = -EINVAL;
387 goto post_clk_err;
388 }
389 sig_cidr = val;
390 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);
391 } else {
392
393 val = cc_read_idr(new_drvdata, pidr_0124_offsets);
394 if (val != hw_rev->pidr_0124) {
395 dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n",
396 val, hw_rev->pidr_0124);
397 rc = -EINVAL;
398 goto post_clk_err;
399 }
400 hw_rev_pidr = val;
401
402 val = cc_read_idr(new_drvdata, cidr_0123_offsets);
403 if (val != hw_rev->cidr_0123) {
404 dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n",
405 val, hw_rev->cidr_0123);
406 rc = -EINVAL;
407 goto post_clk_err;
408 }
409 sig_cidr = val;
410
411
412 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
413 switch (val) {
414 case CC_PINS_FULL:
415
416 break;
417 case CC_PINS_SLIM:
418 if (new_drvdata->std_bodies & CC_STD_NIST) {
419 dev_warn(dev, "703 mode forced due to HW configuration.\n");
420 new_drvdata->std_bodies = CC_STD_OSCCA;
421 }
422 break;
423 default:
424 dev_err(dev, "Unsupported engines configration.\n");
425 rc = -EINVAL;
426 goto post_clk_err;
427 }
428
429
430 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
431 val &= CC_SECURITY_DISABLED_MASK;
432 new_drvdata->sec_disabled |= !!val;
433
434 if (!new_drvdata->sec_disabled) {
435 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
436 if (new_drvdata->std_bodies & CC_STD_NIST)
437 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
438 }
439 }
440
441 if (new_drvdata->sec_disabled)
442 dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n");
443
444
445 dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n",
446 hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION);
447
448 rc = devm_request_irq(dev, new_drvdata->irq, cc_isr,
449 IRQF_SHARED, "ccree", new_drvdata);
450 if (rc) {
451 dev_err(dev, "Could not register to interrupt %d\n",
452 new_drvdata->irq);
453 goto post_clk_err;
454 }
455 dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);
456
457 rc = init_cc_regs(new_drvdata, true);
458 if (rc) {
459 dev_err(dev, "init_cc_regs failed\n");
460 goto post_clk_err;
461 }
462
463 rc = cc_debugfs_init(new_drvdata);
464 if (rc) {
465 dev_err(dev, "Failed registering debugfs interface\n");
466 goto post_regs_err;
467 }
468
469 rc = cc_fips_init(new_drvdata);
470 if (rc) {
471 dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc);
472 goto post_debugfs_err;
473 }
474 rc = cc_sram_mgr_init(new_drvdata);
475 if (rc) {
476 dev_err(dev, "cc_sram_mgr_init failed\n");
477 goto post_fips_init_err;
478 }
479
480 new_drvdata->mlli_sram_addr =
481 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
482 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
483 dev_err(dev, "Failed to alloc MLLI Sram buffer\n");
484 rc = -ENOMEM;
485 goto post_sram_mgr_err;
486 }
487
488 rc = cc_req_mgr_init(new_drvdata);
489 if (rc) {
490 dev_err(dev, "cc_req_mgr_init failed\n");
491 goto post_sram_mgr_err;
492 }
493
494 rc = cc_buffer_mgr_init(new_drvdata);
495 if (rc) {
496 dev_err(dev, "buffer_mgr_init failed\n");
497 goto post_req_mgr_err;
498 }
499
500 rc = cc_pm_init(new_drvdata);
501 if (rc) {
502 dev_err(dev, "ssi_power_mgr_init failed\n");
503 goto post_buf_mgr_err;
504 }
505
506 rc = cc_ivgen_init(new_drvdata);
507 if (rc) {
508 dev_err(dev, "cc_ivgen_init failed\n");
509 goto post_buf_mgr_err;
510 }
511
512
513 rc = cc_cipher_alloc(new_drvdata);
514 if (rc) {
515 dev_err(dev, "cc_cipher_alloc failed\n");
516 goto post_ivgen_err;
517 }
518
519
520 rc = cc_hash_alloc(new_drvdata);
521 if (rc) {
522 dev_err(dev, "cc_hash_alloc failed\n");
523 goto post_cipher_err;
524 }
525
526 rc = cc_aead_alloc(new_drvdata);
527 if (rc) {
528 dev_err(dev, "cc_aead_alloc failed\n");
529 goto post_hash_err;
530 }
531
532
533 cc_pm_go(new_drvdata);
534
535
536
537
538
539 cc_set_ree_fips_status(new_drvdata, true);
540
541 return 0;
542
543post_hash_err:
544 cc_hash_free(new_drvdata);
545post_cipher_err:
546 cc_cipher_free(new_drvdata);
547post_ivgen_err:
548 cc_ivgen_fini(new_drvdata);
549post_buf_mgr_err:
550 cc_buffer_mgr_fini(new_drvdata);
551post_req_mgr_err:
552 cc_req_mgr_fini(new_drvdata);
553post_sram_mgr_err:
554 cc_sram_mgr_fini(new_drvdata);
555post_fips_init_err:
556 cc_fips_fini(new_drvdata);
557post_debugfs_err:
558 cc_debugfs_fini(new_drvdata);
559post_regs_err:
560 fini_cc_regs(new_drvdata);
561post_clk_err:
562 cc_clk_off(new_drvdata);
563 return rc;
564}
565
566void fini_cc_regs(struct cc_drvdata *drvdata)
567{
568
569 cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);
570}
571
572static void cleanup_cc_resources(struct platform_device *plat_dev)
573{
574 struct cc_drvdata *drvdata =
575 (struct cc_drvdata *)platform_get_drvdata(plat_dev);
576
577 cc_aead_free(drvdata);
578 cc_hash_free(drvdata);
579 cc_cipher_free(drvdata);
580 cc_ivgen_fini(drvdata);
581 cc_pm_fini(drvdata);
582 cc_buffer_mgr_fini(drvdata);
583 cc_req_mgr_fini(drvdata);
584 cc_sram_mgr_fini(drvdata);
585 cc_fips_fini(drvdata);
586 cc_debugfs_fini(drvdata);
587 fini_cc_regs(drvdata);
588 cc_clk_off(drvdata);
589}
590
591int cc_clk_on(struct cc_drvdata *drvdata)
592{
593 struct clk *clk = drvdata->clk;
594 int rc;
595
596 if (IS_ERR(clk))
597
598 return 0;
599
600 rc = clk_prepare_enable(clk);
601 if (rc)
602 return rc;
603
604 return 0;
605}
606
607unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata)
608{
609 if (drvdata->hw_rev >= CC_HW_REV_712)
610 return HASH_LEN_SIZE_712;
611 else
612 return HASH_LEN_SIZE_630;
613}
614
615void cc_clk_off(struct cc_drvdata *drvdata)
616{
617 struct clk *clk = drvdata->clk;
618
619 if (IS_ERR(clk))
620
621 return;
622
623 clk_disable_unprepare(clk);
624}
625
626static int ccree_probe(struct platform_device *plat_dev)
627{
628 int rc;
629 struct device *dev = &plat_dev->dev;
630
631
632 rc = init_cc_resources(plat_dev);
633 if (rc)
634 return rc;
635
636 dev_info(dev, "ARM ccree device initialized\n");
637
638 return 0;
639}
640
641static int ccree_remove(struct platform_device *plat_dev)
642{
643 struct device *dev = &plat_dev->dev;
644
645 dev_dbg(dev, "Releasing ccree resources...\n");
646
647 cleanup_cc_resources(plat_dev);
648
649 dev_info(dev, "ARM ccree device terminated\n");
650
651 return 0;
652}
653
654static struct platform_driver ccree_driver = {
655 .driver = {
656 .name = "ccree",
657 .of_match_table = arm_ccree_dev_of_match,
658#ifdef CONFIG_PM
659 .pm = &ccree_pm,
660#endif
661 },
662 .probe = ccree_probe,
663 .remove = ccree_remove,
664};
665
666static int __init ccree_init(void)
667{
668 cc_hash_global_init();
669 cc_debugfs_global_init();
670
671 return platform_driver_register(&ccree_driver);
672}
673module_init(ccree_init);
674
675static void __exit ccree_exit(void)
676{
677 platform_driver_unregister(&ccree_driver);
678 cc_debugfs_global_fini();
679}
680module_exit(ccree_exit);
681
682
683MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver");
684MODULE_VERSION(DRV_MODULE_VERSION);
685MODULE_AUTHOR("ARM");
686MODULE_LICENSE("GPL v2");
687
