LXR linux/drivers/dma/at_hdmac

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Header file for the Atmel AHB DMA Controller driver
   4 *
   5 * Copyright (C) 2008 Atmel Corporation
   6 */
   7#ifndef AT_HDMAC_REGS_H
   8#define AT_HDMAC_REGS_H
   9
  10#include <linux/platform_data/dma-atmel.h>
  11
  12#define AT_DMA_MAX_NR_CHANNELS  8
  13
  14
  15#define AT_DMA_GCFG     0x00    /* Global Configuration Register */
  16#define         AT_DMA_IF_BIGEND(i)     (0x1 << (i))    /* AHB-Lite Interface i in Big-endian mode */
  17#define         AT_DMA_ARB_CFG  (0x1 << 4)      /* Arbiter mode. */
  18#define                 AT_DMA_ARB_CFG_FIXED            (0x0 << 4)
  19#define                 AT_DMA_ARB_CFG_ROUND_ROBIN      (0x1 << 4)
  20
  21#define AT_DMA_EN       0x04    /* Controller Enable Register */
  22#define         AT_DMA_ENABLE   (0x1 << 0)
  23
  24#define AT_DMA_SREQ     0x08    /* Software Single Request Register */
  25#define         AT_DMA_SSREQ(x) (0x1 << ((x) << 1))             /* Request a source single transfer on channel x */
  26#define         AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1)))       /* Request a destination single transfer on channel x */
  27
  28#define AT_DMA_CREQ     0x0C    /* Software Chunk Transfer Request Register */
  29#define         AT_DMA_SCREQ(x) (0x1 << ((x) << 1))             /* Request a source chunk transfer on channel x */
  30#define         AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1)))       /* Request a destination chunk transfer on channel x */
  31
  32#define AT_DMA_LAST     0x10    /* Software Last Transfer Flag Register */
  33#define         AT_DMA_SLAST(x) (0x1 << ((x) << 1))             /* This src rq is last tx of buffer on channel x */
  34#define         AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1)))       /* This dst rq is last tx of buffer on channel x */
  35
  36#define AT_DMA_SYNC     0x14    /* Request Synchronization Register */
  37#define         AT_DMA_SYR(h)   (0x1 << (h))                    /* Synchronize handshake line h */
  38
  39/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
  40#define AT_DMA_EBCIER   0x18    /* Enable register */
  41#define AT_DMA_EBCIDR   0x1C    /* Disable register */
  42#define AT_DMA_EBCIMR   0x20    /* Mask Register */
  43#define AT_DMA_EBCISR   0x24    /* Status Register */
  44#define         AT_DMA_CBTC_OFFSET      8
  45#define         AT_DMA_ERR_OFFSET       16
  46#define         AT_DMA_BTC(x)   (0x1 << (x))
  47#define         AT_DMA_CBTC(x)  (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
  48#define         AT_DMA_ERR(x)   (0x1 << (AT_DMA_ERR_OFFSET + (x)))
  49
  50#define AT_DMA_CHER     0x28    /* Channel Handler Enable Register */
  51#define         AT_DMA_ENA(x)   (0x1 << (x))
  52#define         AT_DMA_SUSP(x)  (0x1 << ( 8 + (x)))
  53#define         AT_DMA_KEEP(x)  (0x1 << (24 + (x)))
  54
  55#define AT_DMA_CHDR     0x2C    /* Channel Handler Disable Register */
  56#define         AT_DMA_DIS(x)   (0x1 << (x))
  57#define         AT_DMA_RES(x)   (0x1 << ( 8 + (x)))
  58
  59#define AT_DMA_CHSR     0x30    /* Channel Handler Status Register */
  60#define         AT_DMA_EMPT(x)  (0x1 << (16 + (x)))
  61#define         AT_DMA_STAL(x)  (0x1 << (24 + (x)))
  62
  63
  64#define AT_DMA_CH_REGS_BASE     0x3C    /* Channel registers base address */
  65#define ch_regs(x)      (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
  66
  67/* Hardware register offset for each channel */
  68#define ATC_SADDR_OFFSET        0x00    /* Source Address Register */
  69#define ATC_DADDR_OFFSET        0x04    /* Destination Address Register */
  70#define ATC_DSCR_OFFSET         0x08    /* Descriptor Address Register */
  71#define ATC_CTRLA_OFFSET        0x0C    /* Control A Register */
  72#define ATC_CTRLB_OFFSET        0x10    /* Control B Register */
  73#define ATC_CFG_OFFSET          0x14    /* Configuration Register */
  74#define ATC_SPIP_OFFSET         0x18    /* Src PIP Configuration Register */
  75#define ATC_DPIP_OFFSET         0x1C    /* Dst PIP Configuration Register */
  76
  77
  78/* Bitfield definitions */
  79
  80/* Bitfields in DSCR */
  81#define ATC_DSCR_IF(i)          (0x3 & (i))     /* Dsc feched via AHB-Lite Interface i */
  82
  83/* Bitfields in CTRLA */
  84#define ATC_BTSIZE_MAX          0xFFFFUL        /* Maximum Buffer Transfer Size */
  85#define ATC_BTSIZE(x)           (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
  86#define ATC_SCSIZE_MASK         (0x7 << 16)     /* Source Chunk Transfer Size */
  87#define         ATC_SCSIZE(x)           (ATC_SCSIZE_MASK & ((x) << 16))
  88#define         ATC_SCSIZE_1            (0x0 << 16)
  89#define         ATC_SCSIZE_4            (0x1 << 16)
  90#define         ATC_SCSIZE_8            (0x2 << 16)
  91#define         ATC_SCSIZE_16           (0x3 << 16)
  92#define         ATC_SCSIZE_32           (0x4 << 16)
  93#define         ATC_SCSIZE_64           (0x5 << 16)
  94#define         ATC_SCSIZE_128          (0x6 << 16)
  95#define         ATC_SCSIZE_256          (0x7 << 16)
  96#define ATC_DCSIZE_MASK         (0x7 << 20)     /* Destination Chunk Transfer Size */
  97#define         ATC_DCSIZE(x)           (ATC_DCSIZE_MASK & ((x) << 20))
  98#define         ATC_DCSIZE_1            (0x0 << 20)
  99#define         ATC_DCSIZE_4            (0x1 << 20)
 100#define         ATC_DCSIZE_8            (0x2 << 20)
 101#define         ATC_DCSIZE_16           (0x3 << 20)
 102#define         ATC_DCSIZE_32           (0x4 << 20)
 103#define         ATC_DCSIZE_64           (0x5 << 20)
 104#define         ATC_DCSIZE_128          (0x6 << 20)
 105#define         ATC_DCSIZE_256          (0x7 << 20)
 106#define ATC_SRC_WIDTH_MASK      (0x3 << 24)     /* Source Single Transfer Size */
 107#define         ATC_SRC_WIDTH(x)        ((x) << 24)
 108#define         ATC_SRC_WIDTH_BYTE      (0x0 << 24)
 109#define         ATC_SRC_WIDTH_HALFWORD  (0x1 << 24)
 110#define         ATC_SRC_WIDTH_WORD      (0x2 << 24)
 111#define         ATC_REG_TO_SRC_WIDTH(r) (((r) >> 24) & 0x3)
 112#define ATC_DST_WIDTH_MASK      (0x3 << 28)     /* Destination Single Transfer Size */
 113#define         ATC_DST_WIDTH(x)        ((x) << 28)
 114#define         ATC_DST_WIDTH_BYTE      (0x0 << 28)
 115#define         ATC_DST_WIDTH_HALFWORD  (0x1 << 28)
 116#define         ATC_DST_WIDTH_WORD      (0x2 << 28)
 117#define ATC_DONE                (0x1 << 31)     /* Tx Done (only written back in descriptor) */
 118
 119/* Bitfields in CTRLB */
 120#define ATC_SIF(i)              (0x3 & (i))     /* Src tx done via AHB-Lite Interface i */
 121#define ATC_DIF(i)              ((0x3 & (i)) <<  4)     /* Dst tx done via AHB-Lite Interface i */
 122                                  /* Specify AHB interfaces */
 123#define AT_DMA_MEM_IF           0 /* interface 0 as memory interface */
 124#define AT_DMA_PER_IF           1 /* interface 1 as peripheral interface */
 125
 126#define ATC_SRC_PIP             (0x1 <<  8)     /* Source Picture-in-Picture enabled */
 127#define ATC_DST_PIP             (0x1 << 12)     /* Destination Picture-in-Picture enabled */
 128#define ATC_SRC_DSCR_DIS        (0x1 << 16)     /* Src Descriptor fetch disable */
 129#define ATC_DST_DSCR_DIS        (0x1 << 20)     /* Dst Descriptor fetch disable */
 130#define ATC_FC_MASK             (0x7 << 21)     /* Choose Flow Controller */
 131#define         ATC_FC_MEM2MEM          (0x0 << 21)     /* Mem-to-Mem (DMA) */
 132#define         ATC_FC_MEM2PER          (0x1 << 21)     /* Mem-to-Periph (DMA) */
 133#define         ATC_FC_PER2MEM          (0x2 << 21)     /* Periph-to-Mem (DMA) */
 134#define         ATC_FC_PER2PER          (0x3 << 21)     /* Periph-to-Periph (DMA) */
 135#define         ATC_FC_PER2MEM_PER      (0x4 << 21)     /* Periph-to-Mem (Peripheral) */
 136#define         ATC_FC_MEM2PER_PER      (0x5 << 21)     /* Mem-to-Periph (Peripheral) */
 137#define         ATC_FC_PER2PER_SRCPER   (0x6 << 21)     /* Periph-to-Periph (Src Peripheral) */
 138#define         ATC_FC_PER2PER_DSTPER   (0x7 << 21)     /* Periph-to-Periph (Dst Peripheral) */
 139#define ATC_SRC_ADDR_MODE_MASK  (0x3 << 24)
 140#define         ATC_SRC_ADDR_MODE_INCR  (0x0 << 24)     /* Incrementing Mode */
 141#define         ATC_SRC_ADDR_MODE_DECR  (0x1 << 24)     /* Decrementing Mode */
 142#define         ATC_SRC_ADDR_MODE_FIXED (0x2 << 24)     /* Fixed Mode */
 143#define ATC_DST_ADDR_MODE_MASK  (0x3 << 28)
 144#define         ATC_DST_ADDR_MODE_INCR  (0x0 << 28)     /* Incrementing Mode */
 145#define         ATC_DST_ADDR_MODE_DECR  (0x1 << 28)     /* Decrementing Mode */
 146#define         ATC_DST_ADDR_MODE_FIXED (0x2 << 28)     /* Fixed Mode */
 147#define ATC_IEN                 (0x1 << 30)     /* BTC interrupt enable (active low) */
 148#define ATC_AUTO                (0x1 << 31)     /* Auto multiple buffer tx enable */
 149
 150/* Bitfields in CFG */
 151/* are in at_hdmac.h */
 152
 153/* Bitfields in SPIP */
 154#define ATC_SPIP_HOLE(x)        (0xFFFFU & (x))
 155#define ATC_SPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
 156
 157/* Bitfields in DPIP */
 158#define ATC_DPIP_HOLE(x)        (0xFFFFU & (x))
 159#define ATC_DPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
 160
 161
 162/*--  descriptors  -----------------------------------------------------*/
 163
 164/* LLI == Linked List Item; aka DMA buffer descriptor */
 165struct at_lli {
 166        /* values that are not changed by hardware */
 167        dma_addr_t      saddr;
 168        dma_addr_t      daddr;
 169        /* value that may get written back: */
 170        u32             ctrla;
 171        /* more values that are not changed by hardware */
 172        u32             ctrlb;
 173        dma_addr_t      dscr;   /* chain to next lli */
 174};
 175
 176/**
 177 * struct at_desc - software descriptor
 178 * @at_lli: hardware lli structure
 179 * @txd: support for the async_tx api
 180 * @desc_node: node on the channed descriptors list
 181 * @len: descriptor byte count
 182 * @total_len: total transaction byte count
 183 */
 184struct at_desc {
 185        /* FIRST values the hardware uses */
 186        struct at_lli                   lli;
 187
 188        /* THEN values for driver housekeeping */
 189        struct list_head                tx_list;
 190        struct dma_async_tx_descriptor  txd;
 191        struct list_head                desc_node;
 192        size_t                          len;
 193        size_t                          total_len;
 194
 195        /* Interleaved data */
 196        size_t                          boundary;
 197        size_t                          dst_hole;
 198        size_t                          src_hole;
 199
 200        /* Memset temporary buffer */
 201        bool                            memset_buffer;
 202        dma_addr_t                      memset_paddr;
 203        int                             *memset_vaddr;
 204};
 205
 206static inline struct at_desc *
 207txd_to_at_desc(struct dma_async_tx_descriptor *txd)
 208{
 209        return container_of(txd, struct at_desc, txd);
 210}
 211
 212
 213/*--  Channels  --------------------------------------------------------*/
 214
 215/**
 216 * atc_status - information bits stored in channel status flag
 217 *
 218 * Manipulated with atomic operations.
 219 */
 220enum atc_status {
 221        ATC_IS_ERROR = 0,
 222        ATC_IS_PAUSED = 1,
 223        ATC_IS_CYCLIC = 24,
 224};
 225
 226/**
 227 * struct at_dma_chan - internal representation of an Atmel HDMAC channel
 228 * @chan_common: common dmaengine channel object members
 229 * @device: parent device
 230 * @ch_regs: memory mapped register base
 231 * @mask: channel index in a mask
 232 * @per_if: peripheral interface
 233 * @mem_if: memory interface
 234 * @status: transmit status information from irq/prep* functions
 235 *                to tasklet (use atomic operations)
 236 * @tasklet: bottom half to finish transaction work
 237 * @save_cfg: configuration register that is saved on suspend/resume cycle
 238 * @save_dscr: for cyclic operations, preserve next descriptor address in
 239 *             the cyclic list on suspend/resume cycle
 240 * @dma_sconfig: configuration for slave transfers, passed via
 241 * .device_config
 242 * @lock: serializes enqueue/dequeue operations to descriptors lists
 243 * @active_list: list of descriptors dmaengine is being running on
 244 * @queue: list of descriptors ready to be submitted to engine
 245 * @free_list: list of descriptors usable by the channel
 246 * @descs_allocated: records the actual size of the descriptor pool
 247 */
 248struct at_dma_chan {
 249        struct dma_chan         chan_common;
 250        struct at_dma           *device;
 251        void __iomem            *ch_regs;
 252        u8                      mask;
 253        u8                      per_if;
 254        u8                      mem_if;
 255        unsigned long           status;
 256        struct tasklet_struct   tasklet;
 257        u32                     save_cfg;
 258        u32                     save_dscr;
 259        struct dma_slave_config dma_sconfig;
 260
 261        spinlock_t              lock;
 262
 263        /* these other elements are all protected by lock */
 264        struct list_head        active_list;
 265        struct list_head        queue;
 266        struct list_head        free_list;
 267        unsigned int            descs_allocated;
 268};
 269
 270#define channel_readl(atchan, name) \
 271        __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
 272
 273#define channel_writel(atchan, name, val) \
 274        __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
 275
 276static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
 277{
 278        return container_of(dchan, struct at_dma_chan, chan_common);
 279}
 280
 281/*
 282 * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
 283 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
 284 *
 285 * This can be done by finding most significant bit set.
 286 */
 287static inline void convert_burst(u32 *maxburst)
 288{
 289        if (*maxburst > 1)
 290                *maxburst = fls(*maxburst) - 2;
 291        else
 292                *maxburst = 0;
 293}
 294
 295/*
 296 * Fix sconfig's bus width according to at_hdmac.
 297 * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
 298 */
 299static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
 300{
 301        switch (addr_width) {
 302        case DMA_SLAVE_BUSWIDTH_2_BYTES:
 303                return 1;
 304        case DMA_SLAVE_BUSWIDTH_4_BYTES:
 305                return 2;
 306        default:
 307                /* For 1 byte width or fallback */
 308                return 0;
 309        }
 310}
 311
 312/*--  Controller  ------------------------------------------------------*/
 313
 314/**
 315 * struct at_dma - internal representation of an Atmel HDMA Controller
 316 * @chan_common: common dmaengine dma_device object members
 317 * @atdma_devtype: identifier of DMA controller compatibility
 318 * @ch_regs: memory mapped register base
 319 * @clk: dma controller clock
 320 * @save_imr: interrupt mask register that is saved on suspend/resume cycle
 321 * @all_chan_mask: all channels availlable in a mask
 322 * @dma_desc_pool: base of DMA descriptor region (DMA address)
 323 * @chan: channels table to store at_dma_chan structures
 324 */
 325struct at_dma {
 326        struct dma_device       dma_common;
 327        void __iomem            *regs;
 328        struct clk              *clk;
 329        u32                     save_imr;
 330
 331        u8                      all_chan_mask;
 332
 333        struct dma_pool         *dma_desc_pool;
 334        struct dma_pool         *memset_pool;
 335        /* AT THE END channels table */
 336        struct at_dma_chan      chan[0];
 337};
 338
 339#define dma_readl(atdma, name) \
 340        __raw_readl((atdma)->regs + AT_DMA_##name)
 341#define dma_writel(atdma, name, val) \
 342        __raw_writel((val), (atdma)->regs + AT_DMA_##name)
 343
 344static inline struct at_dma *to_at_dma(struct dma_device *ddev)
 345{
 346        return container_of(ddev, struct at_dma, dma_common);
 347}
 348
 349
 350/*--  Helper functions  ------------------------------------------------*/
 351
 352static struct device *chan2dev(struct dma_chan *chan)
 353{
 354        return &chan->dev->device;
 355}
 356
 357#if defined(VERBOSE_DEBUG)
 358static void vdbg_dump_regs(struct at_dma_chan *atchan)
 359{
 360        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
 361
 362        dev_err(chan2dev(&atchan->chan_common),
 363                "  channel %d : imr = 0x%x, chsr = 0x%x\n",
 364                atchan->chan_common.chan_id,
 365                dma_readl(atdma, EBCIMR),
 366                dma_readl(atdma, CHSR));
 367
 368        dev_err(chan2dev(&atchan->chan_common),
 369                "  channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
 370                channel_readl(atchan, SADDR),
 371                channel_readl(atchan, DADDR),
 372                channel_readl(atchan, CTRLA),
 373                channel_readl(atchan, CTRLB),
 374                channel_readl(atchan, CFG),
 375                channel_readl(atchan, DSCR));
 376}
 377#else
 378static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
 379#endif
 380
 381static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
 382{
 383        dev_crit(chan2dev(&atchan->chan_common),
 384                 "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
 385                 &lli->saddr, &lli->daddr,
 386                 lli->ctrla, lli->ctrlb, &lli->dscr);
 387}
 388
 389
 390static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
 391{
 392        u32 ebci;
 393
 394        /* enable interrupts on buffer transfer completion & error */
 395        ebci =    AT_DMA_BTC(chan_id)
 396                | AT_DMA_ERR(chan_id);
 397        if (on)
 398                dma_writel(atdma, EBCIER, ebci);
 399        else
 400                dma_writel(atdma, EBCIDR, ebci);
 401}
 402
 403static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
 404{
 405        atc_setup_irq(atdma, chan_id, 1);
 406}
 407
 408static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
 409{
 410        atc_setup_irq(atdma, chan_id, 0);
 411}
 412
 413
 414/**
 415 * atc_chan_is_enabled - test if given channel is enabled
 416 * @atchan: channel we want to test status
 417 */
 418static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
 419{
 420        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
 421
 422        return !!(dma_readl(atdma, CHSR) & atchan->mask);
 423}
 424
 425/**
 426 * atc_chan_is_paused - test channel pause/resume status
 427 * @atchan: channel we want to test status
 428 */
 429static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
 430{
 431        return test_bit(ATC_IS_PAUSED, &atchan->status);
 432}
 433
 434/**
 435 * atc_chan_is_cyclic - test if given channel has cyclic property set
 436 * @atchan: channel we want to test status
 437 */
 438static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
 439{
 440        return test_bit(ATC_IS_CYCLIC, &atchan->status);
 441}
 442
 443/**
 444 * set_desc_eol - set end-of-link to descriptor so it will end transfer
 445 * @desc: descriptor, signle or at the end of a chain, to end chain on
 446 */
 447static void set_desc_eol(struct at_desc *desc)
 448{
 449        u32 ctrlb = desc->lli.ctrlb;
 450
 451        ctrlb &= ~ATC_IEN;
 452        ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
 453
 454        desc->lli.ctrlb = ctrlb;
 455        desc->lli.dscr = 0;
 456}
 457
 458#endif /* AT_HDMAC_REGS_H */
 459