LXR linux/drivers/dma/dw-edma/dw-edma-core.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
   4 * Synopsys DesignWare eDMA core driver
   5 *
   6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
   7 */
   8
   9#ifndef _DW_EDMA_CORE_H
  10#define _DW_EDMA_CORE_H
  11
  12#include <linux/msi.h>
  13#include <linux/dma/edma.h>
  14
  15#include "../virt-dma.h"
  16
  17#define EDMA_LL_SZ                                      24
  18
  19enum dw_edma_dir {
  20        EDMA_DIR_WRITE = 0,
  21        EDMA_DIR_READ
  22};
  23
  24enum dw_edma_mode {
  25        EDMA_MODE_LEGACY = 0,
  26        EDMA_MODE_UNROLL
  27};
  28
  29enum dw_edma_request {
  30        EDMA_REQ_NONE = 0,
  31        EDMA_REQ_STOP,
  32        EDMA_REQ_PAUSE
  33};
  34
  35enum dw_edma_status {
  36        EDMA_ST_IDLE = 0,
  37        EDMA_ST_PAUSE,
  38        EDMA_ST_BUSY
  39};
  40
  41struct dw_edma_chan;
  42struct dw_edma_chunk;
  43
  44struct dw_edma_burst {
  45        struct list_head                list;
  46        u64                             sar;
  47        u64                             dar;
  48        u32                             sz;
  49};
  50
  51struct dw_edma_region {
  52        phys_addr_t                     paddr;
  53        void                            __iomem *vaddr;
  54        size_t                          sz;
  55};
  56
  57struct dw_edma_chunk {
  58        struct list_head                list;
  59        struct dw_edma_chan             *chan;
  60        struct dw_edma_burst            *burst;
  61
  62        u32                             bursts_alloc;
  63
  64        u8                              cb;
  65        struct dw_edma_region           ll_region;      /* Linked list */
  66};
  67
  68struct dw_edma_desc {
  69        struct virt_dma_desc            vd;
  70        struct dw_edma_chan             *chan;
  71        struct dw_edma_chunk            *chunk;
  72
  73        u32                             chunks_alloc;
  74
  75        u32                             alloc_sz;
  76        u32                             xfer_sz;
  77};
  78
  79struct dw_edma_chan {
  80        struct virt_dma_chan            vc;
  81        struct dw_edma_chip             *chip;
  82        int                             id;
  83        enum dw_edma_dir                dir;
  84
  85        off_t                           ll_off;
  86        u32                             ll_max;
  87
  88        off_t                           dt_off;
  89
  90        struct msi_msg                  msi;
  91
  92        enum dw_edma_request            request;
  93        enum dw_edma_status             status;
  94        u8                              configured;
  95
  96        struct dma_slave_config         config;
  97};
  98
  99struct dw_edma_irq {
 100        struct msi_msg                  msi;
 101        u32                             wr_mask;
 102        u32                             rd_mask;
 103        struct dw_edma                  *dw;
 104};
 105
 106struct dw_edma {
 107        char                            name[20];
 108
 109        struct dma_device               wr_edma;
 110        u16                             wr_ch_cnt;
 111
 112        struct dma_device               rd_edma;
 113        u16                             rd_ch_cnt;
 114
 115        struct dw_edma_region           rg_region;      /* Registers */
 116        struct dw_edma_region           ll_region;      /* Linked list */
 117        struct dw_edma_region           dt_region;      /* Data */
 118
 119        struct dw_edma_irq              *irq;
 120        int                             nr_irqs;
 121
 122        u32                             version;
 123        enum dw_edma_mode               mode;
 124
 125        struct dw_edma_chan             *chan;
 126        const struct dw_edma_core_ops   *ops;
 127
 128        raw_spinlock_t                  lock;           /* Only for legacy */
 129};
 130
 131struct dw_edma_sg {
 132        struct scatterlist              *sgl;
 133        unsigned int                    len;
 134};
 135
 136struct dw_edma_cyclic {
 137        dma_addr_t                      paddr;
 138        size_t                          len;
 139        size_t                          cnt;
 140};
 141
 142struct dw_edma_transfer {
 143        struct dma_chan                 *dchan;
 144        union dw_edma_xfer {
 145                struct dw_edma_sg       sg;
 146                struct dw_edma_cyclic   cyclic;
 147        } xfer;
 148        enum dma_transfer_direction     direction;
 149        unsigned long                   flags;
 150        bool                            cyclic;
 151};
 152
 153static inline
 154struct dw_edma_chan *vc2dw_edma_chan(struct virt_dma_chan *vc)
 155{
 156        return container_of(vc, struct dw_edma_chan, vc);
 157}
 158
 159static inline
 160struct dw_edma_chan *dchan2dw_edma_chan(struct dma_chan *dchan)
 161{
 162        return vc2dw_edma_chan(to_virt_chan(dchan));
 163}
 164
 165#endif /* _DW_EDMA_CORE_H */
 166