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8#include <linux/dmaengine.h>
9#include <linux/acpi.h>
10#include <linux/of.h>
11#include <linux/property.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/module.h>
16#include <linux/uaccess.h>
17#include <linux/slab.h>
18#include <linux/pm_runtime.h>
19#include <linux/bitops.h>
20#include <linux/dma-mapping.h>
21
22#include "hidma_mgmt.h"
23
24#define HIDMA_QOS_N_OFFSET 0x700
25#define HIDMA_CFG_OFFSET 0x400
26#define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C
27#define HIDMA_MAX_XACTIONS_OFFSET 0x420
28#define HIDMA_HW_VERSION_OFFSET 0x424
29#define HIDMA_CHRESET_TIMEOUT_OFFSET 0x418
30
31#define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0)
32#define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0)
33#define HIDMA_WEIGHT_MASK GENMASK(6, 0)
34#define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0)
35#define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0)
36
37#define HIDMA_MAX_WR_XACTIONS_BIT_POS 16
38#define HIDMA_MAX_BUS_WR_REQ_BIT_POS 16
39#define HIDMA_WRR_BIT_POS 8
40#define HIDMA_PRIORITY_BIT_POS 15
41
42#define HIDMA_AUTOSUSPEND_TIMEOUT 2000
43#define HIDMA_MAX_CHANNEL_WEIGHT 15
44
45static unsigned int max_write_request;
46module_param(max_write_request, uint, 0644);
47MODULE_PARM_DESC(max_write_request,
48 "maximum write burst (default: ACPI/DT value)");
49
50static unsigned int max_read_request;
51module_param(max_read_request, uint, 0644);
52MODULE_PARM_DESC(max_read_request,
53 "maximum read burst (default: ACPI/DT value)");
54
55static unsigned int max_wr_xactions;
56module_param(max_wr_xactions, uint, 0644);
57MODULE_PARM_DESC(max_wr_xactions,
58 "maximum number of write transactions (default: ACPI/DT value)");
59
60static unsigned int max_rd_xactions;
61module_param(max_rd_xactions, uint, 0644);
62MODULE_PARM_DESC(max_rd_xactions,
63 "maximum number of read transactions (default: ACPI/DT value)");
64
65int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
66{
67 unsigned int i;
68 u32 val;
69
70 if (!is_power_of_2(mgmtdev->max_write_request) ||
71 (mgmtdev->max_write_request < 128) ||
72 (mgmtdev->max_write_request > 1024)) {
73 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
74 mgmtdev->max_write_request);
75 return -EINVAL;
76 }
77
78 if (!is_power_of_2(mgmtdev->max_read_request) ||
79 (mgmtdev->max_read_request < 128) ||
80 (mgmtdev->max_read_request > 1024)) {
81 dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
82 mgmtdev->max_read_request);
83 return -EINVAL;
84 }
85
86 if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
87 dev_err(&mgmtdev->pdev->dev,
88 "max_wr_xactions cannot be bigger than %ld\n",
89 HIDMA_MAX_WR_XACTIONS_MASK);
90 return -EINVAL;
91 }
92
93 if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
94 dev_err(&mgmtdev->pdev->dev,
95 "max_rd_xactions cannot be bigger than %ld\n",
96 HIDMA_MAX_RD_XACTIONS_MASK);
97 return -EINVAL;
98 }
99
100 for (i = 0; i < mgmtdev->dma_channels; i++) {
101 if (mgmtdev->priority[i] > 1) {
102 dev_err(&mgmtdev->pdev->dev,
103 "priority can be 0 or 1\n");
104 return -EINVAL;
105 }
106
107 if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
108 dev_err(&mgmtdev->pdev->dev,
109 "max value of weight can be %d.\n",
110 HIDMA_MAX_CHANNEL_WEIGHT);
111 return -EINVAL;
112 }
113
114
115 if (mgmtdev->weight[i] == 0)
116 mgmtdev->weight[i] = 1;
117 }
118
119 pm_runtime_get_sync(&mgmtdev->pdev->dev);
120 val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
121 val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
122 val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
123 val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
124 val |= mgmtdev->max_read_request;
125 writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
126
127 val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
128 val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
129 val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
130 val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
131 val |= mgmtdev->max_rd_xactions;
132 writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
133
134 mgmtdev->hw_version =
135 readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
136 mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
137 mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
138
139 for (i = 0; i < mgmtdev->dma_channels; i++) {
140 u32 weight = mgmtdev->weight[i];
141 u32 priority = mgmtdev->priority[i];
142
143 val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
144 val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
145 val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
146 val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
147 val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
148 writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
149 }
150
151 val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
152 val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
153 val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
154 writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
155
156 pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
157 pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
158 return 0;
159}
160EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
161
162static int hidma_mgmt_probe(struct platform_device *pdev)
163{
164 struct hidma_mgmt_dev *mgmtdev;
165 struct resource *res;
166 void __iomem *virtaddr;
167 int irq;
168 int rc;
169 u32 val;
170
171 pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
172 pm_runtime_use_autosuspend(&pdev->dev);
173 pm_runtime_set_active(&pdev->dev);
174 pm_runtime_enable(&pdev->dev);
175 pm_runtime_get_sync(&pdev->dev);
176
177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178 virtaddr = devm_ioremap_resource(&pdev->dev, res);
179 if (IS_ERR(virtaddr)) {
180 rc = -ENOMEM;
181 goto out;
182 }
183
184 irq = platform_get_irq(pdev, 0);
185 if (irq < 0) {
186 dev_err(&pdev->dev, "irq resources not found\n");
187 rc = irq;
188 goto out;
189 }
190
191 mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
192 if (!mgmtdev) {
193 rc = -ENOMEM;
194 goto out;
195 }
196
197 mgmtdev->pdev = pdev;
198 mgmtdev->addrsize = resource_size(res);
199 mgmtdev->virtaddr = virtaddr;
200
201 rc = device_property_read_u32(&pdev->dev, "dma-channels",
202 &mgmtdev->dma_channels);
203 if (rc) {
204 dev_err(&pdev->dev, "number of channels missing\n");
205 goto out;
206 }
207
208 rc = device_property_read_u32(&pdev->dev,
209 "channel-reset-timeout-cycles",
210 &mgmtdev->chreset_timeout_cycles);
211 if (rc) {
212 dev_err(&pdev->dev, "channel reset timeout missing\n");
213 goto out;
214 }
215
216 rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
217 &mgmtdev->max_write_request);
218 if (rc) {
219 dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
220 goto out;
221 }
222
223 if (max_write_request &&
224 (max_write_request != mgmtdev->max_write_request)) {
225 dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
226 max_write_request);
227 mgmtdev->max_write_request = max_write_request;
228 } else
229 max_write_request = mgmtdev->max_write_request;
230
231 rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
232 &mgmtdev->max_read_request);
233 if (rc) {
234 dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
235 goto out;
236 }
237 if (max_read_request &&
238 (max_read_request != mgmtdev->max_read_request)) {
239 dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
240 max_read_request);
241 mgmtdev->max_read_request = max_read_request;
242 } else
243 max_read_request = mgmtdev->max_read_request;
244
245 rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
246 &mgmtdev->max_wr_xactions);
247 if (rc) {
248 dev_err(&pdev->dev, "max-write-transactions missing\n");
249 goto out;
250 }
251 if (max_wr_xactions &&
252 (max_wr_xactions != mgmtdev->max_wr_xactions)) {
253 dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
254 max_wr_xactions);
255 mgmtdev->max_wr_xactions = max_wr_xactions;
256 } else
257 max_wr_xactions = mgmtdev->max_wr_xactions;
258
259 rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
260 &mgmtdev->max_rd_xactions);
261 if (rc) {
262 dev_err(&pdev->dev, "max-read-transactions missing\n");
263 goto out;
264 }
265 if (max_rd_xactions &&
266 (max_rd_xactions != mgmtdev->max_rd_xactions)) {
267 dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
268 max_rd_xactions);
269 mgmtdev->max_rd_xactions = max_rd_xactions;
270 } else
271 max_rd_xactions = mgmtdev->max_rd_xactions;
272
273 mgmtdev->priority = devm_kcalloc(&pdev->dev,
274 mgmtdev->dma_channels,
275 sizeof(*mgmtdev->priority),
276 GFP_KERNEL);
277 if (!mgmtdev->priority) {
278 rc = -ENOMEM;
279 goto out;
280 }
281
282 mgmtdev->weight = devm_kcalloc(&pdev->dev,
283 mgmtdev->dma_channels,
284 sizeof(*mgmtdev->weight), GFP_KERNEL);
285 if (!mgmtdev->weight) {
286 rc = -ENOMEM;
287 goto out;
288 }
289
290 rc = hidma_mgmt_setup(mgmtdev);
291 if (rc) {
292 dev_err(&pdev->dev, "setup failed\n");
293 goto out;
294 }
295
296
297 val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
298 val |= 1;
299 writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
300
301 rc = hidma_mgmt_init_sys(mgmtdev);
302 if (rc) {
303 dev_err(&pdev->dev, "sysfs setup failed\n");
304 goto out;
305 }
306
307 dev_info(&pdev->dev,
308 "HW rev: %d.%d @ %pa with %d physical channels\n",
309 mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
310 &res->start, mgmtdev->dma_channels);
311
312 platform_set_drvdata(pdev, mgmtdev);
313 pm_runtime_mark_last_busy(&pdev->dev);
314 pm_runtime_put_autosuspend(&pdev->dev);
315 return 0;
316out:
317 pm_runtime_put_sync_suspend(&pdev->dev);
318 pm_runtime_disable(&pdev->dev);
319 return rc;
320}
321
322#if IS_ENABLED(CONFIG_ACPI)
323static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
324 {"QCOM8060"},
325 {},
326};
327MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
328#endif
329
330static const struct of_device_id hidma_mgmt_match[] = {
331 {.compatible = "qcom,hidma-mgmt-1.0",},
332 {},
333};
334MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
335
336static struct platform_driver hidma_mgmt_driver = {
337 .probe = hidma_mgmt_probe,
338 .driver = {
339 .name = "hidma-mgmt",
340 .of_match_table = hidma_mgmt_match,
341 .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
342 },
343};
344
345#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
346static int object_counter;
347
348static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
349{
350 struct platform_device *pdev_parent = of_find_device_by_node(np);
351 struct platform_device_info pdevinfo;
352 struct device_node *child;
353 struct resource *res;
354 int ret = 0;
355
356
357 res = kcalloc(3, sizeof(*res), GFP_KERNEL);
358 if (!res)
359 return -ENOMEM;
360
361 for_each_available_child_of_node(np, child) {
362 struct platform_device *new_pdev;
363
364 ret = of_address_to_resource(child, 0, &res[0]);
365 if (!ret)
366 goto out;
367
368 ret = of_address_to_resource(child, 1, &res[1]);
369 if (!ret)
370 goto out;
371
372 ret = of_irq_to_resource(child, 0, &res[2]);
373 if (ret <= 0)
374 goto out;
375
376 memset(&pdevinfo, 0, sizeof(pdevinfo));
377 pdevinfo.fwnode = &child->fwnode;
378 pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
379 pdevinfo.name = child->name;
380 pdevinfo.id = object_counter++;
381 pdevinfo.res = res;
382 pdevinfo.num_res = 3;
383 pdevinfo.data = NULL;
384 pdevinfo.size_data = 0;
385 pdevinfo.dma_mask = DMA_BIT_MASK(64);
386 new_pdev = platform_device_register_full(&pdevinfo);
387 if (IS_ERR(new_pdev)) {
388 ret = PTR_ERR(new_pdev);
389 goto out;
390 }
391 of_node_get(child);
392 new_pdev->dev.of_node = child;
393 of_dma_configure(&new_pdev->dev, child, true);
394
395
396
397
398 of_msi_configure(&new_pdev->dev, child);
399 of_node_put(child);
400 }
401out:
402 kfree(res);
403
404 return ret;
405}
406#endif
407
408static int __init hidma_mgmt_init(void)
409{
410#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
411 struct device_node *child;
412
413 for_each_matching_node(child, hidma_mgmt_match) {
414
415 hidma_mgmt_of_populate_channels(child);
416 }
417#endif
418 return platform_driver_register(&hidma_mgmt_driver);
419
420}
421module_init(hidma_mgmt_init);
422MODULE_LICENSE("GPL v2");
423
