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28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include "amdgpu_ctx.h"
32
33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
37#include <linux/rbtree.h>
38#include <linux/hashtable.h>
39#include <linux/dma-fence.h>
40
41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
46
47#include <drm/amdgpu_drm.h>
48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
50#include <drm/gpu_scheduler.h>
51
52#include <kgd_kfd_interface.h>
53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
55
56#include "amd_shared.h"
57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
61#include "amdgpu_ttm.h"
62#include "amdgpu_psp.h"
63#include "amdgpu_gds.h"
64#include "amdgpu_sync.h"
65#include "amdgpu_ring.h"
66#include "amdgpu_vm.h"
67#include "amdgpu_dpm.h"
68#include "amdgpu_acp.h"
69#include "amdgpu_uvd.h"
70#include "amdgpu_vce.h"
71#include "amdgpu_vcn.h"
72#include "amdgpu_mn.h"
73#include "amdgpu_gmc.h"
74#include "amdgpu_gfx.h"
75#include "amdgpu_sdma.h"
76#include "amdgpu_dm.h"
77#include "amdgpu_virt.h"
78#include "amdgpu_csa.h"
79#include "amdgpu_gart.h"
80#include "amdgpu_debugfs.h"
81#include "amdgpu_job.h"
82#include "amdgpu_bo_list.h"
83#include "amdgpu_gem.h"
84#include "amdgpu_doorbell.h"
85#include "amdgpu_amdkfd.h"
86#include "amdgpu_smu.h"
87#include "amdgpu_discovery.h"
88#include "amdgpu_mes.h"
89
90#define MAX_GPU_INSTANCE 16
91
92struct amdgpu_gpu_instance
93{
94 struct amdgpu_device *adev;
95 int mgpu_fan_enabled;
96};
97
98struct amdgpu_mgpu_info
99{
100 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
101 struct mutex mutex;
102 uint32_t num_gpu;
103 uint32_t num_dgpu;
104 uint32_t num_apu;
105};
106
107
108
109
110extern int amdgpu_modeset;
111extern int amdgpu_vram_limit;
112extern int amdgpu_vis_vram_limit;
113extern int amdgpu_gart_size;
114extern int amdgpu_gtt_size;
115extern int amdgpu_moverate;
116extern int amdgpu_benchmarking;
117extern int amdgpu_testing;
118extern int amdgpu_audio;
119extern int amdgpu_disp_priority;
120extern int amdgpu_hw_i2c;
121extern int amdgpu_pcie_gen2;
122extern int amdgpu_msi;
123extern int amdgpu_dpm;
124extern int amdgpu_fw_load_type;
125extern int amdgpu_aspm;
126extern int amdgpu_runtime_pm;
127extern uint amdgpu_ip_block_mask;
128extern int amdgpu_bapm;
129extern int amdgpu_deep_color;
130extern int amdgpu_vm_size;
131extern int amdgpu_vm_block_size;
132extern int amdgpu_vm_fragment_size;
133extern int amdgpu_vm_fault_stop;
134extern int amdgpu_vm_debug;
135extern int amdgpu_vm_update_mode;
136extern int amdgpu_dc;
137extern int amdgpu_sched_jobs;
138extern int amdgpu_sched_hw_submission;
139extern uint amdgpu_pcie_gen_cap;
140extern uint amdgpu_pcie_lane_cap;
141extern uint amdgpu_cg_mask;
142extern uint amdgpu_pg_mask;
143extern uint amdgpu_sdma_phase_quantum;
144extern char *amdgpu_disable_cu;
145extern char *amdgpu_virtual_display;
146extern uint amdgpu_pp_feature_mask;
147extern int amdgpu_ngg;
148extern int amdgpu_prim_buf_per_se;
149extern int amdgpu_pos_buf_per_se;
150extern int amdgpu_cntl_sb_buf_per_se;
151extern int amdgpu_param_buf_per_se;
152extern int amdgpu_job_hang_limit;
153extern int amdgpu_lbpw;
154extern int amdgpu_compute_multipipe;
155extern int amdgpu_gpu_recovery;
156extern int amdgpu_emu_mode;
157extern uint amdgpu_smu_memory_pool_size;
158extern uint amdgpu_dc_feature_mask;
159extern uint amdgpu_dm_abm_level;
160extern struct amdgpu_mgpu_info mgpu_info;
161extern int amdgpu_ras_enable;
162extern uint amdgpu_ras_mask;
163extern int amdgpu_async_gfx_ring;
164extern int amdgpu_mcbp;
165extern int amdgpu_discovery;
166extern int amdgpu_mes;
167extern int amdgpu_noretry;
168
169#ifdef CONFIG_DRM_AMDGPU_SI
170extern int amdgpu_si_support;
171#endif
172#ifdef CONFIG_DRM_AMDGPU_CIK
173extern int amdgpu_cik_support;
174#endif
175
176#define AMDGPU_VM_MAX_NUM_CTX 4096
177#define AMDGPU_SG_THRESHOLD (256*1024*1024)
178#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL
179#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
180#define AMDGPU_MAX_USEC_TIMEOUT 100000
181#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
182
183#define AMDGPU_IB_POOL_SIZE 16
184#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
185#define AMDGPUFB_CONN_LIMIT 4
186#define AMDGPU_BIOS_NUM_SCRATCH 16
187
188
189#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
190
191
192#define AMDGPU_RESET_GFX (1 << 0)
193#define AMDGPU_RESET_COMPUTE (1 << 1)
194#define AMDGPU_RESET_DMA (1 << 2)
195#define AMDGPU_RESET_CP (1 << 3)
196#define AMDGPU_RESET_GRBM (1 << 4)
197#define AMDGPU_RESET_DMA1 (1 << 5)
198#define AMDGPU_RESET_RLC (1 << 6)
199#define AMDGPU_RESET_SEM (1 << 7)
200#define AMDGPU_RESET_IH (1 << 8)
201#define AMDGPU_RESET_VMC (1 << 9)
202#define AMDGPU_RESET_MC (1 << 10)
203#define AMDGPU_RESET_DISPLAY (1 << 11)
204#define AMDGPU_RESET_UVD (1 << 12)
205#define AMDGPU_RESET_VCE (1 << 13)
206#define AMDGPU_RESET_VCE1 (1 << 14)
207
208
209#define CIK_CURSOR_WIDTH 128
210#define CIK_CURSOR_HEIGHT 128
211
212struct amdgpu_device;
213struct amdgpu_ib;
214struct amdgpu_cs_parser;
215struct amdgpu_job;
216struct amdgpu_irq_src;
217struct amdgpu_fpriv;
218struct amdgpu_bo_va_mapping;
219struct amdgpu_atif;
220struct kfd_vm_fault_info;
221
222enum amdgpu_cp_irq {
223 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
224 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
225 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
226 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
227 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
228 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
229 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
230 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
231 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
232 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
233
234 AMDGPU_CP_IRQ_LAST
235};
236
237enum amdgpu_thermal_irq {
238 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
239 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
240
241 AMDGPU_THERMAL_IRQ_LAST
242};
243
244enum amdgpu_kiq_irq {
245 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
246 AMDGPU_CP_KIQ_IRQ_LAST
247};
248
249#define MAX_KIQ_REG_WAIT 5000
250#define MAX_KIQ_REG_BAILOUT_INTERVAL 5
251#define MAX_KIQ_REG_TRY 80
252
253int amdgpu_device_ip_set_clockgating_state(void *dev,
254 enum amd_ip_block_type block_type,
255 enum amd_clockgating_state state);
256int amdgpu_device_ip_set_powergating_state(void *dev,
257 enum amd_ip_block_type block_type,
258 enum amd_powergating_state state);
259void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
260 u32 *flags);
261int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
262 enum amd_ip_block_type block_type);
263bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
264 enum amd_ip_block_type block_type);
265
266#define AMDGPU_MAX_IP_NUM 16
267
268struct amdgpu_ip_block_status {
269 bool valid;
270 bool sw;
271 bool hw;
272 bool late_initialized;
273 bool hang;
274};
275
276struct amdgpu_ip_block_version {
277 const enum amd_ip_block_type type;
278 const u32 major;
279 const u32 minor;
280 const u32 rev;
281 const struct amd_ip_funcs *funcs;
282};
283
284struct amdgpu_ip_block {
285 struct amdgpu_ip_block_status status;
286 const struct amdgpu_ip_block_version *version;
287};
288
289int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
290 enum amd_ip_block_type type,
291 u32 major, u32 minor);
292
293struct amdgpu_ip_block *
294amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
295 enum amd_ip_block_type type);
296
297int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
298 const struct amdgpu_ip_block_version *ip_block_version);
299
300
301
302
303bool amdgpu_get_bios(struct amdgpu_device *adev);
304bool amdgpu_read_bios(struct amdgpu_device *adev);
305
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308
309
310#define AMDGPU_MAX_PPLL 3
311
312struct amdgpu_clock {
313 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
314 struct amdgpu_pll spll;
315 struct amdgpu_pll mpll;
316
317 uint32_t default_mclk;
318 uint32_t default_sclk;
319 uint32_t default_dispclk;
320 uint32_t current_dispclk;
321 uint32_t dp_extclk;
322 uint32_t max_pixel_clock;
323};
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348
349#define AMDGPU_SA_NUM_FENCE_LISTS 32
350
351struct amdgpu_sa_manager {
352 wait_queue_head_t wq;
353 struct amdgpu_bo *bo;
354 struct list_head *hole;
355 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
356 struct list_head olist;
357 unsigned size;
358 uint64_t gpu_addr;
359 void *cpu_ptr;
360 uint32_t domain;
361 uint32_t align;
362};
363
364
365struct amdgpu_sa_bo {
366 struct list_head olist;
367 struct list_head flist;
368 struct amdgpu_sa_manager *manager;
369 unsigned soffset;
370 unsigned eoffset;
371 struct dma_fence *fence;
372};
373
374int amdgpu_fence_slab_init(void);
375void amdgpu_fence_slab_fini(void);
376
377
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379
380
381struct amdgpu_flip_work {
382 struct delayed_work flip_work;
383 struct work_struct unpin_work;
384 struct amdgpu_device *adev;
385 int crtc_id;
386 u32 target_vblank;
387 uint64_t base;
388 struct drm_pending_vblank_event *event;
389 struct amdgpu_bo *old_abo;
390 struct dma_fence *excl;
391 unsigned shared_count;
392 struct dma_fence **shared;
393 struct dma_fence_cb cb;
394 bool async;
395};
396
397
398
399
400
401
402struct amdgpu_ib {
403 struct amdgpu_sa_bo *sa_bo;
404 uint32_t length_dw;
405 uint64_t gpu_addr;
406 uint32_t *ptr;
407 uint32_t flags;
408};
409
410extern const struct drm_sched_backend_ops amdgpu_sched_ops;
411
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414
415
416struct amdgpu_fpriv {
417 struct amdgpu_vm vm;
418 struct amdgpu_bo_va *prt_va;
419 struct amdgpu_bo_va *csa_va;
420 struct mutex bo_list_lock;
421 struct idr bo_list_handles;
422 struct amdgpu_ctx_mgr ctx_mgr;
423};
424
425int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
426int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
427
428int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
429 unsigned size, struct amdgpu_ib *ib);
430void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
431 struct dma_fence *f);
432int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
433 struct amdgpu_ib *ibs, struct amdgpu_job *job,
434 struct dma_fence **f);
435int amdgpu_ib_pool_init(struct amdgpu_device *adev);
436void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
437int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
438
439
440
441
442struct amdgpu_cs_chunk {
443 uint32_t chunk_id;
444 uint32_t length_dw;
445 void *kdata;
446};
447
448struct amdgpu_cs_post_dep {
449 struct drm_syncobj *syncobj;
450 struct dma_fence_chain *chain;
451 u64 point;
452};
453
454struct amdgpu_cs_parser {
455 struct amdgpu_device *adev;
456 struct drm_file *filp;
457 struct amdgpu_ctx *ctx;
458
459
460 unsigned nchunks;
461 struct amdgpu_cs_chunk *chunks;
462
463
464 struct amdgpu_job *job;
465 struct drm_sched_entity *entity;
466
467
468 struct ww_acquire_ctx ticket;
469 struct amdgpu_bo_list *bo_list;
470 struct amdgpu_mn *mn;
471 struct amdgpu_bo_list_entry vm_pd;
472 struct list_head validated;
473 struct dma_fence *fence;
474 uint64_t bytes_moved_threshold;
475 uint64_t bytes_moved_vis_threshold;
476 uint64_t bytes_moved;
477 uint64_t bytes_moved_vis;
478 struct amdgpu_bo_list_entry *evictable;
479
480
481 struct amdgpu_bo_list_entry uf_entry;
482
483 unsigned num_post_deps;
484 struct amdgpu_cs_post_dep *post_deps;
485};
486
487static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
488 uint32_t ib_idx, int idx)
489{
490 return p->job->ibs[ib_idx].ptr[idx];
491}
492
493static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
494 uint32_t ib_idx, int idx,
495 uint32_t value)
496{
497 p->job->ibs[ib_idx].ptr[idx] = value;
498}
499
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501
502
503#define AMDGPU_MAX_WB 128
504
505struct amdgpu_wb {
506 struct amdgpu_bo *wb_obj;
507 volatile uint32_t *wb;
508 uint64_t gpu_addr;
509 u32 num_wb;
510 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
511};
512
513int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
514void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
515
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519void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
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525void amdgpu_test_moves(struct amdgpu_device *adev);
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529
530struct amdgpu_allowed_register_entry {
531 uint32_t reg_offset;
532 bool grbm_indexed;
533};
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537
538struct amdgpu_asic_funcs {
539 bool (*read_disabled_bios)(struct amdgpu_device *adev);
540 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
541 u8 *bios, u32 length_bytes);
542 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
543 u32 sh_num, u32 reg_offset, u32 *value);
544 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
545 int (*reset)(struct amdgpu_device *adev);
546
547 u32 (*get_xclk)(struct amdgpu_device *adev);
548
549 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
550 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
551
552 int (*get_pcie_lanes)(struct amdgpu_device *adev);
553 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
554
555 u32 (*get_config_memsize)(struct amdgpu_device *adev);
556
557 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
558
559 void (*invalidate_hdp)(struct amdgpu_device *adev,
560 struct amdgpu_ring *ring);
561
562 bool (*need_full_reset)(struct amdgpu_device *adev);
563
564 void (*init_doorbell_index)(struct amdgpu_device *adev);
565
566 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
567 uint64_t *count1);
568
569 bool (*need_reset_on_init)(struct amdgpu_device *adev);
570
571 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
572};
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576
577int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *filp);
579
580int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
581int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
582 struct drm_file *filp);
583int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
584int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
585 struct drm_file *filp);
586
587
588struct amdgpu_vram_scratch {
589 struct amdgpu_bo *robj;
590 volatile uint32_t *ptr;
591 u64 gpu_addr;
592};
593
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595
596
597struct amdgpu_atcs_functions {
598 bool get_ext_state;
599 bool pcie_perf_req;
600 bool pcie_dev_rdy;
601 bool pcie_bus_width;
602};
603
604struct amdgpu_atcs {
605 struct amdgpu_atcs_functions functions;
606};
607
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609
610
611struct amdgpu_fw_vram_usage {
612 u64 start_offset;
613 u64 size;
614 struct amdgpu_bo *reserved_bo;
615 void *va;
616};
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618
619
620
621struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
622void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
623
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626
627typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
628typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
629
630typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
631typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
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636
637
638struct nbio_hdp_flush_reg {
639 u32 ref_and_mask_cp0;
640 u32 ref_and_mask_cp1;
641 u32 ref_and_mask_cp2;
642 u32 ref_and_mask_cp3;
643 u32 ref_and_mask_cp4;
644 u32 ref_and_mask_cp5;
645 u32 ref_and_mask_cp6;
646 u32 ref_and_mask_cp7;
647 u32 ref_and_mask_cp8;
648 u32 ref_and_mask_cp9;
649 u32 ref_and_mask_sdma0;
650 u32 ref_and_mask_sdma1;
651};
652
653struct amdgpu_mmio_remap {
654 u32 reg_offset;
655 resource_size_t bus_addr;
656};
657
658struct amdgpu_nbio_funcs {
659 const struct nbio_hdp_flush_reg *hdp_flush_reg;
660 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
661 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
662 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
663 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
664 u32 (*get_rev_id)(struct amdgpu_device *adev);
665 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
666 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
667 u32 (*get_memsize)(struct amdgpu_device *adev);
668 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
669 bool use_doorbell, int doorbell_index, int doorbell_size);
670 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
671 int doorbell_index);
672 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
673 bool enable);
674 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
675 bool enable);
676 void (*ih_doorbell_range)(struct amdgpu_device *adev,
677 bool use_doorbell, int doorbell_index);
678 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
679 bool enable);
680 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
681 bool enable);
682 void (*get_clockgating_state)(struct amdgpu_device *adev,
683 u32 *flags);
684 void (*ih_control)(struct amdgpu_device *adev);
685 void (*init_registers)(struct amdgpu_device *adev);
686 void (*detect_hw_virt)(struct amdgpu_device *adev);
687 void (*remap_hdp_registers)(struct amdgpu_device *adev);
688};
689
690struct amdgpu_df_funcs {
691 void (*sw_init)(struct amdgpu_device *adev);
692 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
693 bool enable);
694 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
695 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
696 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
697 bool enable);
698 void (*get_clockgating_state)(struct amdgpu_device *adev,
699 u32 *flags);
700 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
701 bool enable);
702 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
703 int is_enable);
704 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
705 int is_disable);
706 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
707 uint64_t *count);
708};
709
710enum amd_hw_ip_block_type {
711 GC_HWIP = 1,
712 HDP_HWIP,
713 SDMA0_HWIP,
714 SDMA1_HWIP,
715 MMHUB_HWIP,
716 ATHUB_HWIP,
717 NBIO_HWIP,
718 MP0_HWIP,
719 MP1_HWIP,
720 UVD_HWIP,
721 VCN_HWIP = UVD_HWIP,
722 VCE_HWIP,
723 DF_HWIP,
724 DCE_HWIP,
725 OSSSYS_HWIP,
726 SMUIO_HWIP,
727 PWR_HWIP,
728 NBIF_HWIP,
729 THM_HWIP,
730 CLK_HWIP,
731 MAX_HWIP
732};
733
734#define HWIP_MAX_INSTANCE 6
735
736struct amd_powerplay {
737 void *pp_handle;
738 const struct amd_pm_funcs *pp_funcs;
739};
740
741#define AMDGPU_RESET_MAGIC_NUM 64
742#define AMDGPU_MAX_DF_PERFMONS 4
743struct amdgpu_device {
744 struct device *dev;
745 struct drm_device *ddev;
746 struct pci_dev *pdev;
747
748#ifdef CONFIG_DRM_AMD_ACP
749 struct amdgpu_acp acp;
750#endif
751
752
753 enum amd_asic_type asic_type;
754 uint32_t family;
755 uint32_t rev_id;
756 uint32_t external_rev_id;
757 unsigned long flags;
758 int usec_timeout;
759 const struct amdgpu_asic_funcs *asic_funcs;
760 bool shutdown;
761 bool need_dma32;
762 bool need_swiotlb;
763 bool accel_working;
764 struct notifier_block acpi_nb;
765 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
766 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
767 unsigned debugfs_count;
768#if defined(CONFIG_DEBUG_FS)
769 struct dentry *debugfs_preempt;
770 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
771#endif
772 struct amdgpu_atif *atif;
773 struct amdgpu_atcs atcs;
774 struct mutex srbm_mutex;
775
776 struct mutex grbm_idx_mutex;
777 struct dev_pm_domain vga_pm_domain;
778 bool have_disp_power_ref;
779 bool have_atomics_support;
780
781
782 bool is_atom_fw;
783 uint8_t *bios;
784 uint32_t bios_size;
785 struct amdgpu_bo *stolen_vga_memory;
786 uint32_t bios_scratch_reg_offset;
787 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
788
789
790 resource_size_t rmmio_base;
791 resource_size_t rmmio_size;
792 void __iomem *rmmio;
793
794 spinlock_t mmio_idx_lock;
795 struct amdgpu_mmio_remap rmmio_remap;
796
797 spinlock_t smc_idx_lock;
798 amdgpu_rreg_t smc_rreg;
799 amdgpu_wreg_t smc_wreg;
800
801 spinlock_t pcie_idx_lock;
802 amdgpu_rreg_t pcie_rreg;
803 amdgpu_wreg_t pcie_wreg;
804 amdgpu_rreg_t pciep_rreg;
805 amdgpu_wreg_t pciep_wreg;
806
807 spinlock_t uvd_ctx_idx_lock;
808 amdgpu_rreg_t uvd_ctx_rreg;
809 amdgpu_wreg_t uvd_ctx_wreg;
810
811 spinlock_t didt_idx_lock;
812 amdgpu_rreg_t didt_rreg;
813 amdgpu_wreg_t didt_wreg;
814
815 spinlock_t gc_cac_idx_lock;
816 amdgpu_rreg_t gc_cac_rreg;
817 amdgpu_wreg_t gc_cac_wreg;
818
819 spinlock_t se_cac_idx_lock;
820 amdgpu_rreg_t se_cac_rreg;
821 amdgpu_wreg_t se_cac_wreg;
822
823 spinlock_t audio_endpt_idx_lock;
824 amdgpu_block_rreg_t audio_endpt_rreg;
825 amdgpu_block_wreg_t audio_endpt_wreg;
826 void __iomem *rio_mem;
827 resource_size_t rio_mem_size;
828 struct amdgpu_doorbell doorbell;
829
830
831 struct amdgpu_clock clock;
832
833
834 struct amdgpu_gmc gmc;
835 struct amdgpu_gart gart;
836 dma_addr_t dummy_page_addr;
837 struct amdgpu_vm_manager vm_manager;
838 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
839
840
841 struct amdgpu_mman mman;
842 struct amdgpu_vram_scratch vram_scratch;
843 struct amdgpu_wb wb;
844 atomic64_t num_bytes_moved;
845 atomic64_t num_evictions;
846 atomic64_t num_vram_cpu_page_faults;
847 atomic_t gpu_reset_counter;
848 atomic_t vram_lost_counter;
849
850
851 struct {
852 spinlock_t lock;
853 s64 last_update_us;
854 s64 accum_us;
855 s64 accum_us_vis;
856 u32 log2_max_MBps;
857 } mm_stats;
858
859
860 bool enable_virtual_display;
861 struct amdgpu_mode_info mode_info;
862
863 struct work_struct hotplug_work;
864 struct amdgpu_irq_src crtc_irq;
865 struct amdgpu_irq_src vupdate_irq;
866 struct amdgpu_irq_src pageflip_irq;
867 struct amdgpu_irq_src hpd_irq;
868
869
870 u64 fence_context;
871 unsigned num_rings;
872 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
873 bool ib_pool_ready;
874 struct amdgpu_sa_manager ring_tmp_bo;
875
876
877 struct amdgpu_irq irq;
878
879
880 struct amd_powerplay powerplay;
881 bool pp_force_state_enabled;
882
883
884 struct smu_context smu;
885
886
887 struct amdgpu_pm pm;
888 u32 cg_flags;
889 u32 pg_flags;
890
891
892 struct amdgpu_gfx gfx;
893
894
895 struct amdgpu_sdma sdma;
896
897
898 struct amdgpu_uvd uvd;
899
900
901 struct amdgpu_vce vce;
902
903
904 struct amdgpu_vcn vcn;
905
906
907 struct amdgpu_firmware firmware;
908
909
910 struct psp_context psp;
911
912
913 struct amdgpu_gds gds;
914
915
916 struct amdgpu_kfd_dev kfd;
917
918
919 struct amdgpu_display_manager dm;
920
921
922 uint8_t *discovery;
923
924
925 bool enable_mes;
926 struct amdgpu_mes mes;
927
928 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
929 int num_ip_blocks;
930 struct mutex mn_lock;
931 DECLARE_HASHTABLE(mn_hash, 7);
932
933
934 atomic64_t vram_pin_size;
935 atomic64_t visible_pin_size;
936 atomic64_t gart_pin_size;
937
938
939 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
940
941 const struct amdgpu_nbio_funcs *nbio_funcs;
942 const struct amdgpu_df_funcs *df_funcs;
943
944
945 struct delayed_work delayed_init_work;
946
947 struct amdgpu_virt virt;
948
949 struct amdgpu_fw_vram_usage fw_vram_usage;
950
951
952 struct list_head shadow_list;
953 struct mutex shadow_list_lock;
954
955 struct list_head ring_lru_list;
956 spinlock_t ring_lru_list_lock;
957
958
959 bool has_hw_reset;
960 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
961
962
963 bool in_suspend;
964
965
966 unsigned long last_mm_index;
967 bool in_gpu_reset;
968 struct mutex lock_reset;
969 struct amdgpu_doorbell_index doorbell_index;
970
971 int asic_reset_res;
972 struct work_struct xgmi_reset_work;
973
974 bool in_baco_reset;
975
976 long gfx_timeout;
977 long sdma_timeout;
978 long video_timeout;
979 long compute_timeout;
980
981 uint64_t unique_id;
982 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
983};
984
985static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
986{
987 return container_of(bdev, struct amdgpu_device, mman.bdev);
988}
989
990int amdgpu_device_init(struct amdgpu_device *adev,
991 struct drm_device *ddev,
992 struct pci_dev *pdev,
993 uint32_t flags);
994void amdgpu_device_fini(struct amdgpu_device *adev);
995int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
996
997uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
998 uint32_t acc_flags);
999void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1000 uint32_t acc_flags);
1001void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1002uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1003
1004u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1005void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1006
1007bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1008bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1009
1010int emu_soc_asic_init(struct amdgpu_device *adev);
1011
1012
1013
1014
1015
1016#define AMDGPU_REGS_IDX (1<<0)
1017#define AMDGPU_REGS_NO_KIQ (1<<1)
1018
1019#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1020#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1021
1022#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1023#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1024
1025#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1026#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1027#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1028#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1029#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1030#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1031#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1032#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1033#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1034#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1035#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1036#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1037#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1038#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1039#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1040#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1041#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1042#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1043#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1044#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1045#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1046#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1047#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1048#define WREG32_P(reg, val, mask) \
1049 do { \
1050 uint32_t tmp_ = RREG32(reg); \
1051 tmp_ &= (mask); \
1052 tmp_ |= ((val) & ~(mask)); \
1053 WREG32(reg, tmp_); \
1054 } while (0)
1055#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1056#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1057#define WREG32_PLL_P(reg, val, mask) \
1058 do { \
1059 uint32_t tmp_ = RREG32_PLL(reg); \
1060 tmp_ &= (mask); \
1061 tmp_ |= ((val) & ~(mask)); \
1062 WREG32_PLL(reg, tmp_); \
1063 } while (0)
1064#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1065#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1066#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1067
1068#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1069#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1070
1071#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1072 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1073 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1074
1075#define REG_GET_FIELD(value, reg, field) \
1076 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1077
1078#define WREG32_FIELD(reg, field, val) \
1079 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1080
1081#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1082 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1083
1084
1085
1086
1087#define RBIOS8(i) (adev->bios[i])
1088#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1089#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1090
1091
1092
1093
1094#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1095#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1096#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1097#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1098#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1099#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1100#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1101#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1102#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1103#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1104#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1105#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1106#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1107#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1108#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1109#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1110#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1111#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1112#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1113
1114
1115bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1116int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1117 struct amdgpu_job* job);
1118void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1119bool amdgpu_device_need_post(struct amdgpu_device *adev);
1120
1121void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1122 u64 num_vis_bytes);
1123int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1124void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1125 const u32 *registers,
1126 const u32 array_size);
1127
1128bool amdgpu_device_is_px(struct drm_device *dev);
1129bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1130 struct amdgpu_device *peer_adev);
1131
1132
1133#if defined(CONFIG_VGA_SWITCHEROO)
1134void amdgpu_register_atpx_handler(void);
1135void amdgpu_unregister_atpx_handler(void);
1136bool amdgpu_has_atpx_dgpu_power_cntl(void);
1137bool amdgpu_is_atpx_hybrid(void);
1138bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1139bool amdgpu_has_atpx(void);
1140#else
1141static inline void amdgpu_register_atpx_handler(void) {}
1142static inline void amdgpu_unregister_atpx_handler(void) {}
1143static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1144static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1145static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1146static inline bool amdgpu_has_atpx(void) { return false; }
1147#endif
1148
1149#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1150void *amdgpu_atpx_get_dhandle(void);
1151#else
1152static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1153#endif
1154
1155
1156
1157
1158extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1159extern const int amdgpu_max_kms_ioctl;
1160
1161int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1162void amdgpu_driver_unload_kms(struct drm_device *dev);
1163void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1164int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1165void amdgpu_driver_postclose_kms(struct drm_device *dev,
1166 struct drm_file *file_priv);
1167int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1168int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1169int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1170u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1171int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1172void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1173long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1174 unsigned long arg);
1175
1176
1177
1178
1179struct amdgpu_afmt_acr {
1180 u32 clock;
1181
1182 int n_32khz;
1183 int cts_32khz;
1184
1185 int n_44_1khz;
1186 int cts_44_1khz;
1187
1188 int n_48khz;
1189 int cts_48khz;
1190
1191};
1192
1193struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1194
1195
1196#if defined(CONFIG_ACPI)
1197int amdgpu_acpi_init(struct amdgpu_device *adev);
1198void amdgpu_acpi_fini(struct amdgpu_device *adev);
1199bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1200int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1201 u8 perf_req, bool advertise);
1202int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1203
1204void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1205 struct amdgpu_dm_backlight_caps *caps);
1206#else
1207static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1208static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1209#endif
1210
1211int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1212 uint64_t addr, struct amdgpu_bo **bo,
1213 struct amdgpu_bo_va_mapping **mapping);
1214
1215#if defined(CONFIG_DRM_AMD_DC)
1216int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1217#else
1218static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1219#endif
1220
1221
1222void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1223void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1224
1225#include "amdgpu_object.h"
1226
1227
1228#define AMDGPU_PMU_ATTR(_name, _object) \
1229static ssize_t \
1230_name##_show(struct device *dev, \
1231 struct device_attribute *attr, \
1232 char *page) \
1233{ \
1234 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1235 return sprintf(page, _object "\n"); \
1236} \
1237 \
1238static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1239
1240#endif
1241
1242