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24#ifndef __AMDGPU_GFX_H__
25#define __AMDGPU_GFX_H__
26
27
28
29
30#include "clearstate_defs.h"
31#include "amdgpu_ring.h"
32#include "amdgpu_rlc.h"
33
34
35#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
36#define AMDGPU_GFX_SAFE_MODE 0x00000001L
37#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
38#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
39#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
40
41#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
42#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
43
44struct amdgpu_mec {
45 struct amdgpu_bo *hpd_eop_obj;
46 u64 hpd_eop_gpu_addr;
47 struct amdgpu_bo *mec_fw_obj;
48 u64 mec_fw_gpu_addr;
49 u32 num_mec;
50 u32 num_pipe_per_mec;
51 u32 num_queue_per_pipe;
52 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
53
54
55 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
56};
57
58enum amdgpu_unmap_queues_action {
59 PREEMPT_QUEUES = 0,
60 RESET_QUEUES,
61 DISABLE_PROCESS_QUEUES,
62 PREEMPT_QUEUES_NO_UNMAP,
63};
64
65struct kiq_pm4_funcs {
66
67 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
68 uint64_t queue_mask);
69 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
70 struct amdgpu_ring *ring);
71 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
72 struct amdgpu_ring *ring,
73 enum amdgpu_unmap_queues_action action,
74 u64 gpu_addr, u64 seq);
75 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
76 struct amdgpu_ring *ring,
77 u64 addr,
78 u64 seq);
79
80 int set_resources_size;
81 int map_queues_size;
82 int unmap_queues_size;
83 int query_status_size;
84};
85
86struct amdgpu_kiq {
87 u64 eop_gpu_addr;
88 struct amdgpu_bo *eop_obj;
89 spinlock_t ring_lock;
90 struct amdgpu_ring ring;
91 struct amdgpu_irq_src irq;
92 const struct kiq_pm4_funcs *pmf;
93};
94
95
96
97
98struct amdgpu_scratch {
99 unsigned num_reg;
100 uint32_t reg_base;
101 uint32_t free_mask;
102};
103
104
105
106
107#define AMDGPU_GFX_MAX_SE 4
108#define AMDGPU_GFX_MAX_SH_PER_SE 2
109
110struct amdgpu_rb_config {
111 uint32_t rb_backend_disable;
112 uint32_t user_rb_backend_disable;
113 uint32_t raster_config;
114 uint32_t raster_config_1;
115};
116
117struct gb_addr_config {
118 uint16_t pipe_interleave_size;
119 uint8_t num_pipes;
120 uint8_t max_compress_frags;
121 uint8_t num_banks;
122 uint8_t num_se;
123 uint8_t num_rb_per_se;
124};
125
126struct amdgpu_gfx_config {
127 unsigned max_shader_engines;
128 unsigned max_tile_pipes;
129 unsigned max_cu_per_sh;
130 unsigned max_sh_per_se;
131 unsigned max_backends_per_se;
132 unsigned max_texture_channel_caches;
133 unsigned max_gprs;
134 unsigned max_gs_threads;
135 unsigned max_hw_contexts;
136 unsigned sc_prim_fifo_size_frontend;
137 unsigned sc_prim_fifo_size_backend;
138 unsigned sc_hiz_tile_fifo_size;
139 unsigned sc_earlyz_tile_fifo_size;
140
141 unsigned num_tile_pipes;
142 unsigned backend_enable_mask;
143 unsigned mem_max_burst_length_bytes;
144 unsigned mem_row_size_in_kb;
145 unsigned shader_engine_tile_size;
146 unsigned num_gpus;
147 unsigned multi_gpu_tile_size;
148 unsigned mc_arb_ramcfg;
149 unsigned gb_addr_config;
150 unsigned num_rbs;
151 unsigned gs_vgt_table_depth;
152 unsigned gs_prim_buffer_depth;
153
154 uint32_t tile_mode_array[32];
155 uint32_t macrotile_mode_array[16];
156
157 struct gb_addr_config gb_addr_config_fields;
158 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
159
160
161 uint32_t double_offchip_lds_buf;
162
163 uint32_t db_debug2;
164
165 uint32_t num_sc_per_sh;
166 uint32_t num_packer_per_sc;
167 uint32_t pa_sc_tile_steering_override;
168};
169
170struct amdgpu_cu_info {
171 uint32_t simd_per_cu;
172 uint32_t max_waves_per_simd;
173 uint32_t wave_front_size;
174 uint32_t max_scratch_slots_per_cu;
175 uint32_t lds_size;
176
177
178 uint32_t number;
179 uint32_t ao_cu_mask;
180 uint32_t ao_cu_bitmap[4][4];
181 uint32_t bitmap[4][4];
182};
183
184struct amdgpu_gfx_funcs {
185
186 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
187 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
188 u32 sh_num, u32 instance);
189 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
190 uint32_t wave, uint32_t *dst, int *no_fields);
191 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
192 uint32_t wave, uint32_t thread, uint32_t start,
193 uint32_t size, uint32_t *dst);
194 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
195 uint32_t wave, uint32_t start, uint32_t size,
196 uint32_t *dst);
197 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
198 u32 queue, u32 vmid);
199};
200
201struct amdgpu_ngg_buf {
202 struct amdgpu_bo *bo;
203 uint64_t gpu_addr;
204 uint32_t size;
205 uint32_t bo_size;
206};
207
208enum {
209 NGG_PRIM = 0,
210 NGG_POS,
211 NGG_CNTL,
212 NGG_PARAM,
213 NGG_BUF_MAX
214};
215
216struct amdgpu_ngg {
217 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
218 uint32_t gds_reserve_addr;
219 uint32_t gds_reserve_size;
220 bool init;
221};
222
223struct sq_work {
224 struct work_struct work;
225 unsigned ih_data;
226};
227
228struct amdgpu_pfp {
229 struct amdgpu_bo *pfp_fw_obj;
230 uint64_t pfp_fw_gpu_addr;
231 uint32_t *pfp_fw_ptr;
232};
233
234struct amdgpu_ce {
235 struct amdgpu_bo *ce_fw_obj;
236 uint64_t ce_fw_gpu_addr;
237 uint32_t *ce_fw_ptr;
238};
239
240struct amdgpu_me {
241 struct amdgpu_bo *me_fw_obj;
242 uint64_t me_fw_gpu_addr;
243 uint32_t *me_fw_ptr;
244 uint32_t num_me;
245 uint32_t num_pipe_per_me;
246 uint32_t num_queue_per_pipe;
247 void *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
248
249
250 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
251};
252
253struct amdgpu_gfx {
254 struct mutex gpu_clock_mutex;
255 struct amdgpu_gfx_config config;
256 struct amdgpu_rlc rlc;
257 struct amdgpu_pfp pfp;
258 struct amdgpu_ce ce;
259 struct amdgpu_me me;
260 struct amdgpu_mec mec;
261 struct amdgpu_kiq kiq;
262 struct amdgpu_scratch scratch;
263 const struct firmware *me_fw;
264 uint32_t me_fw_version;
265 const struct firmware *pfp_fw;
266 uint32_t pfp_fw_version;
267 const struct firmware *ce_fw;
268 uint32_t ce_fw_version;
269 const struct firmware *rlc_fw;
270 uint32_t rlc_fw_version;
271 const struct firmware *mec_fw;
272 uint32_t mec_fw_version;
273 const struct firmware *mec2_fw;
274 uint32_t mec2_fw_version;
275 uint32_t me_feature_version;
276 uint32_t ce_feature_version;
277 uint32_t pfp_feature_version;
278 uint32_t rlc_feature_version;
279 uint32_t rlc_srlc_fw_version;
280 uint32_t rlc_srlc_feature_version;
281 uint32_t rlc_srlg_fw_version;
282 uint32_t rlc_srlg_feature_version;
283 uint32_t rlc_srls_fw_version;
284 uint32_t rlc_srls_feature_version;
285 uint32_t mec_feature_version;
286 uint32_t mec2_feature_version;
287 bool mec_fw_write_wait;
288 bool me_fw_write_wait;
289 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
290 unsigned num_gfx_rings;
291 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
292 unsigned num_compute_rings;
293 struct amdgpu_irq_src eop_irq;
294 struct amdgpu_irq_src priv_reg_irq;
295 struct amdgpu_irq_src priv_inst_irq;
296 struct amdgpu_irq_src cp_ecc_error_irq;
297 struct amdgpu_irq_src sq_irq;
298 struct sq_work sq_work;
299
300
301 uint32_t gfx_current_status;
302
303 unsigned ce_ram_size;
304 struct amdgpu_cu_info cu_info;
305 const struct amdgpu_gfx_funcs *funcs;
306
307
308 uint32_t grbm_soft_reset;
309 uint32_t srbm_soft_reset;
310
311
312 struct amdgpu_ngg ngg;
313
314
315 bool gfx_off_state;
316 struct mutex gfx_off_mutex;
317 uint32_t gfx_off_req_count;
318 struct delayed_work gfx_off_delay_work;
319
320
321 struct mutex pipe_reserve_mutex;
322 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
323
324
325 struct ras_common_if *ras_if;
326};
327
328#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
329#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
330#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
331
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337
338
339
340static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
341{
342 return (u32)((1ULL << bit_width) - 1);
343}
344
345int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
346void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
347
348void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
349 unsigned max_sh);
350
351int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
352 struct amdgpu_ring *ring,
353 struct amdgpu_irq_src *irq);
354
355void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
356 struct amdgpu_irq_src *irq);
357
358void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
359int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
360 unsigned hpd_size);
361
362int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
363 unsigned mqd_size);
364void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
365int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
366int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
367
368void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
369void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
370
371int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
372 int pipe, int queue);
373void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
374 int *mec, int *pipe, int *queue);
375bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
376 int pipe, int queue);
377int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
378 int pipe, int queue);
379void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
380 int *me, int *pipe, int *queue);
381bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
382 int pipe, int queue);
383void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
384
385#endif
386
