LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3 *                VA Linux Systems Inc., Fremont, California.
   4 * Copyright 2008 Red Hat Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Original Authors:
  25 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26 *
  27 * Kernel port Author: Dave Airlie
  28 */
  29
  30#ifndef AMDGPU_MODE_H
  31#define AMDGPU_MODE_H
  32
  33#include <drm/drm_crtc.h>
  34#include <drm/drm_edid.h>
  35#include <drm/drm_encoder.h>
  36#include <drm/drm_dp_helper.h>
  37#include <drm/drm_fixed.h>
  38#include <drm/drm_crtc_helper.h>
  39#include <drm/drm_fb_helper.h>
  40#include <drm/drm_plane_helper.h>
  41#include <drm/drm_probe_helper.h>
  42#include <linux/i2c.h>
  43#include <linux/i2c-algo-bit.h>
  44#include <linux/hrtimer.h>
  45#include "amdgpu_irq.h"
  46
  47#include <drm/drm_dp_mst_helper.h>
  48#include "modules/inc/mod_freesync.h"
  49
  50struct amdgpu_bo;
  51struct amdgpu_device;
  52struct amdgpu_encoder;
  53struct amdgpu_router;
  54struct amdgpu_hpd;
  55
  56#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
  57#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
  58#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
  59#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
  60
  61#define to_dm_plane_state(x)    container_of(x, struct dm_plane_state, base)
  62
  63#define AMDGPU_MAX_HPD_PINS 6
  64#define AMDGPU_MAX_CRTCS 6
  65#define AMDGPU_MAX_PLANES 6
  66#define AMDGPU_MAX_AFMT_BLOCKS 9
  67
  68enum amdgpu_rmx_type {
  69        RMX_OFF,
  70        RMX_FULL,
  71        RMX_CENTER,
  72        RMX_ASPECT
  73};
  74
  75enum amdgpu_underscan_type {
  76        UNDERSCAN_OFF,
  77        UNDERSCAN_ON,
  78        UNDERSCAN_AUTO,
  79};
  80
  81#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
  82#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
  83
  84enum amdgpu_hpd_id {
  85        AMDGPU_HPD_1 = 0,
  86        AMDGPU_HPD_2,
  87        AMDGPU_HPD_3,
  88        AMDGPU_HPD_4,
  89        AMDGPU_HPD_5,
  90        AMDGPU_HPD_6,
  91        AMDGPU_HPD_NONE = 0xff,
  92};
  93
  94enum amdgpu_crtc_irq {
  95        AMDGPU_CRTC_IRQ_VBLANK1 = 0,
  96        AMDGPU_CRTC_IRQ_VBLANK2,
  97        AMDGPU_CRTC_IRQ_VBLANK3,
  98        AMDGPU_CRTC_IRQ_VBLANK4,
  99        AMDGPU_CRTC_IRQ_VBLANK5,
 100        AMDGPU_CRTC_IRQ_VBLANK6,
 101        AMDGPU_CRTC_IRQ_VLINE1,
 102        AMDGPU_CRTC_IRQ_VLINE2,
 103        AMDGPU_CRTC_IRQ_VLINE3,
 104        AMDGPU_CRTC_IRQ_VLINE4,
 105        AMDGPU_CRTC_IRQ_VLINE5,
 106        AMDGPU_CRTC_IRQ_VLINE6,
 107        AMDGPU_CRTC_IRQ_NONE = 0xff
 108};
 109
 110enum amdgpu_pageflip_irq {
 111        AMDGPU_PAGEFLIP_IRQ_D1 = 0,
 112        AMDGPU_PAGEFLIP_IRQ_D2,
 113        AMDGPU_PAGEFLIP_IRQ_D3,
 114        AMDGPU_PAGEFLIP_IRQ_D4,
 115        AMDGPU_PAGEFLIP_IRQ_D5,
 116        AMDGPU_PAGEFLIP_IRQ_D6,
 117        AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
 118};
 119
 120enum amdgpu_flip_status {
 121        AMDGPU_FLIP_NONE,
 122        AMDGPU_FLIP_PENDING,
 123        AMDGPU_FLIP_SUBMITTED
 124};
 125
 126#define AMDGPU_MAX_I2C_BUS 16
 127
 128/* amdgpu gpio-based i2c
 129 * 1. "mask" reg and bits
 130 *    grabs the gpio pins for software use
 131 *    0=not held  1=held
 132 * 2. "a" reg and bits
 133 *    output pin value
 134 *    0=low 1=high
 135 * 3. "en" reg and bits
 136 *    sets the pin direction
 137 *    0=input 1=output
 138 * 4. "y" reg and bits
 139 *    input pin value
 140 *    0=low 1=high
 141 */
 142struct amdgpu_i2c_bus_rec {
 143        bool valid;
 144        /* id used by atom */
 145        uint8_t i2c_id;
 146        /* id used by atom */
 147        enum amdgpu_hpd_id hpd;
 148        /* can be used with hw i2c engine */
 149        bool hw_capable;
 150        /* uses multi-media i2c engine */
 151        bool mm_i2c;
 152        /* regs and bits */
 153        uint32_t mask_clk_reg;
 154        uint32_t mask_data_reg;
 155        uint32_t a_clk_reg;
 156        uint32_t a_data_reg;
 157        uint32_t en_clk_reg;
 158        uint32_t en_data_reg;
 159        uint32_t y_clk_reg;
 160        uint32_t y_data_reg;
 161        uint32_t mask_clk_mask;
 162        uint32_t mask_data_mask;
 163        uint32_t a_clk_mask;
 164        uint32_t a_data_mask;
 165        uint32_t en_clk_mask;
 166        uint32_t en_data_mask;
 167        uint32_t y_clk_mask;
 168        uint32_t y_data_mask;
 169};
 170
 171#define AMDGPU_MAX_BIOS_CONNECTOR 16
 172
 173/* pll flags */
 174#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
 175#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
 176#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
 177#define AMDGPU_PLL_LEGACY               (1 << 3)
 178#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 179#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 180#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 181#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 182#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 183#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 184#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
 185#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 186#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
 187#define AMDGPU_PLL_IS_LCD               (1 << 13)
 188#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 189
 190struct amdgpu_pll {
 191        /* reference frequency */
 192        uint32_t reference_freq;
 193
 194        /* fixed dividers */
 195        uint32_t reference_div;
 196        uint32_t post_div;
 197
 198        /* pll in/out limits */
 199        uint32_t pll_in_min;
 200        uint32_t pll_in_max;
 201        uint32_t pll_out_min;
 202        uint32_t pll_out_max;
 203        uint32_t lcd_pll_out_min;
 204        uint32_t lcd_pll_out_max;
 205        uint32_t best_vco;
 206
 207        /* divider limits */
 208        uint32_t min_ref_div;
 209        uint32_t max_ref_div;
 210        uint32_t min_post_div;
 211        uint32_t max_post_div;
 212        uint32_t min_feedback_div;
 213        uint32_t max_feedback_div;
 214        uint32_t min_frac_feedback_div;
 215        uint32_t max_frac_feedback_div;
 216
 217        /* flags for the current clock */
 218        uint32_t flags;
 219
 220        /* pll id */
 221        uint32_t id;
 222};
 223
 224struct amdgpu_i2c_chan {
 225        struct i2c_adapter adapter;
 226        struct drm_device *dev;
 227        struct i2c_algo_bit_data bit;
 228        struct amdgpu_i2c_bus_rec rec;
 229        struct drm_dp_aux aux;
 230        bool has_aux;
 231        struct mutex mutex;
 232};
 233
 234struct amdgpu_fbdev;
 235
 236struct amdgpu_afmt {
 237        bool enabled;
 238        int offset;
 239        bool last_buffer_filled_status;
 240        int id;
 241        struct amdgpu_audio_pin *pin;
 242};
 243
 244/*
 245 * Audio
 246 */
 247struct amdgpu_audio_pin {
 248        int                     channels;
 249        int                     rate;
 250        int                     bits_per_sample;
 251        u8                      status_bits;
 252        u8                      category_code;
 253        u32                     offset;
 254        bool                    connected;
 255        u32                     id;
 256};
 257
 258struct amdgpu_audio {
 259        bool enabled;
 260        struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
 261        int num_pins;
 262};
 263
 264struct amdgpu_display_funcs {
 265        /* display watermarks */
 266        void (*bandwidth_update)(struct amdgpu_device *adev);
 267        /* get frame count */
 268        u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
 269        /* set backlight level */
 270        void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
 271                                    u8 level);
 272        /* get backlight level */
 273        u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
 274        /* hotplug detect */
 275        bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
 276        void (*hpd_set_polarity)(struct amdgpu_device *adev,
 277                                 enum amdgpu_hpd_id hpd);
 278        u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
 279        /* pageflipping */
 280        void (*page_flip)(struct amdgpu_device *adev,
 281                          int crtc_id, u64 crtc_base, bool async);
 282        int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
 283                                        u32 *vbl, u32 *position);
 284        /* display topology setup */
 285        void (*add_encoder)(struct amdgpu_device *adev,
 286                            uint32_t encoder_enum,
 287                            uint32_t supported_device,
 288                            u16 caps);
 289        void (*add_connector)(struct amdgpu_device *adev,
 290                              uint32_t connector_id,
 291                              uint32_t supported_device,
 292                              int connector_type,
 293                              struct amdgpu_i2c_bus_rec *i2c_bus,
 294                              uint16_t connector_object_id,
 295                              struct amdgpu_hpd *hpd,
 296                              struct amdgpu_router *router);
 297
 298
 299};
 300
 301struct amdgpu_framebuffer {
 302        struct drm_framebuffer base;
 303
 304        /* caching for later use */
 305        uint64_t address;
 306};
 307
 308struct amdgpu_fbdev {
 309        struct drm_fb_helper helper;
 310        struct amdgpu_framebuffer rfb;
 311        struct list_head fbdev_list;
 312        struct amdgpu_device *adev;
 313};
 314
 315struct amdgpu_mode_info {
 316        struct atom_context *atom_context;
 317        struct card_info *atom_card_info;
 318        bool mode_config_initialized;
 319        struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
 320        struct drm_plane *planes[AMDGPU_MAX_PLANES];
 321        struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
 322        /* DVI-I properties */
 323        struct drm_property *coherent_mode_property;
 324        /* DAC enable load detect */
 325        struct drm_property *load_detect_property;
 326        /* underscan */
 327        struct drm_property *underscan_property;
 328        struct drm_property *underscan_hborder_property;
 329        struct drm_property *underscan_vborder_property;
 330        /* audio */
 331        struct drm_property *audio_property;
 332        /* FMT dithering */
 333        struct drm_property *dither_property;
 334        /* Adaptive Backlight Modulation (power feature) */
 335        struct drm_property *abm_level_property;
 336        /* hardcoded DFP edid from BIOS */
 337        struct edid *bios_hardcoded_edid;
 338        int bios_hardcoded_edid_size;
 339
 340        /* pointer to fbdev info structure */
 341        struct amdgpu_fbdev *rfbdev;
 342        /* firmware flags */
 343        u16 firmware_flags;
 344        /* pointer to backlight encoder */
 345        struct amdgpu_encoder *bl_encoder;
 346        u8 bl_level; /* saved backlight level */
 347        struct amdgpu_audio     audio; /* audio stuff */
 348        int                     num_crtc; /* number of crtcs */
 349        int                     num_hpd; /* number of hpd pins */
 350        int                     num_dig; /* number of dig blocks */
 351        int                     disp_priority;
 352        const struct amdgpu_display_funcs *funcs;
 353        const enum drm_plane_type *plane_type;
 354};
 355
 356#define AMDGPU_MAX_BL_LEVEL 0xFF
 357
 358#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 359
 360struct amdgpu_backlight_privdata {
 361        struct amdgpu_encoder *encoder;
 362        uint8_t negative;
 363};
 364
 365#endif
 366
 367struct amdgpu_atom_ss {
 368        uint16_t percentage;
 369        uint16_t percentage_divider;
 370        uint8_t type;
 371        uint16_t step;
 372        uint8_t delay;
 373        uint8_t range;
 374        uint8_t refdiv;
 375        /* asic_ss */
 376        uint16_t rate;
 377        uint16_t amount;
 378};
 379
 380struct amdgpu_crtc {
 381        struct drm_crtc base;
 382        int crtc_id;
 383        bool enabled;
 384        bool can_tile;
 385        uint32_t crtc_offset;
 386        struct drm_gem_object *cursor_bo;
 387        uint64_t cursor_addr;
 388        int cursor_x;
 389        int cursor_y;
 390        int cursor_hot_x;
 391        int cursor_hot_y;
 392        int cursor_width;
 393        int cursor_height;
 394        int max_cursor_width;
 395        int max_cursor_height;
 396        enum amdgpu_rmx_type rmx_type;
 397        u8 h_border;
 398        u8 v_border;
 399        fixed20_12 vsc;
 400        fixed20_12 hsc;
 401        struct drm_display_mode native_mode;
 402        u32 pll_id;
 403        /* page flipping */
 404        struct amdgpu_flip_work *pflip_works;
 405        enum amdgpu_flip_status pflip_status;
 406        int deferred_flip_completion;
 407        u32 last_flip_vblank;
 408        /* pll sharing */
 409        struct amdgpu_atom_ss ss;
 410        bool ss_enabled;
 411        u32 adjusted_clock;
 412        int bpc;
 413        u32 pll_reference_div;
 414        u32 pll_post_div;
 415        u32 pll_flags;
 416        struct drm_encoder *encoder;
 417        struct drm_connector *connector;
 418        /* for dpm */
 419        u32 line_time;
 420        u32 wm_low;
 421        u32 wm_high;
 422        u32 lb_vblank_lead_lines;
 423        struct drm_display_mode hw_mode;
 424        /* for virtual dce */
 425        struct hrtimer vblank_timer;
 426        enum amdgpu_interrupt_state vsync_timer_enabled;
 427
 428        int otg_inst;
 429        struct drm_pending_vblank_event *event;
 430};
 431
 432struct amdgpu_encoder_atom_dig {
 433        bool linkb;
 434        /* atom dig */
 435        bool coherent_mode;
 436        int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 437        /* atom lvds/edp */
 438        uint32_t lcd_misc;
 439        uint16_t panel_pwr_delay;
 440        uint32_t lcd_ss_id;
 441        /* panel mode */
 442        struct drm_display_mode native_mode;
 443        struct backlight_device *bl_dev;
 444        int dpms_mode;
 445        uint8_t backlight_level;
 446        int panel_mode;
 447        struct amdgpu_afmt *afmt;
 448};
 449
 450struct amdgpu_encoder {
 451        struct drm_encoder base;
 452        uint32_t encoder_enum;
 453        uint32_t encoder_id;
 454        uint32_t devices;
 455        uint32_t active_device;
 456        uint32_t flags;
 457        uint32_t pixel_clock;
 458        enum amdgpu_rmx_type rmx_type;
 459        enum amdgpu_underscan_type underscan_type;
 460        uint32_t underscan_hborder;
 461        uint32_t underscan_vborder;
 462        struct drm_display_mode native_mode;
 463        void *enc_priv;
 464        int audio_polling_active;
 465        bool is_ext_encoder;
 466        u16 caps;
 467};
 468
 469struct amdgpu_connector_atom_dig {
 470        /* displayport */
 471        u8 dpcd[DP_RECEIVER_CAP_SIZE];
 472        u8 dp_sink_type;
 473        int dp_clock;
 474        int dp_lane_count;
 475        bool edp_on;
 476};
 477
 478struct amdgpu_gpio_rec {
 479        bool valid;
 480        u8 id;
 481        u32 reg;
 482        u32 mask;
 483        u32 shift;
 484};
 485
 486struct amdgpu_hpd {
 487        enum amdgpu_hpd_id hpd;
 488        u8 plugged_state;
 489        struct amdgpu_gpio_rec gpio;
 490};
 491
 492struct amdgpu_router {
 493        u32 router_id;
 494        struct amdgpu_i2c_bus_rec i2c_info;
 495        u8 i2c_addr;
 496        /* i2c mux */
 497        bool ddc_valid;
 498        u8 ddc_mux_type;
 499        u8 ddc_mux_control_pin;
 500        u8 ddc_mux_state;
 501        /* clock/data mux */
 502        bool cd_valid;
 503        u8 cd_mux_type;
 504        u8 cd_mux_control_pin;
 505        u8 cd_mux_state;
 506};
 507
 508enum amdgpu_connector_audio {
 509        AMDGPU_AUDIO_DISABLE = 0,
 510        AMDGPU_AUDIO_ENABLE = 1,
 511        AMDGPU_AUDIO_AUTO = 2
 512};
 513
 514enum amdgpu_connector_dither {
 515        AMDGPU_FMT_DITHER_DISABLE = 0,
 516        AMDGPU_FMT_DITHER_ENABLE = 1,
 517};
 518
 519struct amdgpu_dm_dp_aux {
 520        struct drm_dp_aux aux;
 521        struct ddc_service *ddc_service;
 522};
 523
 524struct amdgpu_i2c_adapter {
 525        struct i2c_adapter base;
 526
 527        struct ddc_service *ddc_service;
 528};
 529
 530#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
 531
 532struct amdgpu_connector {
 533        struct drm_connector base;
 534        uint32_t connector_id;
 535        uint32_t devices;
 536        struct amdgpu_i2c_chan *ddc_bus;
 537        /* some systems have an hdmi and vga port with a shared ddc line */
 538        bool shared_ddc;
 539        bool use_digital;
 540        /* we need to mind the EDID between detect
 541           and get modes due to analog/digital/tvencoder */
 542        struct edid *edid;
 543        void *con_priv;
 544        bool dac_load_detect;
 545        bool detected_by_load; /* if the connection status was determined by load */
 546        uint16_t connector_object_id;
 547        struct amdgpu_hpd hpd;
 548        struct amdgpu_router router;
 549        struct amdgpu_i2c_chan *router_bus;
 550        enum amdgpu_connector_audio audio;
 551        enum amdgpu_connector_dither dither;
 552        unsigned pixelclock_for_modeset;
 553};
 554
 555/* TODO: start to use this struct and remove same field from base one */
 556struct amdgpu_mst_connector {
 557        struct amdgpu_connector base;
 558
 559        struct drm_dp_mst_topology_mgr mst_mgr;
 560        struct amdgpu_dm_dp_aux dm_dp_aux;
 561        struct drm_dp_mst_port *port;
 562        struct amdgpu_connector *mst_port;
 563        bool is_mst_connector;
 564        struct amdgpu_encoder *mst_encoder;
 565};
 566
 567#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 568                                ((em) == ATOM_ENCODER_MODE_DP_MST))
 569
 570/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
 571#define DRM_SCANOUTPOS_VALID        (1 << 0)
 572#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
 573#define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
 574#define USE_REAL_VBLANKSTART            (1 << 30)
 575#define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 576
 577void amdgpu_link_encoder_connector(struct drm_device *dev);
 578
 579struct drm_connector *
 580amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
 581struct drm_connector *
 582amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
 583bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
 584                                    u32 pixel_clock);
 585
 586u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 587struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
 588
 589bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 590                              bool use_aux);
 591
 592void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
 593
 594int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
 595                        unsigned int pipe, unsigned int flags, int *vpos,
 596                        int *hpos, ktime_t *stime, ktime_t *etime,
 597                        const struct drm_display_mode *mode);
 598
 599int amdgpu_display_framebuffer_init(struct drm_device *dev,
 600                                    struct amdgpu_framebuffer *rfb,
 601                                    const struct drm_mode_fb_cmd2 *mode_cmd,
 602                                    struct drm_gem_object *obj);
 603
 604int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 605
 606void amdgpu_enc_destroy(struct drm_encoder *encoder);
 607void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 608bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 609                                const struct drm_display_mode *mode,
 610                                struct drm_display_mode *adjusted_mode);
 611void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
 612                             struct drm_display_mode *adjusted_mode);
 613int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
 614
 615/* fbdev layer */
 616int amdgpu_fbdev_init(struct amdgpu_device *adev);
 617void amdgpu_fbdev_fini(struct amdgpu_device *adev);
 618void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
 619int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
 620bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
 621
 622int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
 623
 624/* amdgpu_display.c */
 625void amdgpu_display_print_display_setup(struct drm_device *dev);
 626int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
 627int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 628                                   struct drm_modeset_acquire_ctx *ctx);
 629int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 630                                struct drm_framebuffer *fb,
 631                                struct drm_pending_vblank_event *event,
 632                                uint32_t page_flip_flags, uint32_t target,
 633                                struct drm_modeset_acquire_ctx *ctx);
 634extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
 635
 636#endif
 637