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24#ifndef __AMDGPU_VCN_H__
25#define __AMDGPU_VCN_H__
26
27#define AMDGPU_VCN_STACK_SIZE (128*1024)
28#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
29
30#define AMDGPU_VCN_FIRMWARE_OFFSET 256
31#define AMDGPU_VCN_MAX_ENC_RINGS 3
32
33#define VCN_DEC_KMD_CMD 0x80000000
34#define VCN_DEC_CMD_FENCE 0x00000000
35#define VCN_DEC_CMD_TRAP 0x00000001
36#define VCN_DEC_CMD_WRITE_REG 0x00000004
37#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
38#define VCN_DEC_CMD_PACKET_START 0x0000000a
39#define VCN_DEC_CMD_PACKET_END 0x0000000b
40
41#define VCN_ENC_CMD_NO_OP 0x00000000
42#define VCN_ENC_CMD_END 0x00000001
43#define VCN_ENC_CMD_IB 0x00000002
44#define VCN_ENC_CMD_FENCE 0x00000003
45#define VCN_ENC_CMD_TRAP 0x00000004
46#define VCN_ENC_CMD_REG_WRITE 0x0000000b
47#define VCN_ENC_CMD_REG_WAIT 0x0000000c
48
49#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
50#define VCN_AON_SOC_ADDRESS_2_0 0x1f800
51#define VCN_VID_IP_ADDRESS_2_0 0x0
52#define VCN_AON_IP_ADDRESS_2_0 0x30000
53
54#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
55 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
56 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
57 UVD_DPG_LMA_CTL__MASK_EN_MASK | \
58 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
59 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
60 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
61 RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
62 })
63
64#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
65 do { \
66 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
67 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
68 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
69 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
70 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
71 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
72 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
73 } while (0)
74
75#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \
76 ({ \
77 uint32_t internal_reg_offset, addr; \
78 bool video_range, aon_range; \
79 \
80 addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
81 addr <<= 2; \
82 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
83 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
84 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \
85 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \
86 if (video_range) \
87 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \
88 (VCN_VID_IP_ADDRESS_2_0)); \
89 else if (aon_range) \
90 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \
91 (VCN_AON_IP_ADDRESS_2_0)); \
92 else \
93 internal_reg_offset = (0xFFFFF & addr); \
94 \
95 internal_reg_offset >>= 2; \
96 })
97
98#define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) \
99 ({ \
100 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
101 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
102 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
103 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
104 RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); \
105 })
106
107#define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect) \
108 do { \
109 if (!indirect) { \
110 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); \
111 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
112 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
113 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
114 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
115 } else { \
116 *adev->vcn.dpg_sram_curr_addr++ = offset; \
117 *adev->vcn.dpg_sram_curr_addr++ = value; \
118 } \
119 } while (0)
120
121enum engine_status_constants {
122 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
123 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
124 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
125 UVD_STATUS__UVD_BUSY = 0x00000004,
126 GB_ADDR_CONFIG_DEFAULT = 0x26010011,
127 UVD_STATUS__IDLE = 0x2,
128 UVD_STATUS__BUSY = 0x5,
129 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
130 UVD_STATUS__RBC_BUSY = 0x1,
131 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
132};
133
134enum internal_dpg_state {
135 VCN_DPG_STATE__UNPAUSE = 0,
136 VCN_DPG_STATE__PAUSE,
137};
138
139struct dpg_pause_state {
140 enum internal_dpg_state fw_based;
141 enum internal_dpg_state jpeg;
142};
143
144struct amdgpu_vcn_reg{
145 unsigned data0;
146 unsigned data1;
147 unsigned cmd;
148 unsigned nop;
149 unsigned scratch9;
150 unsigned jpeg_pitch;
151};
152
153struct amdgpu_vcn {
154 struct amdgpu_bo *vcpu_bo;
155 void *cpu_addr;
156 uint64_t gpu_addr;
157 unsigned fw_version;
158 void *saved_bo;
159 struct delayed_work idle_work;
160 const struct firmware *fw;
161 struct amdgpu_ring ring_dec;
162 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
163 struct amdgpu_ring ring_jpeg;
164 struct amdgpu_irq_src irq;
165 unsigned num_enc_rings;
166 enum amd_powergating_state cur_state;
167 struct dpg_pause_state pause_state;
168 struct amdgpu_vcn_reg internal, external;
169 int (*pause_dpg_mode)(struct amdgpu_device *adev,
170 struct dpg_pause_state *new_state);
171
172 bool indirect_sram;
173 struct amdgpu_bo *dpg_sram_bo;
174 void *dpg_sram_cpu_addr;
175 uint64_t dpg_sram_gpu_addr;
176 uint32_t *dpg_sram_curr_addr;
177};
178
179int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
180int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
181int amdgpu_vcn_suspend(struct amdgpu_device *adev);
182int amdgpu_vcn_resume(struct amdgpu_device *adev);
183void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
184void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
185
186int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
187int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
188
189int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
190int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
191
192int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
193int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
194
195#endif
196
