LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Christian König
  23 */
  24#ifndef __AMDGPU_VM_H__
  25#define __AMDGPU_VM_H__
  26
  27#include <linux/idr.h>
  28#include <linux/kfifo.h>
  29#include <linux/rbtree.h>
  30#include <drm/gpu_scheduler.h>
  31#include <drm/drm_file.h>
  32#include <drm/ttm/ttm_bo_driver.h>
  33
  34#include "amdgpu_sync.h"
  35#include "amdgpu_ring.h"
  36#include "amdgpu_ids.h"
  37
  38struct amdgpu_bo_va;
  39struct amdgpu_job;
  40struct amdgpu_bo_list_entry;
  41
  42/*
  43 * GPUVM handling
  44 */
  45
  46/* Maximum number of PTEs the hardware can write with one command */
  47#define AMDGPU_VM_MAX_UPDATE_SIZE       0x3FFFF
  48
  49/* number of entries in page table */
  50#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
  51
  52#define AMDGPU_PTE_VALID        (1ULL << 0)
  53#define AMDGPU_PTE_SYSTEM       (1ULL << 1)
  54#define AMDGPU_PTE_SNOOPED      (1ULL << 2)
  55
  56/* VI only */
  57#define AMDGPU_PTE_EXECUTABLE   (1ULL << 4)
  58
  59#define AMDGPU_PTE_READABLE     (1ULL << 5)
  60#define AMDGPU_PTE_WRITEABLE    (1ULL << 6)
  61
  62#define AMDGPU_PTE_FRAG(x)      ((x & 0x1fULL) << 7)
  63
  64/* TILED for VEGA10, reserved for older ASICs  */
  65#define AMDGPU_PTE_PRT          (1ULL << 51)
  66
  67/* PDE is handled as PTE for VEGA10 */
  68#define AMDGPU_PDE_PTE          (1ULL << 54)
  69
  70#define AMDGPU_PTE_LOG          (1ULL << 55)
  71
  72/* PTE is handled as PDE for VEGA10 (Translate Further) */
  73#define AMDGPU_PTE_TF           (1ULL << 56)
  74
  75/* PDE Block Fragment Size for VEGA10 */
  76#define AMDGPU_PDE_BFS(a)       ((uint64_t)a << 59)
  77
  78
  79/* For GFX9 */
  80#define AMDGPU_PTE_MTYPE_VG10(a)        ((uint64_t)(a) << 57)
  81#define AMDGPU_PTE_MTYPE_VG10_MASK      AMDGPU_PTE_MTYPE_VG10(3ULL)
  82
  83#define AMDGPU_MTYPE_NC 0
  84#define AMDGPU_MTYPE_CC 2
  85
  86#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
  87                                | AMDGPU_PTE_SNOOPED    \
  88                                | AMDGPU_PTE_EXECUTABLE \
  89                                | AMDGPU_PTE_READABLE   \
  90                                | AMDGPU_PTE_WRITEABLE  \
  91                                | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
  92
  93/* NAVI10 only */
  94#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
  95#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
  96
  97/* How to programm VM fault handling */
  98#define AMDGPU_VM_FAULT_STOP_NEVER      0
  99#define AMDGPU_VM_FAULT_STOP_FIRST      1
 100#define AMDGPU_VM_FAULT_STOP_ALWAYS     2
 101
 102/* max number of VMHUB */
 103#define AMDGPU_MAX_VMHUBS                       2
 104#define AMDGPU_GFXHUB                           0
 105#define AMDGPU_MMHUB                            1
 106
 107/* hardcode that limit for now */
 108#define AMDGPU_VA_RESERVED_SIZE                 (1ULL << 20)
 109
 110/* max vmids dedicated for process */
 111#define AMDGPU_VM_MAX_RESERVED_VMID     1
 112
 113#define AMDGPU_VM_CONTEXT_GFX 0
 114#define AMDGPU_VM_CONTEXT_COMPUTE 1
 115
 116/* See vm_update_mode */
 117#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
 118#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
 119
 120/* VMPT level enumerate, and the hiberachy is:
 121 * PDB2->PDB1->PDB0->PTB
 122 */
 123enum amdgpu_vm_level {
 124        AMDGPU_VM_PDB2,
 125        AMDGPU_VM_PDB1,
 126        AMDGPU_VM_PDB0,
 127        AMDGPU_VM_PTB
 128};
 129
 130/* base structure for tracking BO usage in a VM */
 131struct amdgpu_vm_bo_base {
 132        /* constant after initialization */
 133        struct amdgpu_vm                *vm;
 134        struct amdgpu_bo                *bo;
 135
 136        /* protected by bo being reserved */
 137        struct amdgpu_vm_bo_base        *next;
 138
 139        /* protected by spinlock */
 140        struct list_head                vm_status;
 141
 142        /* protected by the BO being reserved */
 143        bool                            moved;
 144};
 145
 146struct amdgpu_vm_pt {
 147        struct amdgpu_vm_bo_base        base;
 148
 149        /* array of page tables, one for each directory entry */
 150        struct amdgpu_vm_pt             *entries;
 151};
 152
 153/* provided by hw blocks that can write ptes, e.g., sdma */
 154struct amdgpu_vm_pte_funcs {
 155        /* number of dw to reserve per operation */
 156        unsigned        copy_pte_num_dw;
 157
 158        /* copy pte entries from GART */
 159        void (*copy_pte)(struct amdgpu_ib *ib,
 160                         uint64_t pe, uint64_t src,
 161                         unsigned count);
 162
 163        /* write pte one entry at a time with addr mapping */
 164        void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
 165                          uint64_t value, unsigned count,
 166                          uint32_t incr);
 167        /* for linear pte/pde updates without addr mapping */
 168        void (*set_pte_pde)(struct amdgpu_ib *ib,
 169                            uint64_t pe,
 170                            uint64_t addr, unsigned count,
 171                            uint32_t incr, uint64_t flags);
 172};
 173
 174struct amdgpu_task_info {
 175        char    process_name[TASK_COMM_LEN];
 176        char    task_name[TASK_COMM_LEN];
 177        pid_t   pid;
 178        pid_t   tgid;
 179};
 180
 181/**
 182 * struct amdgpu_vm_update_params
 183 *
 184 * Encapsulate some VM table update parameters to reduce
 185 * the number of function parameters
 186 *
 187 */
 188struct amdgpu_vm_update_params {
 189
 190        /**
 191         * @adev: amdgpu device we do this update for
 192         */
 193        struct amdgpu_device *adev;
 194
 195        /**
 196         * @vm: optional amdgpu_vm we do this update for
 197         */
 198        struct amdgpu_vm *vm;
 199
 200        /**
 201         * @pages_addr:
 202         *
 203         * DMA addresses to use for mapping
 204         */
 205        dma_addr_t *pages_addr;
 206
 207        /**
 208         * @job: job to used for hw submission
 209         */
 210        struct amdgpu_job *job;
 211
 212        /**
 213         * @num_dw_left: number of dw left for the IB
 214         */
 215        unsigned int num_dw_left;
 216};
 217
 218struct amdgpu_vm_update_funcs {
 219        int (*map_table)(struct amdgpu_bo *bo);
 220        int (*prepare)(struct amdgpu_vm_update_params *p, void * owner,
 221                       struct dma_fence *exclusive);
 222        int (*update)(struct amdgpu_vm_update_params *p,
 223                      struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
 224                      unsigned count, uint32_t incr, uint64_t flags);
 225        int (*commit)(struct amdgpu_vm_update_params *p,
 226                      struct dma_fence **fence);
 227};
 228
 229struct amdgpu_vm {
 230        /* tree of virtual addresses mapped */
 231        struct rb_root_cached   va;
 232
 233        /* BOs who needs a validation */
 234        struct list_head        evicted;
 235
 236        /* PT BOs which relocated and their parent need an update */
 237        struct list_head        relocated;
 238
 239        /* per VM BOs moved, but not yet updated in the PT */
 240        struct list_head        moved;
 241
 242        /* All BOs of this VM not currently in the state machine */
 243        struct list_head        idle;
 244
 245        /* regular invalidated BOs, but not yet updated in the PT */
 246        struct list_head        invalidated;
 247        spinlock_t              invalidated_lock;
 248
 249        /* BO mappings freed, but not yet updated in the PT */
 250        struct list_head        freed;
 251
 252        /* contains the page directory */
 253        struct amdgpu_vm_pt     root;
 254        struct dma_fence        *last_update;
 255
 256        /* Scheduler entity for page table updates */
 257        struct drm_sched_entity entity;
 258
 259        unsigned int            pasid;
 260        /* dedicated to vm */
 261        struct amdgpu_vmid      *reserved_vmid[AMDGPU_MAX_VMHUBS];
 262
 263        /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
 264        bool                                    use_cpu_for_update;
 265
 266        /* Functions to use for VM table updates */
 267        const struct amdgpu_vm_update_funcs     *update_funcs;
 268
 269        /* Flag to indicate ATS support from PTE for GFX9 */
 270        bool                    pte_support_ats;
 271
 272        /* Up to 128 pending retry page faults */
 273        DECLARE_KFIFO(faults, u64, 128);
 274
 275        /* Points to the KFD process VM info */
 276        struct amdkfd_process_info *process_info;
 277
 278        /* List node in amdkfd_process_info.vm_list_head */
 279        struct list_head        vm_list_node;
 280
 281        /* Valid while the PD is reserved or fenced */
 282        uint64_t                pd_phys_addr;
 283
 284        /* Some basic info about the task */
 285        struct amdgpu_task_info task_info;
 286
 287        /* Store positions of group of BOs */
 288        struct ttm_lru_bulk_move lru_bulk_move;
 289        /* mark whether can do the bulk move */
 290        bool                    bulk_moveable;
 291};
 292
 293struct amdgpu_vm_manager {
 294        /* Handling of VMIDs */
 295        struct amdgpu_vmid_mgr                  id_mgr[AMDGPU_MAX_VMHUBS];
 296
 297        /* Handling of VM fences */
 298        u64                                     fence_context;
 299        unsigned                                seqno[AMDGPU_MAX_RINGS];
 300
 301        uint64_t                                max_pfn;
 302        uint32_t                                num_level;
 303        uint32_t                                block_size;
 304        uint32_t                                fragment_size;
 305        enum amdgpu_vm_level                    root_level;
 306        /* vram base address for page table entry  */
 307        u64                                     vram_base_offset;
 308        /* vm pte handling */
 309        const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
 310        struct drm_sched_rq                     *vm_pte_rqs[AMDGPU_MAX_RINGS];
 311        unsigned                                vm_pte_num_rqs;
 312        struct amdgpu_ring                      *page_fault;
 313
 314        /* partial resident texture handling */
 315        spinlock_t                              prt_lock;
 316        atomic_t                                num_prt_users;
 317
 318        /* controls how VM page tables are updated for Graphics and Compute.
 319         * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
 320         * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
 321         */
 322        int                                     vm_update_mode;
 323
 324        /* PASID to VM mapping, will be used in interrupt context to
 325         * look up VM of a page fault
 326         */
 327        struct idr                              pasid_idr;
 328        spinlock_t                              pasid_lock;
 329
 330        /* counter of mapped memory through xgmi */
 331        uint32_t                                xgmi_map_counter;
 332        struct mutex                            lock_pstate;
 333};
 334
 335#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
 336#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 337#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
 338
 339extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
 340extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
 341
 342void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 343void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
 344
 345long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
 346int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 347                   int vm_context, unsigned int pasid);
 348int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
 349void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 350void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 351void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 352                         struct list_head *validated,
 353                         struct amdgpu_bo_list_entry *entry);
 354bool amdgpu_vm_ready(struct amdgpu_vm *vm);
 355int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 356                              int (*callback)(void *p, struct amdgpu_bo *bo),
 357                              void *param);
 358int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
 359int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 360                                 struct amdgpu_vm *vm);
 361int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 362                          struct amdgpu_vm *vm,
 363                          struct dma_fence **fence);
 364int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 365                           struct amdgpu_vm *vm);
 366int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 367                        struct amdgpu_bo_va *bo_va,
 368                        bool clear);
 369void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 370                             struct amdgpu_bo *bo, bool evicted);
 371uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
 372struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 373                                       struct amdgpu_bo *bo);
 374struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
 375                                      struct amdgpu_vm *vm,
 376                                      struct amdgpu_bo *bo);
 377int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 378                     struct amdgpu_bo_va *bo_va,
 379                     uint64_t addr, uint64_t offset,
 380                     uint64_t size, uint64_t flags);
 381int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
 382                             struct amdgpu_bo_va *bo_va,
 383                             uint64_t addr, uint64_t offset,
 384                             uint64_t size, uint64_t flags);
 385int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
 386                       struct amdgpu_bo_va *bo_va,
 387                       uint64_t addr);
 388int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 389                                struct amdgpu_vm *vm,
 390                                uint64_t saddr, uint64_t size);
 391struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
 392                                                         uint64_t addr);
 393void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
 394void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 395                      struct amdgpu_bo_va *bo_va);
 396void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
 397                           uint32_t fragment_size_default, unsigned max_level,
 398                           unsigned max_bits);
 399int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 400bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
 401                                  struct amdgpu_job *job);
 402void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
 403
 404void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
 405                             struct amdgpu_task_info *task_info);
 406
 407void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
 408
 409void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 410                                struct amdgpu_vm *vm);
 411void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
 412
 413#endif
 414