LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v10

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Author: Huang Rui
  23 *
  24 */
  25
  26#include <linux/firmware.h>
  27#include <linux/module.h>
  28#include <linux/pci.h>
  29
  30#include "amdgpu.h"
  31#include "amdgpu_psp.h"
  32#include "amdgpu_ucode.h"
  33#include "soc15_common.h"
  34#include "psp_v10_0.h"
  35
  36#include "mp/mp_10_0_offset.h"
  37#include "gc/gc_9_1_offset.h"
  38#include "sdma0/sdma0_4_1_offset.h"
  39
  40MODULE_FIRMWARE("amdgpu/raven_asd.bin");
  41MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
  42MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
  43
  44static int psp_v10_0_init_microcode(struct psp_context *psp)
  45{
  46        struct amdgpu_device *adev = psp->adev;
  47        const char *chip_name;
  48        char fw_name[30];
  49        int err = 0;
  50        const struct psp_firmware_header_v1_0 *hdr;
  51
  52        DRM_DEBUG("\n");
  53
  54        switch (adev->asic_type) {
  55        case CHIP_RAVEN:
  56                if (adev->rev_id >= 0x8)
  57                        chip_name = "raven2";
  58                else if (adev->pdev->device == 0x15d8)
  59                        chip_name = "picasso";
  60                else
  61                        chip_name = "raven";
  62                break;
  63        default: BUG();
  64        }
  65
  66        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
  67        err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
  68        if (err)
  69                goto out;
  70
  71        err = amdgpu_ucode_validate(adev->psp.asd_fw);
  72        if (err)
  73                goto out;
  74
  75        hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
  76        adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
  77        adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
  78        adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
  79        adev->psp.asd_start_addr = (uint8_t *)hdr +
  80                                le32_to_cpu(hdr->header.ucode_array_offset_bytes);
  81
  82        return 0;
  83out:
  84        if (err) {
  85                dev_err(adev->dev,
  86                        "psp v10.0: Failed to load firmware \"%s\"\n",
  87                        fw_name);
  88                release_firmware(adev->psp.asd_fw);
  89                adev->psp.asd_fw = NULL;
  90        }
  91
  92        return err;
  93}
  94
  95static int psp_v10_0_ring_init(struct psp_context *psp,
  96                               enum psp_ring_type ring_type)
  97{
  98        int ret = 0;
  99        struct psp_ring *ring;
 100        struct amdgpu_device *adev = psp->adev;
 101
 102        ring = &psp->km_ring;
 103
 104        ring->ring_type = ring_type;
 105
 106        /* allocate 4k Page of Local Frame Buffer memory for ring */
 107        ring->ring_size = 0x1000;
 108        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 109                                      AMDGPU_GEM_DOMAIN_VRAM,
 110                                      &adev->firmware.rbuf,
 111                                      &ring->ring_mem_mc_addr,
 112                                      (void **)&ring->ring_mem);
 113        if (ret) {
 114                ring->ring_size = 0;
 115                return ret;
 116        }
 117
 118        return 0;
 119}
 120
 121static int psp_v10_0_ring_create(struct psp_context *psp,
 122                                 enum psp_ring_type ring_type)
 123{
 124        int ret = 0;
 125        unsigned int psp_ring_reg = 0;
 126        struct psp_ring *ring = &psp->km_ring;
 127        struct amdgpu_device *adev = psp->adev;
 128
 129        /* Write low address of the ring to C2PMSG_69 */
 130        psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 131        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 132        /* Write high address of the ring to C2PMSG_70 */
 133        psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 134        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 135        /* Write size of ring to C2PMSG_71 */
 136        psp_ring_reg = ring->ring_size;
 137        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 138        /* Write the ring initialization command to C2PMSG_64 */
 139        psp_ring_reg = ring_type;
 140        psp_ring_reg = psp_ring_reg << 16;
 141        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 142
 143        /* There might be handshake issue with hardware which needs delay */
 144        mdelay(20);
 145
 146        /* Wait for response flag (bit 31) in C2PMSG_64 */
 147        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 148                           0x80000000, 0x8000FFFF, false);
 149
 150        return ret;
 151}
 152
 153static int psp_v10_0_ring_stop(struct psp_context *psp,
 154                               enum psp_ring_type ring_type)
 155{
 156        int ret = 0;
 157        unsigned int psp_ring_reg = 0;
 158        struct amdgpu_device *adev = psp->adev;
 159
 160        /* Write the ring destroy command to C2PMSG_64 */
 161        psp_ring_reg = 3 << 16;
 162        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 163
 164        /* There might be handshake issue with hardware which needs delay */
 165        mdelay(20);
 166
 167        /* Wait for response flag (bit 31) in C2PMSG_64 */
 168        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 169                           0x80000000, 0x80000000, false);
 170
 171        return ret;
 172}
 173
 174static int psp_v10_0_ring_destroy(struct psp_context *psp,
 175                                  enum psp_ring_type ring_type)
 176{
 177        int ret = 0;
 178        struct psp_ring *ring = &psp->km_ring;
 179        struct amdgpu_device *adev = psp->adev;
 180
 181        ret = psp_v10_0_ring_stop(psp, ring_type);
 182        if (ret)
 183                DRM_ERROR("Fail to stop psp ring\n");
 184
 185        amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 186                              &ring->ring_mem_mc_addr,
 187                              (void **)&ring->ring_mem);
 188
 189        return ret;
 190}
 191
 192static int psp_v10_0_cmd_submit(struct psp_context *psp,
 193                                struct amdgpu_firmware_info *ucode,
 194                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 195                                int index)
 196{
 197        unsigned int psp_write_ptr_reg = 0;
 198        struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 199        struct psp_ring *ring = &psp->km_ring;
 200        struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 201        struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 202                ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 203        struct amdgpu_device *adev = psp->adev;
 204        uint32_t ring_size_dw = ring->ring_size / 4;
 205        uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 206
 207        /* KM (GPCOM) prepare write pointer */
 208        psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 209
 210        /* Update KM RB frame pointer to new frame */
 211        if ((psp_write_ptr_reg % ring_size_dw) == 0)
 212                write_frame = ring_buffer_start;
 213        else
 214                write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 215        /* Check invalid write_frame ptr address */
 216        if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 217                DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 218                          ring_buffer_start, ring_buffer_end, write_frame);
 219                DRM_ERROR("write_frame is pointing to address out of bounds\n");
 220                return -EINVAL;
 221        }
 222
 223        /* Initialize KM RB frame */
 224        memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 225
 226        /* Update KM RB frame */
 227        write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 228        write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 229        write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 230        write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 231        write_frame->fence_value = index;
 232
 233        /* Update the write Pointer in DWORDs */
 234        psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 235        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 236
 237        return 0;
 238}
 239
 240static int
 241psp_v10_0_sram_map(struct amdgpu_device *adev,
 242                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 243                   unsigned int *sram_data_reg_offset,
 244                   enum AMDGPU_UCODE_ID ucode_id)
 245{
 246        int ret = 0;
 247
 248        switch(ucode_id) {
 249/* TODO: needs to confirm */
 250#if 0
 251        case AMDGPU_UCODE_ID_SMC:
 252                *sram_offset = 0;
 253                *sram_addr_reg_offset = 0;
 254                *sram_data_reg_offset = 0;
 255                break;
 256#endif
 257
 258        case AMDGPU_UCODE_ID_CP_CE:
 259                *sram_offset = 0x0;
 260                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 261                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 262                break;
 263
 264        case AMDGPU_UCODE_ID_CP_PFP:
 265                *sram_offset = 0x0;
 266                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 267                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 268                break;
 269
 270        case AMDGPU_UCODE_ID_CP_ME:
 271                *sram_offset = 0x0;
 272                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 273                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 274                break;
 275
 276        case AMDGPU_UCODE_ID_CP_MEC1:
 277                *sram_offset = 0x10000;
 278                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 279                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 280                break;
 281
 282        case AMDGPU_UCODE_ID_CP_MEC2:
 283                *sram_offset = 0x10000;
 284                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 285                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 286                break;
 287
 288        case AMDGPU_UCODE_ID_RLC_G:
 289                *sram_offset = 0x2000;
 290                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 291                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 292                break;
 293
 294        case AMDGPU_UCODE_ID_SDMA0:
 295                *sram_offset = 0x0;
 296                *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 297                *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 298                break;
 299
 300/* TODO: needs to confirm */
 301#if 0
 302        case AMDGPU_UCODE_ID_SDMA1:
 303                *sram_offset = ;
 304                *sram_addr_reg_offset = ;
 305                break;
 306
 307        case AMDGPU_UCODE_ID_UVD:
 308                *sram_offset = ;
 309                *sram_addr_reg_offset = ;
 310                break;
 311
 312        case AMDGPU_UCODE_ID_VCE:
 313                *sram_offset = ;
 314                *sram_addr_reg_offset = ;
 315                break;
 316#endif
 317
 318        case AMDGPU_UCODE_ID_MAXIMUM:
 319        default:
 320                ret = -EINVAL;
 321                break;
 322        }
 323
 324        return ret;
 325}
 326
 327static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 328                                        struct amdgpu_firmware_info *ucode,
 329                                        enum AMDGPU_UCODE_ID ucode_type)
 330{
 331        int err = 0;
 332        unsigned int fw_sram_reg_val = 0;
 333        unsigned int fw_sram_addr_reg_offset = 0;
 334        unsigned int fw_sram_data_reg_offset = 0;
 335        unsigned int ucode_size;
 336        uint32_t *ucode_mem = NULL;
 337        struct amdgpu_device *adev = psp->adev;
 338
 339        err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 340                                &fw_sram_data_reg_offset, ucode_type);
 341        if (err)
 342                return false;
 343
 344        WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 345
 346        ucode_size = ucode->ucode_size;
 347        ucode_mem = (uint32_t *)ucode->kaddr;
 348        while (!ucode_size) {
 349                fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 350
 351                if (*ucode_mem != fw_sram_reg_val)
 352                        return false;
 353
 354                ucode_mem++;
 355                /* 4 bytes */
 356                ucode_size -= 4;
 357        }
 358
 359        return true;
 360}
 361
 362
 363static int psp_v10_0_mode1_reset(struct psp_context *psp)
 364{
 365        DRM_INFO("psp mode 1 reset not supported now! \n");
 366        return -EINVAL;
 367}
 368
 369static const struct psp_funcs psp_v10_0_funcs = {
 370        .init_microcode = psp_v10_0_init_microcode,
 371        .ring_init = psp_v10_0_ring_init,
 372        .ring_create = psp_v10_0_ring_create,
 373        .ring_stop = psp_v10_0_ring_stop,
 374        .ring_destroy = psp_v10_0_ring_destroy,
 375        .cmd_submit = psp_v10_0_cmd_submit,
 376        .compare_sram_data = psp_v10_0_compare_sram_data,
 377        .mode1_reset = psp_v10_0_mode1_reset,
 378};
 379
 380void psp_v10_0_set_psp_funcs(struct psp_context *psp)
 381{
 382        psp->funcs = &psp_v10_0_funcs;
 383}
 384