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24#include "kfd_kernel_queue.h"
25#include "kfd_device_queue_manager.h"
26#include "kfd_pm4_headers_ai.h"
27#include "kfd_pm4_opcodes.h"
28
29static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
30 enum kfd_queue_type type, unsigned int queue_size);
31static void uninitialize_v9(struct kernel_queue *kq);
32static void submit_packet_v9(struct kernel_queue *kq);
33
34void kernel_queue_init_v9(struct kernel_queue_ops *ops)
35{
36 ops->initialize = initialize_v9;
37 ops->uninitialize = uninitialize_v9;
38 ops->submit_packet = submit_packet_v9;
39}
40
41static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
42 enum kfd_queue_type type, unsigned int queue_size)
43{
44 int retval;
45
46 retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
47 if (retval)
48 return false;
49
50 kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
51 kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
52
53 memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
54
55 return true;
56}
57
58static void uninitialize_v9(struct kernel_queue *kq)
59{
60 kfd_gtt_sa_free(kq->dev, kq->eop_mem);
61}
62
63static void submit_packet_v9(struct kernel_queue *kq)
64{
65 *kq->wptr64_kernel = kq->pending_wptr64;
66 write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
67 kq->pending_wptr64);
68}
69
70static int pm_map_process_v9(struct packet_manager *pm,
71 uint32_t *buffer, struct qcm_process_device *qpd)
72{
73 struct pm4_mes_map_process *packet;
74 uint64_t vm_page_table_base_addr = qpd->page_table_base;
75
76 packet = (struct pm4_mes_map_process *)buffer;
77 memset(buffer, 0, sizeof(struct pm4_mes_map_process));
78
79 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
80 sizeof(struct pm4_mes_map_process));
81 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
82 packet->bitfields2.process_quantum = 1;
83 packet->bitfields2.pasid = qpd->pqm->process->pasid;
84 packet->bitfields14.gds_size = qpd->gds_size;
85 packet->bitfields14.num_gws = qpd->num_gws;
86 packet->bitfields14.num_oac = qpd->num_oac;
87 packet->bitfields14.sdma_enable = 1;
88 packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
89
90 packet->sh_mem_config = qpd->sh_mem_config;
91 packet->sh_mem_bases = qpd->sh_mem_bases;
92 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
93 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
94 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
95 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
96
97 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
98 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
99
100 packet->vm_context_page_table_base_addr_lo32 =
101 lower_32_bits(vm_page_table_base_addr);
102 packet->vm_context_page_table_base_addr_hi32 =
103 upper_32_bits(vm_page_table_base_addr);
104
105 return 0;
106}
107
108static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
109 uint64_t ib, size_t ib_size_in_dwords, bool chain)
110{
111 struct pm4_mes_runlist *packet;
112
113 int concurrent_proc_cnt = 0;
114 struct kfd_dev *kfd = pm->dqm->dev;
115
116
117
118
119
120
121
122
123
124
125 concurrent_proc_cnt = min(pm->dqm->processes_count,
126 kfd->max_proc_per_quantum);
127
128 packet = (struct pm4_mes_runlist *)buffer;
129
130 memset(buffer, 0, sizeof(struct pm4_mes_runlist));
131 packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
132 sizeof(struct pm4_mes_runlist));
133
134 packet->bitfields4.ib_size = ib_size_in_dwords;
135 packet->bitfields4.chain = chain ? 1 : 0;
136 packet->bitfields4.offload_polling = 0;
137 packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0;
138 packet->bitfields4.valid = 1;
139 packet->bitfields4.process_cnt = concurrent_proc_cnt;
140 packet->ordinal2 = lower_32_bits(ib);
141 packet->ib_base_hi = upper_32_bits(ib);
142
143 return 0;
144}
145
146static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
147 struct queue *q, bool is_static)
148{
149 struct pm4_mes_map_queues *packet;
150 bool use_static = is_static;
151
152 packet = (struct pm4_mes_map_queues *)buffer;
153 memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
154
155 packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
156 sizeof(struct pm4_mes_map_queues));
157 packet->bitfields2.num_queues = 1;
158 packet->bitfields2.queue_sel =
159 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
160
161 packet->bitfields2.engine_sel =
162 engine_sel__mes_map_queues__compute_vi;
163 packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
164 packet->bitfields2.queue_type =
165 queue_type__mes_map_queues__normal_compute_vi;
166
167 switch (q->properties.type) {
168 case KFD_QUEUE_TYPE_COMPUTE:
169 if (use_static)
170 packet->bitfields2.queue_type =
171 queue_type__mes_map_queues__normal_latency_static_queue_vi;
172 break;
173 case KFD_QUEUE_TYPE_DIQ:
174 packet->bitfields2.queue_type =
175 queue_type__mes_map_queues__debug_interface_queue_vi;
176 break;
177 case KFD_QUEUE_TYPE_SDMA:
178 case KFD_QUEUE_TYPE_SDMA_XGMI:
179 packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
180 engine_sel__mes_map_queues__sdma0_vi;
181 use_static = false;
182 break;
183 default:
184 WARN(1, "queue type %d", q->properties.type);
185 return -EINVAL;
186 }
187 packet->bitfields3.doorbell_offset =
188 q->properties.doorbell_off;
189
190 packet->mqd_addr_lo =
191 lower_32_bits(q->gart_mqd_addr);
192
193 packet->mqd_addr_hi =
194 upper_32_bits(q->gart_mqd_addr);
195
196 packet->wptr_addr_lo =
197 lower_32_bits((uint64_t)q->properties.write_ptr);
198
199 packet->wptr_addr_hi =
200 upper_32_bits((uint64_t)q->properties.write_ptr);
201
202 return 0;
203}
204
205static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
206 enum kfd_queue_type type,
207 enum kfd_unmap_queues_filter filter,
208 uint32_t filter_param, bool reset,
209 unsigned int sdma_engine)
210{
211 struct pm4_mes_unmap_queues *packet;
212
213 packet = (struct pm4_mes_unmap_queues *)buffer;
214 memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
215
216 packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
217 sizeof(struct pm4_mes_unmap_queues));
218 switch (type) {
219 case KFD_QUEUE_TYPE_COMPUTE:
220 case KFD_QUEUE_TYPE_DIQ:
221 packet->bitfields2.engine_sel =
222 engine_sel__mes_unmap_queues__compute;
223 break;
224 case KFD_QUEUE_TYPE_SDMA:
225 case KFD_QUEUE_TYPE_SDMA_XGMI:
226 packet->bitfields2.engine_sel =
227 engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
228 break;
229 default:
230 WARN(1, "queue type %d", type);
231 return -EINVAL;
232 }
233
234 if (reset)
235 packet->bitfields2.action =
236 action__mes_unmap_queues__reset_queues;
237 else
238 packet->bitfields2.action =
239 action__mes_unmap_queues__preempt_queues;
240
241 switch (filter) {
242 case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
243 packet->bitfields2.queue_sel =
244 queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
245 packet->bitfields2.num_queues = 1;
246 packet->bitfields3b.doorbell_offset0 = filter_param;
247 break;
248 case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
249 packet->bitfields2.queue_sel =
250 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
251 packet->bitfields3a.pasid = filter_param;
252 break;
253 case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
254 packet->bitfields2.queue_sel =
255 queue_sel__mes_unmap_queues__unmap_all_queues;
256 break;
257 case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
258
259 packet->bitfields2.queue_sel =
260 queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
261 break;
262 default:
263 WARN(1, "filter %d", filter);
264 return -EINVAL;
265 }
266
267 return 0;
268
269}
270
271static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
272 uint64_t fence_address, uint32_t fence_value)
273{
274 struct pm4_mes_query_status *packet;
275
276 packet = (struct pm4_mes_query_status *)buffer;
277 memset(buffer, 0, sizeof(struct pm4_mes_query_status));
278
279
280 packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
281 sizeof(struct pm4_mes_query_status));
282
283 packet->bitfields2.context_id = 0;
284 packet->bitfields2.interrupt_sel =
285 interrupt_sel__mes_query_status__completion_status;
286 packet->bitfields2.command =
287 command__mes_query_status__fence_only_after_write_ack;
288
289 packet->addr_hi = upper_32_bits((uint64_t)fence_address);
290 packet->addr_lo = lower_32_bits((uint64_t)fence_address);
291 packet->data_hi = upper_32_bits((uint64_t)fence_value);
292 packet->data_lo = lower_32_bits((uint64_t)fence_value);
293
294 return 0;
295}
296
297
298static int pm_release_mem_v9(uint64_t gpu_addr, uint32_t *buffer)
299{
300 struct pm4_mec_release_mem *packet;
301
302 packet = (struct pm4_mec_release_mem *)buffer;
303 memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
304
305 packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
306 sizeof(struct pm4_mec_release_mem));
307
308 packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
309 packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
310 packet->bitfields2.tcl1_action_ena = 1;
311 packet->bitfields2.tc_action_ena = 1;
312 packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
313
314 packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
315 packet->bitfields3.int_sel =
316 int_sel__mec_release_mem__send_interrupt_after_write_confirm;
317
318 packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
319 packet->address_hi = upper_32_bits(gpu_addr);
320
321 packet->data_lo = 0;
322
323 return 0;
324}
325
326const struct packet_manager_funcs kfd_v9_pm_funcs = {
327 .map_process = pm_map_process_v9,
328 .runlist = pm_runlist_v9,
329 .set_resources = pm_set_resources_vi,
330 .map_queues = pm_map_queues_v9,
331 .unmap_queues = pm_unmap_queues_v9,
332 .query_status = pm_query_status_v9,
333 .release_mem = pm_release_mem_v9,
334 .map_process_size = sizeof(struct pm4_mes_map_process),
335 .runlist_size = sizeof(struct pm4_mes_runlist),
336 .set_resources_size = sizeof(struct pm4_mes_set_resources),
337 .map_queues_size = sizeof(struct pm4_mes_map_queues),
338 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
339 .query_status_size = sizeof(struct pm4_mes_query_status),
340 .release_mem_size = sizeof(struct pm4_mec_release_mem)
341};
342